A data sampling circuit, a delay detection circuit and a memory

Abstract

The embodiments of the present disclosure disclose a data sampling circuit, a delay detection circuit and a memory. The data sampling circuit includes: a first signal path and a second signal path. The first signal path is configured to receive a first signal, process and transmit the first signal. The first signal path has a first delay; the first delay includes: a first physical delay and a compensation delay. The second signal path is configured to receive a second signal, and receive a processed first signal from the first signal path, and sample the second signal according to the processed first signal. The embodiments of the present disclosure can keep the relative delay between the first signal and the second signal stable and avoid sampling failure.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a data sampling circuit, a delay detection circuit and a memory. Background Art

[0002] With the development of integrated circuit technology, the chip frequency needs to be higher and higher to improve the operating speed of the chip. However, as the chip frequency increases, the timing of the signal in the chip becomes more difficult to control, which in turn affects the normal operation of the chip. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a data sampling circuit, a delay detection circuit and a memory, which can keep the relative delay between the first signal and the second signal stable and avoid sampling failure.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a data sampling circuit, which includes: a first signal path, configured to receive a first signal, process and transmit the first signal; the first signal path has a first delay; the first delay includes: a first physical delay and a compensation delay; a second signal path, configured to receive a second signal, and receive the processed first signal from the first signal path, and sample the second signal according to the processed first signal.

[0006] In the above scheme, the first signal path includes: a main path, configured to process and transmit the first signal; the main path has the first physical delay; a compensation unit, coupled to the main path, configured to receive at least one compensation signal from a compensation controller, and generate the compensation delay in response to at least one compensation signal; at least one compensation signal is obtained based on a process angle, voltage conditions and / or temperature conditions.

[0007] In the above scheme, the compensation controller includes: a temperature sensor; at least one of the compensation signals includes: at least one temperature compensation signal; at least one of the temperature compensation signals is obtained by the temperature sensor according to the temperature condition.

[0008] In the above scheme, the compensation unit includes: at least one first load capacitor; the load connection end of at least one first load capacitor is connected to any position of the main path; at least one first load capacitor is configured to receive at least one compensation signal in response, and is activated by being triggered by at least one compensation signal to change the capacitance value to generate the compensation delay.

[0009] In the above scheme, each of the first load capacitors includes: an input subunit, configured to receive the compensation signal and generate two control signals based on the compensation signal; a capacitor subunit, connected to the input subunit, configured to be activated by the two control signals to change the capacitance value of the first load capacitor.

[0010] In the above scheme, the input subunit includes: a first inverter, configured to receive the compensation signal and output the first control signal of the two control signals; a second inverter, the input end of the second inverter is connected to the output end of the first inverter, and the second inverter is configured to output the second control signal of the two control signals.

[0011] In the above scheme, the capacitor subunit includes: a first MOS tube, the source and the drain of the first MOS tube are both connected to the output end of the first inverter; a second MOS tube, the source and the drain of the second MOS tube are both connected to the output end of the second inverter, the gate of the second MOS tube is connected to the gate of the first MOS tube and together serve as the load connection end of the first load capacitor; the type of the second MOS tube is opposite to that of the first MOS tube.

[0012] In the above solution, the first signal is a data selection signal, and the second signal is a data signal.

[0013] An embodiment of the present disclosure also provides a delay detection circuit, which includes: an analog unit, configured to simulate a first delay of a first signal path to generate a delay to be measured; the first delay includes: a first physical delay and a compensation delay; a counting unit, coupled to the analog unit, configured to count the parameters to be measured corresponding to the analog unit to calculate the delay amount of the delay to be measured.

[0014] In the above scheme, the simulation unit includes: a ring oscillation path, configured to simulate the first physical delay; the parameter to be measured includes the number of oscillation cycles corresponding to the ring oscillation path; and a compensation simulation unit, configured to receive at least one compensation signal from a compensation controller, and simulate the compensation delay in response to at least one compensation signal.

[0015] In the above solution, the number of gate-level circuits included in the ring oscillation path is equal to the number of gate-level circuits included in the main path in the first signal path.

[0016] In the above scheme, the compensation simulation unit includes: at least one second load capacitor; the load connection end of at least one second load capacitor is connected to any position of the ring oscillation path; at least one second load capacitor is configured to receive at least one compensation signal in response, and is activated by being triggered by at least one compensation signal to change the capacitance value to simulate the compensation delay.

[0017] In the above scheme, at least one of the second load capacitors corresponds one-to-one to at least one first load capacitor in the first signal path; each of the second load capacitors has the same structure as the corresponding first load capacitor, and receives the same compensation signal as the corresponding first load capacitor.

[0018] In the above scheme, the delay detection circuit also includes: an operation control unit, coupled to the analog unit, configured to receive a start signal and a stop signal, and control the operation time of the analog unit according to the start signal and the stop signal; a storage unit, coupled to the counting unit, configured to store the parameter to be measured.

[0019] The embodiment of the present disclosure further provides a memory, which includes: the data sampling circuit as described in the above solution, and / or the delay detection circuit as described in the above solution.

[0020] In the above solution, the memory is a dynamic random access memory DRAM.

[0021] In the above solution, the dynamic random access memory DRAM complies with the DDR5 memory specification.

[0022] It can be seen that the embodiments of the present disclosure provide a data sampling circuit, a delay detection circuit and a memory. The data sampling circuit includes: a first signal path and a second signal path. The first signal path is configured to receive a first signal, process and transmit the first signal. The first signal path has a first delay; the first delay includes: a first physical delay and a compensation delay. The second signal path is configured to receive a second signal, and receive the processed first signal from the first signal path, and sample the second signal according to the processed first signal. In this way, when the first physical delay changes due to the influence of PVT conditions, the compensation delay will be compensated accordingly to reduce the change of the first delay due to the influence of PVT conditions. Thereby, the relative delay between the first signal and the second signal can be kept stable, avoiding sampling failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of the data sampling circuit provided in the embodiment of the present disclosure Figure 1 ;

[0024] Figure 2 A schematic diagram of the structure of the data sampling circuit provided in the embodiment of the present disclosure Figure 2 ;

[0025] Figure 3 A schematic diagram of the structure of the data sampling circuit provided in the embodiment of the present disclosure Figure 3 ;

[0026] Figure 4 A schematic diagram of the structure of the data sampling circuit provided in the embodiment of the present disclosure Figure 4 ;

[0027] Figure 5 A schematic diagram of the structure of the data sampling circuit provided in the embodiment of the present disclosure Figure 5 ;

[0028] Figure 6 A schematic diagram of the structure of the data sampling circuit provided in the embodiment of the present disclosure Figure 6 ;

[0029] Figure 7 A schematic diagram of the structure of the delay detection circuit provided in the embodiment of the present disclosure Figure 1 ;

[0030] Figure 8 A schematic diagram of the structure of the delay detection circuit provided in the embodiment of the present disclosure Figure 2 ;

[0031] Fig. 9 A schematic diagram of the structure of the delay detection circuit provided in the embodiment of the present disclosure Figure 3 ;

[0032] Fig.10 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0034] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0035] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0037] Figure 1 is an optional structural diagram of a data sampling circuit provided in an embodiment of the present disclosure, such as Figure 1 As shown, the data sampling circuit 80 includes: a first signal path 10 and a second signal path 20. The first signal path 10 is configured to receive a first signal S1, process the first signal S1 and transmit it. The first signal path 10 has a first delay; the first delay includes: a first physical delay and a compensation delay. The second signal path 20 is configured to receive a second signal S2, and receive the processed first signal S1 from the first signal path 10, and sample the second signal S2 according to the processed first signal S1.

[0038] It should be noted that during the transmission process, the signal will be delayed due to the physical delay of the signal path. The physical delay includes the route delay and the circuit delay, wherein the route delay is positively correlated with the route length in the signal path, and the circuit delay is positively correlated with the number of gate-level circuits in the signal path. In the physical delay, the circuit delay is more sensitive than the route delay and is more easily affected by the PVT (Process, Voltage, Temperature) conditions. Therefore, the first physical delay of the first signal path 10 will change due to the influence of the PVT conditions, which will in turn affect the relative delay between the first signal S1 and the second signal S2.

[0039] It should also be noted that the PVT conditions include process conditions, voltage conditions and temperature conditions. Due to process deviations in the chip manufacturing process, such as different doping concentrations, diffusion depths and etching degrees, the process conditions of different chips will be different. Different process conditions can be expressed as different process corners, such as fast corners, typical corners and worst corners. At the same time, the voltage environment and temperature environment in which the chip is working are characterized by voltage conditions and temperature conditions, respectively. Since the data sampling circuit 80 will be integrated into the chip, the PVT conditions corresponding to the chip are the PVT conditions corresponding to the data sampling circuit 80.

[0040] In the embodiment of the present disclosure, since the second signal path 20 samples the second signal S2 according to the processed first signal S1, that is, the processed first signal S1 serves as the sampling clock signal of the second signal S2, the relative delay between the first signal S1 and the second signal S2 needs to remain stable to avoid sampling failure.

[0041] In the embodiment of the present disclosure, the first delay includes the first physical delay and the compensation delay. When the first physical delay is affected by the PVT condition and changes, the compensation delay will be compensated accordingly to reduce the change of the first delay caused by the PVT condition. In this way, the relative delay between the first signal S1 and the second signal S2 can be kept stable, thereby avoiding sampling failure.

[0042] In some embodiments of the present disclosure, Figure 2 As shown, the first signal path 10 includes: a main path 11 and a compensation unit 12. The main path 11 is configured to process and transmit a first signal S1. The main path 11 has a first physical delay. The compensation unit 12 is coupled to the main path 11. The compensation unit 12 is configured to receive at least one compensation signal Sc from a compensation controller, and generate a compensation delay in response to the at least one compensation signal Sc. The at least one compensation signal Sc is obtained according to a PVT condition.

[0043] It should be noted that the coupling described in the present disclosure includes: direct electrical connection, or indirect electrical connection through electrical components, which will not be described in detail below.

[0044] In the embodiment of the present disclosure, the compensation controller generates the compensation signal Sc according to the PVT condition corresponding to the data sampling circuit 80, that is, the compensation controller can generate the compensation signal Sc according to at least one of the process condition, the voltage condition and the temperature condition. Among the PVT conditions, the process condition can be determined during the chip manufacturing process, and the voltage condition and the temperature condition can be measured in real time by the compensation controller.

[0045] It can be understood that, since the compensation signal Sc is generated according to the PVT condition corresponding to the data sampling circuit 80, the compensation unit 12 generates a compensation delay according to the compensation signal Sc, which can compensate for the change of the first physical delay due to the influence of the PVT condition. Thus, the relative delay between the first signal S1 and the second signal S2 can be kept stable, avoiding sampling failure.

[0046] In some embodiments of the present disclosure, the compensation controller includes: a temperature sensor. The at least one compensation signal includes: at least one temperature compensation signal. The at least one temperature compensation signal is obtained by the temperature sensor according to temperature conditions.

[0047] In the embodiment of the present disclosure, the temperature sensor can measure the real-time temperature of the chip in the working state, and determine at least one temperature compensation signal corresponding to the real-time temperature based on the curve of the first physical delay changing with the temperature, and then send the at least one temperature compensation signal to the compensation unit.

[0048] It is understandable that the temperature sensor obtains a temperature compensation signal according to the temperature condition, and then the temperature compensation signal can be used to control the compensation unit to generate a compensation delay to compensate for the change in the first physical delay due to the temperature condition. Thus, the relative delay between the first signal and the second signal can be kept stable, avoiding sampling failure.

[0049] In some embodiments of the present disclosure, Figure 3 As shown, the compensation unit 12 includes: at least one first load capacitor 121. The load connection terminal of the at least one first load capacitor 121 is connected to any position of the main path 11. The at least one first load capacitor 121 is configured to receive at least one compensation signal Sc in response to the at least one compensation signal Sc. <1> ~Sc <n>The trigger activates the capacitor to change the capacitor value to generate a compensation delay.

[0050] In the embodiments of the present disclosure, reference Figure 3 The main path 11 includes a plurality of circuit modules 110, each of which has a different function to process and transmit the first signal S1. These circuit modules 110 will generate physical delays, and the sum of the physical delays generated by all the circuit modules 110 is the first physical delay.

[0051] At the same time, the compensation unit 12 includes at least one first load capacitor 121. The load connection end of at least one first load capacitor 121 is connected to any position of the main path 11. After each first load capacitor 121 is activated, its capacitance value will change, generating a certain load delay. The sum of the load delays generated by all first load capacitors 121 is the compensation delay.

[0052] It should be noted that the load delays generated by the first load capacitors 121 may be the same or different. Since the load delays generated by the first load capacitors 121 are related to the equivalent device size of the first load capacitors 121, the equivalent device sizes of the first load capacitors 121 may be the same or different. Here, the device size may be the channel width-to-length ratio of the transistor. For example, the ratio of the equivalent device sizes of the first load capacitors 121 may be 1:1:1...:1, or 1:2:4...:2:4. n-1 , among which, the latter can make the adjustment range of compensation delay larger than the former.

[0053] In the embodiment of the present disclosure, at least one first load capacitor 121 will correspondingly receive at least one compensation signal Sc <1> ~Sc <n>Each first load capacitor 121 can be activated by the trigger of the corresponding compensation signal, and correspondingly, each first load capacitor 121 can also be deactivated by the trigger of the corresponding compensation signal, and the two triggering conditions correspond to two different levels of the compensation signal. For each first load capacitor 121, when it is in an activated state, it will generate its corresponding load delay, and when it is in a deactivated state, it will not generate the corresponding load delay.

[0054] For example, the high level (i.e., "1") of each compensation signal triggers the activation of the corresponding first load capacitor 121, and the low level (i.e., "0") of each compensation signal triggers the deactivation of the corresponding first load capacitor 121. <1> Sc <n-1>and Sc <n>If they are 1, 0 and 1 respectively, the 1st and nth first load capacitors 121 will be triggered to be activated, and the n-1th first load capacitor 121 will be triggered to stop being activated. At this time, the compensation delay will include the load delay generated by the 1st and nth first load capacitors 121, but will not include the load delay generated by the n-1th first load capacitor 121.

[0055] It is understood that by at least one compensation signal Sc <1> ~Sc <n>, the load delay generated by at least one first load capacitor 121 can be controlled, and then the compensation delay generated by the compensation unit 12 can be controlled. Thus, the change of the first physical delay of the main path 11 due to the influence of the PVT condition can be compensated, so that the relative delay of the first signal S1 and the second signal S2 remains stable, avoiding sampling failure.

[0056] In some embodiments of the present disclosure, Figure 4 As shown, each first load capacitor 121 includes: an input subunit 122 and a capacitor subunit 123. The input subunit 122 is configured to receive the compensation signal Sc and generate two control signals Va and Vb based on the compensation signal Sc. The capacitor subunit 123 is connected to the input subunit 122 and is configured to be activated by the two control signals Va and Vb to change the capacitance value of the first load capacitor 121. Port A of the capacitor subunit 123 serves as the load connection terminal of the first load capacitor 121 and is connected to any position on the main path 11.

[0057] In some embodiments of the present disclosure, Figure 5 As shown, the input subunit 122 includes: a first inverter 124 and a second inverter 125. The first inverter 124 is configured to receive the compensation signal Sc and output the first control signal Va of the two control signals. The input end of the second inverter 125 is connected to the output end of the first inverter 124. The second inverter 125 is configured to output the second control signal Vb of the two control signals.

[0058] The capacitor subunit 123 includes: a first MOS transistor 126 and a second MOS transistor 127. The source and drain of the first MOS transistor 126 are both connected to the output end of the first inverter 124. The source and drain of the second MOS transistor 127 are both connected to the output end of the second inverter 125. The gate of the second MOS transistor 127 is connected to the gate of the first MOS transistor 126 and serves together as the load connection terminal A of the first load capacitor 121. The type of the second MOS transistor 127 is opposite to that of the first MOS transistor 126.

[0059] In the embodiment of the present disclosure, the first MOS transistor 126 and the second MOS transistor 127 are MOS transistors of opposite types, for example, the first MOS transistor 126 is an NMOS transistor, and the second MOS transistor 127 is a PMOS transistor. After the compensation signal Sc passes through the first inverter 124 and the second inverter 125, the first control signal Va and the second control signal Vb are obtained. The first control signal Va and the second control signal Vb have opposite levels, so the first MOS transistor 126 and the second MOS transistor 127 can be turned on at the same time.

[0060] In the disclosed embodiment, the first MOS tube 126 is an NMOS tube, and the second MOS tube 127 is a PMOS tube. When the first load capacitor 121 receives the compensation signal Sc of a high level, the compensation signal Sc passes through the first inverter 124 and the second inverter 125 to obtain the first control signal Va of a low level, and the second control signal is Vb of a high level. Then, the first MOS tube 126 is turned on by the triggering of the first control signal Va, and the gate capacitance of the first MOS tube 126 is changed; the second MOS tube 127 is turned on by the triggering of the second control signal Vb, and the gate capacitance of the second MOS tube 127 is changed. In this way, the capacitance value of the first load capacitor 121 is changed, which has an impact on the delay on the main path, that is, it plays a role in compensating the first delay.

[0061] It can be understood that two MOS tubes of opposite types are used to form a capacitor unit, and at the same time, two inverters are used to provide different voltage levels to the two MOS tubes, so as to change the conduction state of the two MOS tubes and change the capacitance value of the first load capacitor to compensate for the first delay. In this way, the change of the first physical delay of the main path due to the influence of PVT conditions can be compensated, so that the relative delay of the first signal and the second signal remains stable, and sampling failure is avoided.

[0062] In some embodiments of the present disclosure, Figure 6 As shown, the first signal is a data selection signal DQS, and the second signal is a data signal DQ. The main path 11 of the first signal path 10 includes: a buffer 111, a divider 112 and a clock tree 113. The buffer 111, the divider 112 and the clock tree 113 are coupled to each other in sequence. The second signal path 20 includes: a first amplifier 201, a second amplifier 202, an analog adder 203 and a sampler 204. The first amplifier 201, the second amplifier 202, the analog adder 203 and the sampler 204 are coupled to each other in sequence.

[0063] In the embodiments of the present disclosure, reference Figure 6 The buffer 111 is configured to receive the data selection signal DQS and the complementary data selection signal DQSB, and amplify and drive the data selection signal DQS and the complementary data selection signal DQSB to avoid signal strength attenuation. The phase splitter 112 is configured to phase the data selection signal DQS and the complementary data selection signal DQSB to obtain multiple data selection sub-signals with equal phase differences to achieve frequency reduction of the data selection signal DQS. The clock tree 113 is configured to drive multiple data selection sub-signals to avoid signal strength attenuation, and transmit the multiple data selection sub-signals to the sampler 204.

[0064] In the embodiments of the present disclosure, reference Figure 6 , the first amplifier 201 receives the data signal DQ and the reference data signal VREFDQ. The first amplifier 201 and the second amplifier 202 are configured to amplify the data signal DQ. The analog adder 203 is configured to receive the amplified data signal DQ and perform decision feedback equalization processing on the amplified data signal DQ to eliminate intersymbol interference (ISI). The sampler 204 is configured to receive the data signal DQ and multiple data selection sub-signals after decision feedback equalization processing, and sample the data signal DQ according to the multiple data selection sub-signals.

[0065] In the embodiments of the present disclosure, reference Figure 6 , the difference between the first physical delay of the main path 11 of the first signal path 10 and the second physical delay of the second signal path 20 is recorded as TDQS2DQ. When the signal transmitter sends the data selection signal DQS and the data signal DQ, it will impose a certain relative delay on the sending time of the two signals according to TDQS2DQ, that is, a mismatch delay is imposed between the data selection signal DQS and the data signal DQ, for example, the data selection signal DQS is sent first, and then the data signal DQ is sent. In this way, the difference in physical delays on the two signal paths can be compensated, so that during the sampling process, the timing of the data selection signal DQS and the data signal DQ can be matched, so that the sampling process can be completed.

[0066] However, since the main path 11 of the first signal path 10 is easily affected by the PVT condition, the first physical delay is changed. Therefore, TDQS2DQ will also change significantly due to the influence of the PVT condition. Further, if TDQS2DQ increases, the signal transmitter also needs to increase the mismatch delay applied between the data selection signal DQS and the data signal DQ when sending the data selection signal DQS and the data signal DQ. In this way, it will bring a greater burden to the signal transmitter, and even exceed the adjustment range of the signal transmitter for the mismatch delay, causing the mismatch delay to be invalid.

[0067] Continue to refer Figure 6 , the compensation unit 12 will generate a compensation delay according to the compensation signal Sc, and the compensation signal Sc is obtained according to the PVT condition, that is, the compensation unit 12 will generate a compensation delay according to the PVT condition. At the same time, the mismatch delay is obtained according to the difference between the total delay of the first signal path and the total delay of the second signal path; wherein the total delay of the first signal path is the first delay, and the first delay includes the first physical delay and the compensation delay; the total delay of the second signal path is the second physical delay. Therefore, the compensation delay will compensate for the change of the mismatch delay due to the influence of the PVT condition, thereby reducing the mismatch delay imposed by the signal transmitter between the data selection signal DQS and the data signal DQ, so that the mismatch delay is controlled within a certain range. In this way, the effective control of the timing of controlling the data selection signal DQS and the data signal DQ is guaranteed, thereby ensuring that the sampling of the data signal DQ can be effectively carried out.

[0068] Figure 7 is an optional structural diagram of a delay detection circuit provided in an embodiment of the present disclosure, such as Figure 7 As shown, the delay detection circuit 70 includes: an analog unit 30 and a counting unit 40. The analog unit 30 is configured to simulate the first delay of the first signal path to generate a delay to be measured. The first delay includes: a first physical delay and a compensation delay. The counting unit 40 is coupled to the analog unit 30 and configured to count the parameters to be measured corresponding to the analog unit 30 to calculate the delay amount of the delay to be measured.

[0069] In the disclosed embodiment, since the first delay of the first signal path is not easy to measure, the simulation unit 30 can simulate the first delay to generate the delay to be measured, and then the delay amount of the first delay can be determined by calculating the delay amount of the delay to be measured.

[0070] At the same time, the first delay includes the first physical delay and the compensation delay; when the first physical delay is affected by the PVT condition and changes, the compensation delay will be compensated accordingly to reduce the change of the first delay caused by the PVT condition. Accordingly, the simulation unit 30 will simulate the first physical delay and the compensation delay respectively to obtain the delay to be measured.

[0071] In some embodiments of the present disclosure, Figure 7 As shown, the delay detection circuit 70 further includes: an operation control unit 41 and a register unit 42. The operation control unit 41 is coupled to the analog unit 30 and is configured to receive a start signal OSC_1 and a stop signal OSC_2, and control the operation time of the analog unit 30 according to the start signal OSC_1 and the stop signal OSC_2. The register unit 42 is coupled to the counting unit 40 and is configured to register the parameter to be measured.

[0072] In some embodiments of the present disclosure, Figure 8 As shown, the simulation unit 30 includes: a ring oscillation path 31 and a compensation simulation unit 32. The ring oscillation path 31 is configured to simulate a first physical delay. The measured parameter includes the number of oscillation cycles corresponding to the ring oscillation path 31. The compensation simulation unit 32 is configured to receive at least one compensation signal Sc from the compensation controller. <1> ~Sc <n>, in response to at least one compensation signal Sc <1> ~Sc <n>, simulate compensation delay.

[0073] In the present disclosure, Figure 7 and Figure 8 , the operation control unit 41 can control the ring oscillation path 31 to start oscillation in response to the start signal OSC_1. When the ring oscillation path 31 starts to oscillate, the counting unit 40 can count the number of oscillation cycles of the ring oscillation path 31 and store the number of oscillation cycles in the storage unit 42. Furthermore, the operation control unit 41 can control the ring oscillation path 31 to stop oscillation in response to the stop signal OSC_2. The storage unit 42 will store the final number of oscillation cycles for calculating the delay amount of the delay to be measured. Among them, the delay to be measured includes the physical delay of the ring oscillation path 31 and the compensation delay simulated by the compensation simulation unit 32.

[0074] In some embodiments of the present disclosure, reference Figure 8 The number of gate-level circuits included in the ring oscillation path 31 is equal to the number of gate-level circuits included in the main path in the first signal path.

[0075] In the embodiments of the present disclosure, reference Figure 8 , the ring oscillation path 31 includes a plurality of gate-level circuits 310, and the number of gate-level circuits 310 is equal to the number of gate-level circuits included in the main path in the first signal path. At the same time, the routing length in the ring oscillation path 31 can be equal to the routing length of the main path in the first signal path. Since the physical delay includes routing delay and circuit delay, wherein the routing delay is positively correlated with the routing length in the signal path, and the circuit delay is positively correlated with the number of gate-level circuits in the signal path. Therefore, the ring oscillation path 31 and the main path in the first signal path have equal circuit delay and equal routing delay. Furthermore, the ring oscillation path 31 and the main path in the first signal path can have equal physical delay.

[0076] In some embodiments of the present disclosure, reference Figure 8 The compensation simulation unit 32 includes: at least one second load capacitor 321. The load connection terminal of the at least one second load capacitor 321 is connected to any position of the ring oscillation path 31. The at least one second load capacitor 321 is configured to receive at least one compensation signal Sc <1> ~Sc <n>, subject to at least one compensation signal Sc <1> ~Sc <n>It is activated by the trigger and changes the capacitance value to simulate the compensation delay.

[0077] In the embodiments of the present disclosure, reference Figure 8 , at least one second load capacitor 321 corresponds to at least one first load capacitor in the first signal path. Each second load capacitor 321 has the same structure as the first load capacitor corresponding to it, and receives the same compensation signal as the first load capacitor corresponding to it. In other words, each second load capacitor 321 has Figure 4 or Figure 5 In this way, the at least one second load capacitor 321 can generate the same load delay as the at least one first load capacitor, thereby simulating the compensation delay.

[0078] In some embodiments of the present disclosure, the first signal transmitted by the first signal path is a data selection signal DQS, and the second signal transmitted by the second signal path is a data signal DQ. Fig. 9 As shown, the ring oscillation path 31 includes: a buffer 311, a phase splitter 312 and a clock tree 313. That is, the first signal path for transmitting the data selection signal DQS is connected into a ring, and the ring oscillation path 31 is obtained. Since the ring oscillation path 31 and the main path of the first signal path have the same electrical components, the ring oscillation path 31 can simulate the first physical delay.

[0079] For further reference, Figure 7 In the case where the first signal transmitted by the first signal path is the data select signal DQS, the delay detection circuit 70 may be the DQSinterval OSC function (data select signal interval oscillation function module) specified in the DDR5 (5th generation double rate synchronous dynamic random access memory) specification. Accordingly, the operation control unit 41 may be the DQS OSC timer (data select signal oscillation timer) in the DQS interval OSC function, and the analog unit 30 may be the DQS OSC REP (data select signal oscillation replicator) in the DQS interval OSC function. The DQSOSC timer receives the ZQ_OSC_START signal and the ZQ_OSC_STOP signal; furthermore, the DQS OSC timer controls the DQS OSC REP to start oscillation in response to the ZQ_OSC_START signal, and controls the DQS OSCREP to stop oscillation in response to the ZQ_OSC_STOP signal.

[0080] In addition, when the signal transmitter sends the data selection signal DQS and the data signal DQ, it will impose a certain relative delay on the transmission time of the two signals according to TDQS2DQ, that is, a mismatch delay is imposed between the data selection signal DQS and the data signal DQ. Figure 7 The external computing device can obtain the number of oscillation cycles in the register unit 42, calculate the delay amount of the delay to be measured (i.e., the delay amount of the first delay of the first signal path), and send the delay amount of the first delay to the signal transmitter. The signal transmitter can adjust the mismatch delay according to the delay amount of the first delay, so that the timing of the data selection signal DQS and the data signal DQ can match.

[0081] It can be understood that by simulating the first delay, determining the delay amount of the first delay, and feeding back the delay amount of the first delay to the signal transmitter, the signal transmitter can adjust the mismatch delay to match the timing. At the same time, since the first delay includes the first physical delay and the compensation delay, the compensation delay will compensate for the change of the mismatch delay due to the influence of the PVT condition, so that the mismatch delay is controlled within a certain range, thereby ensuring effective control of the timing.

[0082] Fig.10 is an optional structural diagram of a memory provided by an embodiment of the present disclosure, such as Fig.10 As shown, the memory 90 includes: a data sampling circuit 80 and a delay detection circuit 70.

[0083] In some embodiments of the present disclosure, reference Fig.10 , memory 90 is a dynamic random access memory DRAM.

[0084] In some embodiments of the present disclosure, reference Fig.10 , the dynamic random access memory DRAM (ie, memory 90) complies with the DDR5 memory specification.

[0085] It should be noted that, in this article, the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0086] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0087] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A data sampling circuit, characterized in that: The data sampling circuit comprises: A first signal path is configured to receive a first signal, process and transmit the first signal; the first signal path has a first delay; the first delay includes: a first physical delay and a compensation delay; a second signal path configured to receive a second signal, and receive the processed first signal from the first signal path, and sample the second signal according to the processed first signal; Wherein, the first signal path includes: A main path, configured to process and transmit the first signal; the main path having the first physical delay; A compensation unit, coupled to the main path, configured to receive at least one compensation signal from a compensation controller, and generate the compensation delay in response to at least one compensation signal; at least one compensation signal is obtained according to a process angle, a voltage condition and / or a temperature condition; The compensation unit comprises: at least one first load capacitor; A load connection terminal of at least one of the first load capacitors is connected to any position of the main path; At least one of the first load capacitors is configured to receive at least one of the compensation signals in response, be activated by being triggered by at least one of the compensation signals, and change a capacitance value to generate the compensation delay.

2. The data sampling circuit according to claim 1, characterized in that: The compensation controller includes: a temperature sensor; at least one of the compensation signals includes: at least one temperature compensation signal; At least one of the temperature compensation signals is obtained by the temperature sensor according to the temperature condition.

3. The data sampling circuit according to claim 1, characterized in that: Each of the first load capacitors comprises: An input subunit, configured to receive the compensation signal and generate two control signals based on the compensation signal; The capacitor subunit is connected to the input subunit and is configured to be activated by being triggered by the two control signals to change the capacitance value of the first load capacitor.

4. The data sampling circuit according to claim 3, characterized in that: The input subunit comprises: A first inverter is configured to receive the compensation signal and output a first control signal of the two control signals; A second inverter, wherein an input terminal of the second inverter is connected to an output terminal of the first inverter, and the second inverter is configured to output a second control signal of the two control signals.

5. The data sampling circuit according to claim 4, characterized in that: The capacitor subunit comprises: A first MOS transistor, wherein a source and a drain of the first MOS transistor are both connected to an output end of the first inverter; a second MOS tube, wherein the source and the drain of the second MOS tube are both connected to the output end of the second inverter, the gate of the second MOS tube is connected to the gate of the first MOS tube and together serve as the load connection end of the first load capacitor; the type of the second MOS tube is opposite to that of the first MOS tube.

6. The data sampling circuit according to claim 1, characterized in that: The first signal is a data strobe signal, and the second signal is a data signal.

7. A delay detection circuit, characterized in that: The delay detection circuit comprises: A simulation unit is configured to simulate a first delay of a first signal path to generate a delay to be measured; the first delay includes: a first physical delay and a compensation delay; A counting unit, coupled to the simulation unit, configured to count the measured parameters corresponding to the simulation unit to calculate the delay amount of the measured delay; Wherein, the simulation unit comprises: a ring oscillation path configured to simulate the first physical delay; the parameter to be measured includes the number of oscillation cycles corresponding to the ring oscillation path; The compensation simulation unit is configured to receive at least one compensation signal from the compensation controller, and simulate the compensation delay in response to the at least one compensation signal.

8. The delay detection circuit according to claim 7, characterized in that: The number of gate-level circuits included in the ring oscillation path is equal to the number of gate-level circuits included in the main path in the first signal path.

9. The delay detection circuit according to claim 7, characterized in that: The compensation simulation unit includes: at least one second load capacitor; A load connection terminal of at least one of the second load capacitors is connected to any position of the ring oscillation path; At least one of the second load capacitors is configured to receive at least one of the compensation signals in response, and is activated by being triggered by at least one of the compensation signals to change a capacitance value to simulate the compensation delay.

10. The delay detection circuit according to claim 9, characterized in that: At least one of the second load capacitors corresponds one-to-one to at least one of the first load capacitors in the first signal path; Each of the second load capacitors has the same structure as the corresponding first load capacitor, and receives the same compensation signal as the corresponding first load capacitor.

11. The delay detection circuit according to claim 9, characterized in that: The delay detection circuit also includes: An operation control unit, coupled to the simulation unit, configured to receive a start signal and a stop signal, and control the operation time of the simulation unit according to the start signal and the stop signal; The storage unit is coupled to the counting unit and is configured to store the parameter to be measured.

12. A memory, characterized in that: The memory comprises: the data sampling circuit according to any one of claims 1 to 6, and / or the delay detection circuit according to any one of claims 7 to 11.

13. The memory according to claim 12, characterized in that: The memory is a dynamic random access memory DRAM.

14. The memory according to claim 13, characterized in that: The dynamic random access memory DRAM complies with the DDR5 memory specification.

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