Integrated circuit scan test method and system

Abstract

The present invention relates to the field of electronic testing technology, and in particular to a method and system for integrated circuit scan testing. The method comprises the following steps: performing multi-channel scan test design and test point screening optimization processing on an integrated circuit to obtain an integrated circuit scan test optimization point; performing historical operation data collection and fault degree detection on the integrated circuit scan test optimization point to obtain a scan test point historical operation fault degree value; performing comparative judgment and scan testing on the integrated circuit scan test optimization point corresponding to the scan test point historical operation fault degree value according to a preset operation fault degree standard value to obtain integrated circuit high-frequency fault asynchronous test data and integrated circuit low-frequency fault timing test data; performing integrated analysis on the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain integrated circuit scan test integrated data. The present invention can improve the efficiency and accuracy of scan testing.

Description

Technical Field

[0001] The present invention relates to the field of electronic testing technology, and in particular to a method and system for scanning testing of integrated circuits. Background Art

[0002] In today's digital society, integrated circuits play a key role and are widely used in electronic equipment, communication systems, computers and other fields. As the complexity of integrated circuits continues to increase, reliable scan testing of their quality and performance has become a vital task. Traditional scan test methods have been widely used in integrated circuit production. However, with the expansion of integrated circuit scale and the continuous advancement of manufacturing processes, traditional methods are facing challenges such as test efficiency, real-time performance and inaccurate fault location. Summary of the invention

[0003] Based on this, it is necessary for the present invention to provide a method and system for integrated circuit scan testing to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for scanning and testing an integrated circuit comprises the following steps:

[0005] Step S1: performing a multi-channel scan test design on an integrated circuit to obtain a multi-channel scan test path for the integrated circuit; performing a test point screening and optimization process on the multi-channel scan test path for the integrated circuit to obtain an optimized point for the integrated circuit scan test;

[0006] Step S2: collecting historical operation data of the integrated circuit scan test optimization point to obtain the scan test point historical operation data; performing fault degree detection on the scan test point historical operation data to obtain the scan test point historical operation fault degree value; comparing and judging the integrated circuit scan test optimization point corresponding to the scan test point historical operation fault degree value according to the preset operation fault degree standard value to obtain the integrated circuit scan test high-frequency fault point and the integrated circuit scan test low-frequency fault point;

[0007] Step S3: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, an asynchronous scan adjustment test is performed on the integrated circuit scan test high-frequency fault point to obtain the integrated circuit high-frequency fault asynchronous test data;

[0008] Step S4: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, a high-speed timing scan test is performed on the integrated circuit scan test low-frequency fault point to obtain the integrated circuit low-frequency fault timing test data;

[0009] Step S5: Integrate and analyze the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain integrated circuit scan test integrated data.

[0010] The present invention firstly designs a multi-channel scanning test for an integrated circuit by using a multi-channel scanning technology, and can provide an efficient and accurate testing means. Through this technology, scanning signals can be obtained from multiple channels at the same time, thereby realizing a comprehensive scan of the entire integrated circuit, and this comprehensiveness not only improves the test speed, but also enhances the accuracy and reliability of the test. Specifically, by using the multi-channel scanning technology, a large number of multi-channel scanning signals can be captured in a short time, providing the necessary data basis for subsequent testing and analysis, thereby obtaining a multi-channel scanning test path for the integrated circuit, and this path design fully considers the overall structure of the integrated circuit and the interaction between the components, ensuring the comprehensiveness and accuracy of the test. Through this design, the key parameters and performance indicators in the circuit can be effectively captured and analyzed, and the test process is further optimized, thereby providing strong technical support for the performance evaluation and optimization of the integrated circuit. Subsequently, by performing test point screening and optimization processing on the multi-channel scanning test path of the integrated circuit, the purpose of this step is to identify and select the most representative and critical test points to further improve the test efficiency and accuracy. Through careful analysis and screening, resources can be concentrated and focused on the most critical test areas, thereby achieving more accurate and efficient test results, ensuring the comprehensiveness and efficiency of the scan test. Secondly, by collecting historical operation data of the integrated circuit scan test optimization points, detailed historical operation data of the scan test points can be obtained, which includes the performance of each test point in the past operation, thereby providing sufficient basic data for subsequent fault detection and fault degree calculation. In addition, by performing fault degree detection on the historical operation data of the scan test points, the fault degree of each test point in the historical operation can be quantitatively evaluated, providing a specific numerical basis for subsequent optimization judgment. Through the calculation of the fault degree, the operation state of the test point can be more accurately identified, thereby providing a scientific basis for the judgment process. At the same time, according to the preset standard value of the operation fault degree, the integrated circuit scan test optimization points corresponding to the historical operation fault degree value of the scan test point are compared and judged, thereby determining the operation state of each test point. When the historical operation fault degree value is greater than or equal to the preset standard value, it is judged as a high-frequency fault point; conversely, when the historical operation fault degree value is less than the preset standard value, it is judged as a low-frequency fault point. In this way, qualitative judgment can be made according to the specific standard value to accurately distinguish high-frequency and low-frequency fault points, which can improve the accuracy of fault location, thereby providing a targeted direction for subsequent test optimization. Then, according to the judgment results of the previous step, asynchronous scan adjustment test and high-speed timing scan test are performed on the high-frequency fault points and low-frequency fault points of the integrated circuit scan test respectively. In this way, through different test methods, the characteristics of high-frequency and low-frequency faults can be captured more comprehensively, providing more complete test data for subsequent data analysis and comprehensive utilization.Finally, by integrating the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data, we can comprehensively analyze the test results of integrated high-frequency and low-frequency faults, thereby obtaining the integrated data of integrated circuit scan testing. This provides a comprehensive understanding of the entire testing process for the integrated circuit, helps to deeply understand the performance characteristics and potential problems of the integrated circuit, and provides strong support for the interpretation of test results and performance optimization.

[0011] Preferably, the present invention further provides a system for integrated circuit scan testing, which is used to execute the integrated circuit scan testing method as described above, and the integrated circuit scan testing system comprises:

[0012] The integrated circuit test point processing module is used to perform multi-channel scan test design on the integrated circuit to obtain the integrated circuit multi-channel scan test path; perform test point screening and optimization processing on the integrated circuit multi-channel scan test path to obtain the integrated circuit scan test optimization point;

[0013] The scanning test point fault detection module is used to collect historical operation data of the integrated circuit scanning test optimization point to obtain the scanning test point historical operation data; perform fault degree detection on the scanning test point historical operation data to obtain the scanning test point historical operation fault degree value; compare and judge the integrated circuit scanning test optimization point corresponding to the scanning test point historical operation fault degree value according to the preset operation fault degree standard value to obtain the integrated circuit scanning test high-frequency fault point and the integrated circuit scanning test low-frequency fault point;

[0014] A high-frequency fault asynchronous scanning test module is used to perform an asynchronous scanning adjustment test on the high-frequency fault point of the integrated circuit scanning test when the integrated circuit scanning test optimization point is determined to be the high-frequency fault point of the integrated circuit scanning test, so as to obtain the asynchronous test data of the high-frequency fault of the integrated circuit;

[0015] A low-frequency fault high-speed timing test module is used to perform a high-speed timing scan test on the integrated circuit scan test low-frequency fault point when determining that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, so as to obtain the integrated circuit low-frequency fault timing test data;

[0016] The integrated test analysis module is used to perform integrated test analysis on the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain the integrated circuit scan test integrated data.

[0017] In summary, the present invention provides a system for integrated circuit scan testing, which is composed of an integrated circuit test point processing module, a scan test point fault detection module, a high-frequency fault asynchronous scan test module, a low-frequency fault high-speed timing test module and an integrated test analysis module, and can implement any integrated circuit scan test method described in the present invention, and is used to implement an integrated circuit scan test method by combining the operations between computer programs running on each module, and the internal structure of the system cooperates with each other, wherein the integrated circuit test point processing module is a key component, which is intended to design a multi-channel scan test path, so as to comprehensively evaluate the performance of the integrated circuit. Through the carefully designed multi-channel path, the module can improve the test efficiency and ensure that each key area of ​​the integrated circuit is covered. Its optimization processing function can further improve the test effect, ensure that high-quality scan test points are obtained, and provide a reliable data basis for subsequent modules. The scan test point fault detection module is the core part of the entire system, and provides valuable information for the scan test optimization point of the integrated circuit by collecting historical operation data. Through the fault degree detection, the operation fault state of the integrated circuit can be quantified, providing a basis for subsequent decision-making, and the high-frequency fault point and the low-frequency fault point can be accurately identified based on the preset operation fault degree standard value by using the comparison judgment function, providing a clear direction for the subsequent processing process. The high-frequency fault asynchronous scan test module focuses on the asynchronous scan adjustment test of high-frequency fault points. Through the fine test process, the module obtains the asynchronous test data of high-frequency faults of integrated circuits. These data are crucial for in-depth understanding of the performance of integrated circuits under high-frequency conditions and provide substantial support for performance optimization. The low-frequency fault high-speed timing test module focuses on the low-frequency fault points of integrated circuits and obtains relevant data through high-speed timing scan tests. These data can reveal the behavior of integrated circuits under low-frequency conditions and provide important clues for subsequent adjustments and optimizations. The synergy of the two modules enables the system to fully cope with faults at different frequencies, improving the comprehensiveness and practicality of the system. Finally, the integrated test analysis module integrates the high-frequency fault asynchronous test data and the low-frequency fault timing test data, and can provide users with comprehensive integrated circuit scan test integrated data, enabling users to have a more comprehensive and in-depth understanding of the performance and potential problems of integrated circuits. The modular design and collaborative work of the entire system make it a powerful tool that provides all-round support for the testing and optimization of integrated circuits, which can greatly reduce duplication of work and manpower investment, and can quickly and effectively provide a more accurate and efficient integrated circuit scan test process, thereby simplifying the system operation process of integrated circuit scan test. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments thereof made with reference to the following drawings:

[0019] Figure 1 A schematic flow chart of the steps of the integrated circuit scan test method of the present invention;

[0020] Figure 2 for Figure 1 Detailed step flow diagram of step S1;

[0021] Figure 3 for Figure 2 Detailed step flow chart of step S15 in FIG. DETAILED DESCRIPTION

[0022] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0024] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0025] To achieve this, please refer to Figures 1 to 3 The present invention provides a method for scanning an integrated circuit, the method comprising the following steps:

[0026] Step S1: performing a multi-channel scan test design on an integrated circuit to obtain a multi-channel scan test path for the integrated circuit; performing a test point screening and optimization process on the multi-channel scan test path for the integrated circuit to obtain an optimized point for the integrated circuit scan test;

[0027] Step S2: collecting historical operation data of the integrated circuit scan test optimization point to obtain the scan test point historical operation data; performing fault degree detection on the scan test point historical operation data to obtain the scan test point historical operation fault degree value; comparing and judging the integrated circuit scan test optimization point corresponding to the scan test point historical operation fault degree value according to the preset operation fault degree standard value to obtain the integrated circuit scan test high-frequency fault point and the integrated circuit scan test low-frequency fault point;

[0028] Step S3: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, an asynchronous scan adjustment test is performed on the integrated circuit scan test high-frequency fault point to obtain the integrated circuit high-frequency fault asynchronous test data;

[0029] Step S4: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, a high-speed timing scan test is performed on the integrated circuit scan test low-frequency fault point to obtain the integrated circuit low-frequency fault timing test data;

[0030] Step S5: Integrate and analyze the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain integrated circuit scan test integrated data.

[0031] In the embodiment of the present invention, please refer to Figure 1 FIG. 1 is a flow chart of steps of a method for scanning an integrated circuit of the present invention. In this example, the steps of the method for scanning an integrated circuit include:

[0032] Step S1: performing a multi-channel scan test design on an integrated circuit to obtain a multi-channel scan test path for the integrated circuit; performing a test point screening and optimization process on the multi-channel scan test path for the integrated circuit to obtain an optimized point for the integrated circuit scan test;

[0033] The embodiment of the present invention processes the integrated circuit by using multi-channel scanning technology to realize a comprehensive scan of the entire integrated circuit, and obtains scanning signals from multiple channels at the same time. At the same time, the corresponding scanning test stimulus is designed according to the scanning signal obtained by scanning, and the adjusted scanning signal is applied to the integrated circuit. Then, according to the state of the integrated circuit after applying the adjustment signal, the corresponding multi-channel scanning test path is designed to fully design the overall structure of the integrated circuit and the interaction between each component, so as to obtain the integrated circuit multi-channel scanning test path. Finally, by analyzing the topological structure of the designed integrated circuit multi-channel scanning test path to analyze and identify potential test bottlenecks and redundant test situations, the corresponding test point screening standards are formulated to identify and select the most representative and critical test points, and the identified test points are optimized by considering the test coverage to further improve the test efficiency and accuracy, and finally the integrated circuit scanning test optimization points are obtained.

[0034] Step S2: collecting historical operation data of the integrated circuit scan test optimization point to obtain the scan test point historical operation data; performing fault degree detection on the scan test point historical operation data to obtain the scan test point historical operation fault degree value; comparing and judging the integrated circuit scan test optimization point corresponding to the scan test point historical operation fault degree value according to the preset operation fault degree standard value to obtain the integrated circuit scan test high-frequency fault point and the integrated circuit scan test low-frequency fault point;

[0035] The embodiment of the present invention first determines the type of historical operation data of the integrated circuit scan test optimization point to be collected, such as the input / output data, circuit state information, etc. of the integrated circuit scan test optimization point, and at the same time, obtains the historical operation data of the corresponding integrated circuit scan test optimization point from the log file or database according to the determined data type, thereby obtaining the historical operation data of the scan test point. Secondly, by using an appropriate fault detection method (such as statistical analysis, machine learning model, fault detection algorithm) to calculate the degree of the scan test point historical operation data, so as to detect and quantitatively evaluate the fault degree in the historical operation of each scan test point, thereby obtaining the fault degree value of the scan test point historical operation. Then, the calculated historical operation fault degree values ​​of the scan test points are compared and judged by using a preset operation fault degree standard value. If the historical operation fault degree value of the scan test point is greater than or equal to the preset operation fault degree standard value, it means that the fault degree of the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is relatively high, and the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined to be an integrated circuit scan test high-frequency fault point; if the historical operation fault degree value of the scan test point is less than the preset operation fault degree standard value, it means that the fault degree of the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is relatively low, and the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined to be an integrated circuit scan test low-frequency fault point.

[0036] Step S3: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, an asynchronous scan adjustment test is performed on the integrated circuit scan test high-frequency fault point to obtain the integrated circuit high-frequency fault asynchronous test data;

[0037] If the embodiment of the present invention determines that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, it means that the integrated circuit scan test optimization point has a high frequency of failure during operation. Then, the integrated circuit scan test high-frequency fault point is analyzed by using a scan test tool or test equipment to reproduce the operating characteristics of the integrated circuit scan test high-frequency fault point, and set corresponding asynchronous test parameters according to the analyzed operating properties and characteristics, such as sampling rate, test mode, etc. Then, the integrated circuit scan test high-frequency fault point is scanned and adjusted by using the set asynchronous test parameters to more comprehensively understand the fault test information of the high-frequency fault point in an asynchronous environment, and finally obtain the integrated circuit high-frequency fault asynchronous test data.

[0038] Step S4: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, a high-speed timing scan test is performed on the integrated circuit scan test low-frequency fault point to obtain the integrated circuit low-frequency fault timing test data;

[0039] If the embodiment of the present invention determines that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, it means that the frequency of failure of the integrated circuit scan test optimization point during operation is low. Then, the integrated circuit scan test low-frequency fault point is analyzed by using appropriate high-speed timing sampling technology (such as an oscilloscope, a high-speed sampler, etc.) to accurately capture the high-speed timing characteristic information of the integrated circuit scan test low-frequency fault point, and design the parameters of the dynamic timing scan test according to the timing behavior pattern of the high-speed timing characteristic information, including the scan speed, the sampling rate, etc. Then, the integrated circuit scan test low-frequency fault point is scanned and tested according to the designed dynamic timing scan test parameters to simulate the timing changes of the low-frequency fault point in the real-time environment, and finally the integrated circuit low-frequency fault timing test data is obtained.

[0040] Step S5: Integrate and analyze the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain integrated circuit scan test integrated data.

[0041] The embodiment of the present invention first preprocesses the asynchronous test data of high-frequency faults of integrated circuits and the timing test data of low-frequency faults of integrated circuits to eliminate missing values, abnormal values, noise and other data in the test data, and ensure the accuracy and reliability of the data. Secondly, the preprocessed data is analyzed by using a timing data alignment algorithm to eliminate the time difference between the high-frequency fault data and the low-frequency fault data, ensuring that the high-frequency and low-frequency fault test data are consistent in time. Then, according to the correlation between the high-frequency and low-frequency fault point scan tests, the high-frequency and low-frequency fault test data are integrated using a data integration method to comprehensively integrate the characteristics and timing information of the high-frequency and low-frequency fault scan tests to reflect the scan test situation of the entire integrated circuit, and finally obtain the integrated circuit scan test integrated data.

[0042] The present invention firstly designs a multi-channel scanning test for an integrated circuit by using a multi-channel scanning technology, and can provide an efficient and accurate testing means. Through this technology, scanning signals can be obtained from multiple channels at the same time, thereby realizing a comprehensive scan of the entire integrated circuit, and this comprehensiveness not only improves the test speed, but also enhances the accuracy and reliability of the test. Specifically, by using the multi-channel scanning technology, a large number of multi-channel scanning signals can be captured in a short time, providing the necessary data basis for subsequent testing and analysis, thereby obtaining a multi-channel scanning test path for the integrated circuit, and this path design fully considers the overall structure of the integrated circuit and the interaction between the components, ensuring the comprehensiveness and accuracy of the test. Through this design, the key parameters and performance indicators in the circuit can be effectively captured and analyzed, and the test process is further optimized, thereby providing strong technical support for the performance evaluation and optimization of the integrated circuit. Subsequently, by performing test point screening and optimization processing on the multi-channel scanning test path of the integrated circuit, the purpose of this step is to identify and select the most representative and critical test points to further improve the test efficiency and accuracy. Through careful analysis and screening, resources can be concentrated and focused on the most critical test areas, thereby achieving more accurate and efficient test results, ensuring the comprehensiveness and efficiency of the scan test. Secondly, by collecting historical operation data of the integrated circuit scan test optimization points, detailed historical operation data of the scan test points can be obtained, which includes the performance of each test point in the past operation, thereby providing sufficient basic data for subsequent fault detection and fault degree calculation. In addition, by performing fault degree detection on the historical operation data of the scan test points, the fault degree of each test point in the historical operation can be quantitatively evaluated, providing a specific numerical basis for subsequent optimization judgment. Through the calculation of the fault degree, the operation state of the test point can be more accurately identified, thereby providing a scientific basis for the judgment process. At the same time, according to the preset standard value of the operation fault degree, the integrated circuit scan test optimization points corresponding to the historical operation fault degree value of the scan test point are compared and judged, thereby determining the operation state of each test point. When the historical operation fault degree value is greater than or equal to the preset standard value, it is judged as a high-frequency fault point; conversely, when the historical operation fault degree value is less than the preset standard value, it is judged as a low-frequency fault point. In this way, qualitative judgment can be made according to the specific standard value to accurately distinguish high-frequency and low-frequency fault points, which can improve the accuracy of fault location, thereby providing a targeted direction for subsequent test optimization. Then, according to the judgment results of the previous step, asynchronous scan adjustment test and high-speed timing scan test are performed on the high-frequency fault points and low-frequency fault points of the integrated circuit scan test respectively. In this way, through different test methods, the characteristics of high-frequency and low-frequency faults can be captured more comprehensively, providing more complete test data for subsequent data analysis and comprehensive utilization.Finally, by integrating the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data, we can comprehensively analyze the test results of integrated high-frequency and low-frequency faults, thereby obtaining the integrated data of integrated circuit scan testing. This provides a comprehensive understanding of the entire testing process for the integrated circuit, helps to deeply understand the performance characteristics and potential problems of the integrated circuit, and provides strong support for the interpretation of test results and performance optimization.

[0043] Preferably, step S1 comprises the following steps:

[0044] Step S11: performing multi-channel scanning processing on the integrated circuit using a multi-channel scanning technology to obtain a multi-channel scanning signal of the integrated circuit;

[0045] Step S12: performing test excitation processing on the integrated circuit according to the integrated circuit multi-channel scanning signal to obtain integrated circuit multi-channel scanning test excitation feedback data;

[0046] Step S13: dynamically performing scan test adjustment on the integrated circuit multi-channel scan signal according to the integrated circuit multi-channel scan test stimulus feedback data to generate an integrated circuit multi-channel scan test adjustment signal;

[0047] Step S14: designing a scan test path for the integrated circuit based on the integrated circuit multi-channel scan test adjustment signal to obtain a multi-channel scan test path for the integrated circuit;

[0048] Step S15: performing test point screening and optimization processing on the integrated circuit multi-channel scan test path to obtain the integrated circuit scan test optimization point.

[0049] As an embodiment of the present invention, refer to Figure 2 As shown, Figure 1 Detailed step flow diagram of step S1 in FIG. 1 , in this embodiment, step S1 includes the following steps:

[0050] Step S11: performing multi-channel scanning processing on the integrated circuit using a multi-channel scanning technology to obtain a multi-channel scanning signal of the integrated circuit;

[0051] The embodiment of the present invention processes the integrated circuit by using a multi-channel scanning technology to achieve a comprehensive scan of the entire integrated circuit, and simultaneously obtains scanning signals from multiple channels, and finally obtains a multi-channel scanning signal of the integrated circuit.

[0052] Step S12: performing test excitation processing on the integrated circuit according to the integrated circuit multi-channel scanning signal to obtain integrated circuit multi-channel scanning test excitation feedback data;

[0053] The embodiment of the present invention designs corresponding scan test stimuli according to the multi-channel scan signals of the integrated circuit obtained by scanning to ensure that the stimuli can effectively cover various parts on the integrated circuit. Then, by applying the designed scan test stimuli to the integrated circuit, necessary test stimuli are introduced and feedback data is obtained, and finally the multi-channel scan test stimuli feedback data of the integrated circuit is obtained.

[0054] Step S13: dynamically performing scan test adjustment on the integrated circuit multi-channel scan signal according to the integrated circuit multi-channel scan test stimulus feedback data to generate an integrated circuit multi-channel scan test adjustment signal;

[0055] The embodiment of the present invention first analyzes the integrated circuit multi-channel scan test stimulus feedback data to analyze the scan test coverage and performance feedback information, and then dynamically adjusts the integrated circuit multi-channel scan signal according to the feedback information obtained from the analysis to ensure the accuracy and efficiency of the integrated circuit scan test and make it more adaptable to the characteristics of the integrated circuit, and finally generates an integrated circuit multi-channel scan test adjustment signal.

[0056] Step S14: designing a scan test path for the integrated circuit based on the integrated circuit multi-channel scan test adjustment signal to obtain a multi-channel scan test path for the integrated circuit;

[0057] The embodiment of the present invention applies the generated integrated circuit multi-channel scan test adjustment signal to the integrated circuit, and then designs the corresponding multi-channel scan test path according to the state of the integrated circuit after the application of the adjustment signal, so as to fully design the overall structure of the integrated circuit and the interaction between the components, and ensure that the test path can fully cover the function and performance of the integrated circuit, and finally obtain the integrated circuit multi-channel scan test path.

[0058] Step S15: performing test point screening and optimization processing on the integrated circuit multi-channel scan test path to obtain the integrated circuit scan test optimization point.

[0059] The embodiment of the present invention analyzes the topological structure of the designed integrated circuit multi-channel scan test path to analyze and identify potential test bottlenecks and redundant test situations, formulates corresponding test point screening standards to identify and select the most representative and critical test points, and then optimizes the identified test points by considering the test coverage to further improve the test efficiency and accuracy, and finally obtains the integrated circuit scan test optimization points.

[0060] The present invention firstly provides an efficient and accurate testing method by using a multi-channel scanning technology to perform multi-channel scanning processing on an integrated circuit. Through this technology, scanning signals can be obtained from multiple channels at the same time, thereby realizing a comprehensive scan of the entire integrated circuit, and this comprehensiveness not only improves the test speed, but also enhances the accuracy and reliability of the test. Specifically, by using a multi-channel scanning technology, a large number of multi-channel scanning signals can be captured in a short time, thereby providing a necessary data basis for subsequent testing and analysis. Secondly, by performing test excitation processing on the integrated circuit according to the multi-channel scanning signal of the integrated circuit obtained by scanning, the necessary test stimulus can be introduced and feedback data can be obtained. This processing process can not only stimulate the response of each component in the integrated circuit, but also capture the specific characteristics of these responses. By analyzing these feedback data, possible problems or potential fault points in the circuit can be identified, thereby ensuring the reliability and performance of the integrated circuit, and providing necessary data support for subsequent dynamic adjustment and optimization. Then, by dynamically adjusting the integrated circuit multi-channel scan signal according to the integrated circuit multi-channel scan test stimulus feedback data, the scan signal can be finely adjusted according to the real-time test feedback, thereby optimizing the test process and results. This dynamic adjustment ensures the accuracy and efficiency of the integrated circuit scan test, and also provides key technical support for the quality control of the integrated circuit. It can also enhance the accuracy and operability of the scan test, laying the foundation for the next stage of design and optimization. Next, the integrated circuit is scanned and tested based on the adjusted integrated circuit multi-channel scan test adjustment signal. This path design fully considers the overall structure of the integrated circuit and the interaction between the components, ensuring the comprehensiveness and accuracy of the test. Through this design, the key parameters and performance indicators in the circuit can be effectively captured and analyzed, and the test process is further optimized, thereby providing an efficient and reliable test method, providing strong technical support for the performance evaluation and optimization of the integrated circuit. Finally, the test point screening and optimization processing of the integrated circuit multi-channel scan test path is carried out. The purpose of this step is to identify and select the most representative and critical test points to further improve the test efficiency and accuracy. Through meticulous analysis and screening, it is possible to concentrate resources and focus on the most critical test areas, thereby achieving more accurate and efficient test results. In addition, it ensures the effective use of test resources while providing a comprehensive and in-depth perspective on the quality and performance evaluation of integrated circuits.

[0061] Preferably, step S15 comprises the following steps:

[0062] Step S151: performing topological analysis on the multi-channel scan test path of the integrated circuit to obtain a multi-channel scan test path topological structure;

[0063] Step S152: screening and marking test points on the multi-channel scan test path topology structure to obtain integrated circuit scan test points;

[0064] Step S153: Calculate the coverage of the integrated circuit scan test points using a test coverage calculation formula to obtain an integrated circuit scan test coverage value;

[0065] Step S154: Optimizing the integrated circuit scan test points based on the integrated circuit scan test coverage value to obtain the integrated circuit scan test optimization points.

[0066] As an embodiment of the present invention, refer to Figure 3 As shown, Figure 2 Detailed step flow diagram of step S15 in FIG. 1 , in this embodiment, step S15 includes the following steps:

[0067] Step S151: performing topological analysis on the multi-channel scan test path of the integrated circuit to obtain a multi-channel scan test path topological structure;

[0068] The embodiment of the present invention analyzes the multi-channel scan test path of the integrated circuit by using a topology analysis tool to analyze the connection relationship between each channel in the multi-channel scan test path of the integrated circuit, the signal transmission path and other structures, and finally obtains the multi-channel scan test path topology structure.

[0069] Step S152: screening and marking test points on the multi-channel scan test path topology structure to obtain integrated circuit scan test points;

[0070] The embodiment of the present invention formulates corresponding criteria for screening and marking test points by considering the signal transmission path and channel connection relationship in the multi-channel scan test path topology structure, and then marks and screens the required scan test points in the multi-channel scan test path topology structure by using the formulated criteria to ensure that the key paths and nodes are covered, and finally the integrated circuit scan test points are obtained.

[0071] Step S153: Calculate the coverage of the integrated circuit scan test points using a test coverage calculation formula to obtain an integrated circuit scan test coverage value;

[0072] The embodiment of the present invention combines the test coverage area range parameter, the test coverage area space parameter, the test coverage measurement parameter, the test coverage weight parameter, the total test point value, the total testable function value, the weight adjustment parameter, the total test mode value, the test coverage complexity parameter and related parameters to form a suitable test coverage calculation formula to calculate the coverage of the integrated circuit scan test points, so as to quantify the coverage of each test point in the entire test path, and finally obtain the integrated circuit scan test coverage value. In addition, the test coverage calculation formula can also use any test coverage detection algorithm in the field to replace the coverage calculation process, and is not limited to the test coverage calculation formula.

[0073] Step S154: Optimizing the integrated circuit scan test points based on the integrated circuit scan test coverage value to obtain the integrated circuit scan test optimization points.

[0074] The embodiment of the present invention analyzes the calculated integrated circuit scan test coverage value by using a preset scan test coverage threshold to analyze and obtain the integrated circuit scan test points under the corresponding coverage level, and then optimizes the integrated circuit scan test points under the corresponding coverage level by using an optimization method to improve test efficiency, reduce redundant tests, increase coverage, etc., and finally obtain the integrated circuit scan test optimization points.

[0075] The present invention firstly performs a topological analysis on the multi-channel scan test path of the integrated circuit, and can deeply understand the mutual relationship between the test paths, so as to obtain the topological structure of the multi-channel scan test path. This analysis process not only provides a comprehensive understanding of the circuit structure, but also lays a foundation for the selection of subsequent test points and the calculation of test coverage. By understanding the topological relationship between the test paths, the test points can be designed more effectively to ensure the full coverage of the entire circuit, and a strong structural basis can be provided for the selection of the test points, thereby enhancing the comprehensiveness and accuracy of the test. Secondly, by screening and marking the test points of the multi-channel scan test path topological structure, the scan test points of the integrated circuit can be accurately determined. This process combines the information of the topological structure and intelligently selects the most representative and critical test points to ensure the efficiency and accuracy of the test. In this way, through the in-depth analysis of the topological structure, the key nodes in the circuit can be effectively identified, which provides a strong guidance for the marking of the test points. Then, by using the test coverage calculation formula to calculate the coverage of the integrated circuit scan test points, the comprehensiveness of the scan test coverage can be quantified. Through this calculation, the coverage of each test point in the entire test path can be evaluated, so as to understand the comprehensiveness and depth of the test. This quantitative evaluation provides an objective basis for subsequent optimization, accurately reflects the comprehensiveness of the test through mathematical calculations, and provides quantitative indicators for the evaluation of integrated circuit performance. Finally, by optimizing the integrated circuit scan test points based on the calculated integrated circuit scan test coverage value, the efficiency and accuracy of the test can be improved. By analyzing the coverage value, the relatively redundant or unnecessary parts of the test path can be identified and optimized. This optimization can help focus resources on the most critical test areas, thereby improving the efficiency of the test, and can also ensure the optimal use of test resources, while improving the overall effect of the test.

[0076] Preferably, the test coverage calculation formula in step S153 is specifically:

[0077]

[0078] Where C is the integrated circuit scan test coverage value, a is the lower limit of the test coverage area of ​​the integrated circuit scan test point, b is the upper limit of the test coverage area of ​​the integrated circuit scan test point, x is the test coverage area space parameter of the integrated circuit scan test point, n is the number of integrated circuit scan test points, T i is the test coverage measurement parameter of the i-th integrated circuit scan test point, with a value of 0 or 1. iis the test coverage weight parameter of the i-th integrated circuit scan test point, P(x) is the total test point value of the integrated circuit scan test point in the test coverage area space x, S(x) is the total testable function value of the integrated circuit scan test point in the test coverage area space x, m is the number of test modes in the integrated circuit scan test point, Q j is the weight adjustment parameter of the jth test mode in the integrated circuit scan test point, R(x) is the total test mode value of the integrated circuit scan test point in the test coverage area space x, D(x) is the test coverage complexity parameter of the integrated circuit scan test point in the test coverage area space x, and μ is the correction value of the integrated circuit scan test coverage value.

[0079] The present invention constructs a test coverage calculation formula for calculating the coverage of integrated circuit scan test points. The test coverage calculation formula involves the measurement of different test points and test modes, as well as the weight adjustment of different parameters. Such a design makes the calculation of coverage more flexible, and different factors can be adjusted according to actual conditions. Finally, by calculating the test coverage value, the integrated circuit scan test points can be optimized to improve the test coverage, thereby improving the test effect and reliability. The formula fully considers the integrated circuit scan test coverage value C, the lower limit a of the test coverage area range of the integrated circuit scan test point, the upper limit b of the test coverage area range of the integrated circuit scan test point, the test coverage area space parameter x of the integrated circuit scan test point, the number n of the integrated circuit scan test points, and the test coverage measurement parameter T of the i-th integrated circuit scan test point. i , with a value of 0 or 1, the test coverage weight parameter F of the i-th integrated circuit scan test point i , the total test point value P(x) of the integrated circuit scan test point in the test coverage area space x, the total testable function value S(x) of the integrated circuit scan test point in the test coverage area space x, the number of test modes in the integrated circuit scan test point m, the weight adjustment parameter Q of the jth test mode in the integrated circuit scan test point j , the total test pattern value R(x) of the integrated circuit scan test point in the test coverage area space x, the test coverage complexity parameter D(x) of the integrated circuit scan test point in the test coverage area space x, the correction value μ of the integrated circuit scan test coverage value, and a functional relationship is formed according to the mutual correlation between the integrated circuit scan test coverage value C and the above parameters The formula can realize the coverage calculation process of integrated circuit scan test points. At the same time, by introducing the correction value μ of the integrated circuit scan test coverage value, it can be adjusted according to the error situation occurring in the calculation process, thereby improving the accuracy and applicability of the test coverage calculation formula.

[0080] Preferably, step S154 includes the following steps:

[0081] Step S1541: comparing and judging the integrated circuit scan test coverage value according to a preset test coverage threshold, when the integrated circuit scan test coverage value is greater than or equal to the preset test coverage threshold, determining the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value as an integrated circuit test high coverage point;

[0082] The embodiment of the present invention compares and judges the calculated integrated circuit scan test coverage value by using a preset test coverage threshold. If the integrated circuit scan test coverage value is greater than or equal to the preset test coverage threshold, it means that the test coverage of the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value is large, and the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value is determined as an integrated circuit test high coverage point.

[0083] Step S1542: performing redundant test reduction analysis on the integrated circuit test high coverage points to obtain the integrated circuit high coverage redundant test reduction points; performing edge fuzzy optimization on the integrated circuit high coverage redundant test reduction points to obtain the integrated circuit high coverage edge optimization points;

[0084] The embodiment of the present invention first analyzes the integrated circuit scan test points determined as integrated circuit test high coverage points by using a redundant test reduction algorithm to identify unnecessary repeated tests in the integrated circuit test high coverage points and eliminate them, thereby obtaining integrated circuit high coverage redundant test reduction points. Then, the edge of the integrated circuit high coverage redundant test reduction points is optimized by using an edge fuzzy optimization method to optimize the edge conditions of the integrated circuit high coverage redundant test reduction points, and finally obtain the integrated circuit high coverage edge optimization points.

[0085] Step S1543: when the integrated circuit scan test coverage value is less than a preset test coverage threshold, the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value is determined as an integrated circuit test low coverage point;

[0086] In an embodiment of the present invention, if the integrated circuit scan test coverage value is less than a preset test coverage threshold, it means that the test coverage of the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value is relatively small, then the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value is determined as an integrated circuit test low coverage point.

[0087] Step S1544: performing uncovered form detection on the low coverage points of the integrated circuit test to obtain uncovered form data of the integrated circuit test; performing dynamic test adjustment and optimization on the low coverage points of the integrated circuit test according to the uncovered form data of the integrated circuit test to obtain the low coverage dynamic optimization points of the integrated circuit;

[0088] The embodiment of the present invention detects the low coverage point of the integrated circuit test by using a coverage detection algorithm to detect the uncovered form part in the low coverage point, thereby obtaining the uncovered form data of the integrated circuit test. Then, the scan test strategy is adjusted according to the uncovered form part in the uncovered form data of the integrated circuit test, and the low coverage point of the integrated circuit test is dynamically optimized by using the adjusted scan test strategy to improve the test effect of the low coverage point, and finally the low coverage dynamic optimization point of the integrated circuit is obtained.

[0089] Step S1545: Integrate the integrated circuit high coverage edge optimization points and the integrated circuit low coverage dynamic optimization points to obtain the integrated circuit scan test optimization points.

[0090] The embodiment of the present invention integrates integrated circuit high coverage edge optimization points and integrated circuit low coverage dynamic optimization points by using a test point integration method to ensure that the integrated test points can improve test efficiency and accuracy, and finally obtain integrated circuit scan test optimization points.

[0091] The present invention first compares and judges the integrated circuit scan test coverage value according to the preset test coverage threshold. When it is greater than or equal to the preset threshold, the corresponding integrated circuit scan test point is determined as the integrated circuit test high coverage point. The key to this step is that by setting the test coverage threshold, the high coverage test point can be clearly identified, thereby providing a basis for subsequent redundancy reduction and edge optimization. Secondly, by performing redundant test reduction analysis on the integrated circuit test high coverage point, it is helpful to eliminate redundant tests and improve test efficiency, and on this basis, edge fuzzy optimization is performed, and the edge of the high coverage point can be adjusted to further improve the comprehensiveness of the test. The key to this step is that through redundancy reduction and edge fuzzy optimization, the high coverage point can be more accurately located, providing more targeted improvements for the final test optimization. Then, when the test coverage value is lower than the preset threshold, the corresponding integrated circuit scan test point is determined as the integrated circuit test low coverage point, so that the low coverage test point can be identified, providing a basis for subsequent uncovered form detection and dynamic test adjustment. By clarifying the low coverage point, further test optimization can be carried out in a targeted manner. Next, the uncovered form data is obtained by performing uncovered form detection on the low coverage points of the integrated circuit test, and the low coverage points of the integrated circuit test are dynamically adjusted and optimized based on these data. In this way, through the uncovered form detection, the specific characteristics of the low coverage points can be deeply understood, and the test points can be refined and optimized through dynamic test adjustment, thereby improving the comprehensiveness and depth of the test. Finally, by integrating the high coverage edge optimization points of the integrated circuit and the low coverage dynamic optimization points of the integrated circuit, the optimization points of high coverage and low coverage can be integrated, thereby achieving coordinated optimization of the entire test strategy and ensuring the efficiency and comprehensiveness of the test. The key to this step is that it can provide a systematic and holistic method for the final optimization of the test results, thereby enhancing the comprehensive effect and practicality of the test.

[0092] Preferably, step S2 comprises the following steps:

[0093] Step S21: collecting historical operation data of the integrated circuit scan test optimization point to obtain the historical operation data of the scan test point;

[0094] The embodiment of the present invention first determines the type of historical operation data of the integrated circuit scan test optimization point to be collected, such as the input / output data, circuit status information, etc. of the integrated circuit scan test optimization point, and then obtains the historical operation data of the corresponding integrated circuit scan test optimization point from the log file or database according to the determined data type to ensure that it can record the required historical operation data, and finally obtains the historical operation data of the scan test point.

[0095] Step S22: performing fault detection on the historical operation data of the scanning test points to obtain the historical operation fault data of the scanning test points;

[0096] The embodiment of the present invention detects the historical operation data of the scan test points by using appropriate fault detection methods (such as statistical analysis, machine learning models, fault detection algorithms) to detect possible fault conditions in the integrated circuit scan test optimization points, and finally obtains the historical operation fault data of the scan test points.

[0097] Step S23: Calculate the fault degree of the historical running fault data of the scanning test point using the running fault degree calculation formula to obtain the historical running fault degree value of the scanning test point;

[0098] The embodiment of the present invention forms a suitable operation fault degree calculation formula by combining time variable parameters, historical operation fault rate, historical operation fault impact weight parameter, fault attenuation rate, fault attenuation vibration amplitude adjustment parameter, fault attenuation impact weight parameter, system load efficiency, system load impact weight parameter, system load change adjustment parameter and related parameters to calculate the fault degree of the historical operation fault data of the scan test point, so as to quantitatively evaluate the fault degree of each scan test point in the historical operation, and finally obtain the historical operation fault degree value of the scan test point. In addition, the operation fault degree calculation formula can also use any fault degree detection algorithm in the art to replace the fault degree calculation process, and is not limited to the operation fault degree calculation formula.

[0099] The calculation formula for the degree of operation failure is as follows:

[0100]

[0101] Wherein, F(t) is the historical operation fault degree value of the scanning test point at time t, t is the time variable parameter of the historical operation fault data of the scanning test point, t′ is the external integral time variable parameter of the fault degree calculation, t″ is the internal integral time variable parameter of the fault degree calculation, G(t′) is the historical operation fault rate of the historical operation fault data of the scanning test point at time t′, α is the historical operation fault influence weight parameter, N(t′) is the fault attenuation rate of the historical operation fault data of the scanning test point at time t′, γ is the fault attenuation vibration amplitude adjustment parameter, β is the fault attenuation influence weight parameter, L(t″) is the system load efficiency of the historical operation fault data of the scanning test point at time t″, δ is the system load influence weight parameter, ∈ is the system load change adjustment parameter, and η is the correction value of the historical operation fault degree value of the scanning test point;

[0102] The present invention constructs an operation failure degree calculation formula for calculating the failure degree of the historical operation failure data of the scan test point. The operation failure degree calculation formula comprehensively considers the historical operation failure rate, failure attenuation, system load efficiency and the integration of the respective influencing weight parameters, and is used to evaluate the historical operation failure degree of the scan test point. The integral term of the formula can reflect the cumulative efficiency over time, and also considers the dynamic changes of historical data and system load, which can help identify which parts of the integrated circuit need to be scan tested more frequently to improve reliability. The formula fully considers the historical operation fault degree value F(t) of the scanning test point at time t, the time variable parameter t of the historical operation fault data of the scanning test point, the outer integral time variable parameter t′ of the fault degree calculation, the inner integral time variable parameter t″ of the fault degree calculation, the historical operation fault rate G(t′) of the historical operation fault data of the scanning test point at time t′, the historical operation fault influence weight parameter α, the fault attenuation rate N(t′) of the historical operation fault data of the scanning test point at time t′, the fault attenuation vibration amplitude adjustment parameter γ, the fault attenuation influence weight parameter β, the system load efficiency L(t″) of the historical operation fault data of the scanning test point at time t″, the system load influence weight parameter δ, the system load change adjustment parameter ∈, and the correction value η of the historical operation fault degree value of the scanning test point. According to the mutual correlation between the historical operation fault degree value F(t) of the scanning test point at time t and the above parameters, a functional relationship is formed:

[0103]

[0104] The formula can realize the fault degree calculation process of the historical operation fault data of the scanning test point. At the same time, by introducing the correction value η of the historical operation fault degree value of the scanning test point, it can be adjusted according to the error situation occurring in the calculation process, thereby improving the accuracy and applicability of the operation fault degree calculation formula.

[0105] Step S24: Compare and judge the integrated circuit scan test optimization points corresponding to the historical operation fault degree values ​​of the scan test points according to the preset operation fault degree standard value; when the historical operation fault degree value of the scan test point is greater than or equal to the preset operation fault degree standard value, the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined to be an integrated circuit scan test high-frequency fault point; when the historical operation fault degree value of the scan test point is less than the preset operation fault degree standard value, the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined to be an integrated circuit scan test low-frequency fault point.

[0106] The embodiment of the present invention compares and judges the calculated historical operation fault degree values ​​of the scan test points by using a preset operation fault degree standard value. If the historical operation fault degree value of the scan test point is greater than or equal to the preset operation fault degree standard value, it means that the fault degree of the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is relatively high, and the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined to be an integrated circuit scan test high-frequency fault point; if the historical operation fault degree value of the scan test point is less than the preset operation fault degree standard value, it means that the fault degree of the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is relatively low, and the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined to be an integrated circuit scan test low-frequency fault point.

[0107] The present invention firstly acquires detailed historical operation data of the scan test optimization points of the integrated circuit by collecting historical operation data, which includes the performance of each test point in the past operation, thereby providing sufficient basic data for subsequent fault detection and fault degree calculation. Through the comprehensive collection of historical operation data, the operation status of each test point can be deeply understood, laying a solid foundation for the entire test optimization process. Secondly, by performing fault detection on the historical operation data of the scan test points to detect the possible fault conditions therein, the fault information of the test points can be accurately captured, and accurate and reliable input data can be provided for the subsequent fault degree calculation. The accuracy of fault detection is directly related to the reliability and effectiveness of subsequent analysis. Then, by using the operation fault degree calculation formula to calculate the fault degree of the historical operation fault data of the scan test points, the fault degree of each test point in the historical operation can be quantitatively evaluated, and a specific numerical basis can be provided for the subsequent optimization judgment. Through the calculation of the fault degree, the operation status of the test point can be more accurately identified, providing a scientific basis for the optimization judgment. Finally, the historical operation fault degree values ​​of the scan test points are compared and judged according to the preset operation fault degree standard value, thereby determining the operation status of each test point. When the historical operation fault degree value is greater than or equal to the preset standard value, it is judged as a high-frequency fault point; conversely, when the historical operation fault degree value is less than the preset standard value, it is judged as a low-frequency fault point. In this way, a qualitative judgment can be made based on the specific standard value, thereby accurately distinguishing high-frequency and low-frequency fault points, providing targeted direction for subsequent test optimization.

[0108] Preferably, step S3 comprises the following steps:

[0109] Step S31: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, a recurrence scan analysis is performed on the integrated circuit scan test high-frequency fault point to obtain high-frequency fault point recurrence characteristic data;

[0110] If the embodiment of the present invention determines that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, it means that the integrated circuit scan test optimization point has a high frequency of failure during operation. Then, the integrated circuit scan test high-frequency fault point is analyzed by using a scan test tool or test equipment to reproduce the operating characteristics of the integrated circuit scan test high-frequency fault point, including circuit status, signal characteristics, etc., and finally obtain the high-frequency fault point reproduction characteristic data.

[0111] Step S32: performing asynchronous testing on the high-frequency fault point of the integrated circuit scanning test according to the high-frequency fault point recurrence characteristic data to obtain initial asynchronous testing data of the high-frequency fault point;

[0112] The embodiment of the present invention sets corresponding asynchronous test parameters, such as sampling rate, test mode, etc., according to the operating properties and characteristics in the high-frequency fault point reproduction characteristic data, and then uses the set asynchronous test parameters to scan the high-frequency fault point of the integrated circuit for testing, so as to more comprehensively understand the initial performance of the high-frequency fault point in an asynchronous environment, and finally obtain the initial asynchronous test data of the high-frequency fault point.

[0113] Step S33: performing waveform analysis on the initial asynchronous test data of the high-frequency fault point to obtain waveform change data of the asynchronous test of the high-frequency fault point;

[0114] The embodiment of the present invention analyzes the initial asynchronous test data of the high-frequency fault point by using the test signal waveform analysis method, so as to deeply explore the signal waveform characteristics and change rules of the high-frequency fault point in the asynchronous test of the integrated circuit scanning test, and finally obtain the asynchronous test waveform change data of the high-frequency fault point.

[0115] Step S34: Based on the high-frequency fault point asynchronous test waveform change data, a delay program is used to perform a dynamic delay adjustment test on the high-frequency fault point of the integrated circuit scan test to obtain the integrated circuit high-frequency fault asynchronous test data.

[0116] The embodiment of the present invention sets dynamic delay adjustment parameters, such as delay step, test range, etc., according to the signal waveform change law in the asynchronous test waveform change data of the high-frequency fault point, and then uses the set parameters through the delay program to adjust the high-frequency fault point of the integrated circuit scan test, adjust and optimize the timing setting and signal transmission of the asynchronous test to better capture the fault information, and finally obtain the integrated circuit high-frequency fault asynchronous test data.

[0117] The present invention first determines the judgment situation of the integrated circuit scan test optimization point. When the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, the integrated circuit scan test high-frequency fault point is reproduced and scanned for analysis, and the operation characteristics of the high-frequency fault point can be deeply analyzed to obtain the recurrence characteristic data of the high-frequency fault point. This analysis process is beneficial to a comprehensive understanding of the nature and characteristics of the high-frequency fault point, and provides a clear direction for subsequent asynchronous testing. Through this step, the operation law of the high-frequency fault point can be captured more accurately, providing strong support for the collection of subsequent test data. Secondly, by using the high-frequency fault point recurrence characteristic data to perform asynchronous testing on the high-frequency fault point of the integrated circuit scan test, the performance of the high-frequency fault point in an asynchronous environment can be more comprehensively understood, laying the foundation for further waveform analysis and delay adjustment testing. Asynchronous testing provides a more detailed observation of the high-frequency fault point, and provides more information for understanding and solving high-frequency faults. Then, by performing waveform analysis on the initial asynchronous test data of the high-frequency fault point, the waveform change data of the asynchronous test of the high-frequency fault point can be obtained. The key to this step is to deeply explore the waveform characteristics and change rules of high-frequency fault points in asynchronous testing, which provides valuable information for subsequent dynamic delay adjustment tests, so that test conditions can be adjusted more specifically, thereby improving the efficiency and accuracy of high-frequency fault scanning tests. Finally, based on the changes in the waveform change data of the asynchronous test of high-frequency fault points, the delay program is used to perform dynamic delay adjustment tests on the high-frequency fault points of the integrated circuit scanning test, which can more flexibly adjust the test conditions to obtain the asynchronous test data of high-frequency faults of integrated circuits, which helps to better simulate the high-frequency fault conditions in the actual working environment and improve the reliability and adaptability of the test. Through this series of steps, the nature of high-frequency fault points can be fully and deeply understood, and strong support is provided for the subsequent processing process.

[0118] Preferably, step S4 comprises the following steps:

[0119] Step S41: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, a high-speed timing analysis is performed on the integrated circuit scan test low-frequency fault point using a high-speed timing sampling technique to obtain high-speed timing characteristic data of the low-frequency fault point;

[0120] If the embodiment of the present invention determines that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, it means that the frequency of failure of the integrated circuit scan test optimization point during operation is low. Then, the integrated circuit scan test low-frequency fault point is analyzed by using appropriate high-speed timing sampling technology (such as an oscilloscope, high-speed sampler, etc.) to accurately capture the high-speed timing characteristic information of the integrated circuit scan test low-frequency fault point, including the scan test signal rise time, fall time, period, etc., and finally obtain the high-speed timing characteristic data of the low-frequency fault point.

[0121] Step S42: performing a timing pattern analysis on the high-speed timing characteristic data of the low-frequency fault point to obtain the high-speed timing pattern data of the low-frequency fault point;

[0122] The embodiment of the present invention analyzes the high-speed timing characteristic data of the low-frequency fault point obtained by analysis by using a timing pattern recognition algorithm (such as waveform matching, pattern matching, etc.) to identify and understand the timing behavior pattern of the low-frequency fault point, and finally obtain the high-speed timing pattern data of the low-frequency fault point.

[0123] Step S43: performing a dynamic timing scan test on the low-frequency fault point of the integrated circuit scan test according to the high-speed timing mode data of the low-frequency fault point to obtain the low-frequency fault timing test data of the integrated circuit.

[0124] The embodiment of the present invention designs the parameters of the dynamic timing scan test according to the timing behavior pattern in the high-speed timing pattern data of the low-frequency fault point, including the scan speed, sampling rate, etc., and then performs a scan test on the low-frequency fault point of the integrated circuit scan test according to the designed dynamic timing scan test parameters to simulate the timing changes of the low-frequency fault point in the real-time environment, and finally obtain the low-frequency fault timing test data of the integrated circuit.

[0125] The present invention first determines the judgment situation of the integrated circuit scan test optimization point. When the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, the integrated circuit scan test low-frequency fault point is subjected to high-speed timing analysis by using high-speed timing sampling technology, and the high-speed timing characteristic data of the integrated circuit scan test low-frequency fault point can be accurately captured. This process can improve the sensitivity and accuracy of data acquisition by using high-speed timing sampling technology, thereby providing a reliable data basis for subsequent analysis and testing, and can also deeply understand the timing behavior of the low-frequency fault point, providing a reliable basis for targeted optimization. Then, by performing timing pattern analysis on the high-speed timing characteristic data of the low-frequency fault point, the timing behavior pattern of the low-frequency fault point can be identified and understood, thereby revealing potential laws and characteristics. The timing pattern data can provide guidance for subsequent test optimization, so that dynamic timing scan tests can be designed and executed more effectively. Finally, a dynamic timing scan test was performed on the low-frequency fault points of the integrated circuit scan test using the high-speed timing mode data of the low-frequency fault points to obtain the timing test data of the low-frequency faults of the integrated circuit. The key to this step is that through the dynamic timing scan test, the timing changes of the low-frequency fault points can be simulated in a real-time environment to capture more realistic and comprehensive test data. These data help to better understand the dynamic behavior of low-frequency faults, thereby providing substantial support for further analysis and optimization.

[0126] Preferably, step S5 comprises the following steps:

[0127] Step S51: preprocessing and standardizing the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain high-frequency fault asynchronous test standard data and low-frequency fault timing test standard data;

[0128] The embodiment of the present invention first preprocesses the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to eliminate missing values, abnormal values, noise and other data in the test data to ensure the accuracy and reliability of the data. Then, the preprocessed data is standardized by using the Z-score standardization method to ensure the uniformity and standardization of the data format, and finally obtains the high-frequency fault asynchronous test standard data and the low-frequency fault timing test standard data.

[0129] Step S52: using a timing data alignment algorithm to perform timing alignment and synchronization analysis on the high-frequency fault asynchronous test standard data and the low-frequency fault timing test standard data, so as to obtain high-frequency fault test timing synchronization data and low-frequency fault test timing synchronization data;

[0130] The embodiment of the present invention uses a timing data alignment algorithm to analyze the high-frequency fault asynchronous test standard data and the low-frequency fault timing test standard data obtained after standardization processing to eliminate the time difference between the high-frequency fault asynchronous test standard data and the low-frequency fault timing test standard data, ensure that the high-frequency and low-frequency fault test data are consistent in time, and finally obtain high-frequency fault test timing synchronization data and low-frequency fault test timing synchronization data.

[0131] Step S53: Integrate and analyze the high-frequency fault test timing synchronization data and the low-frequency fault test timing synchronization data to obtain integrated circuit scan test integration data.

[0132] The embodiment of the present invention first analyzes the high-frequency fault test timing synchronization data and the low-frequency fault test timing synchronization data by using the correlation analysis technology to analyze and obtain the correlation between the high-frequency and low-frequency fault point scan tests. Then, the high-frequency fault test timing synchronization data and the low-frequency fault test timing synchronization data are processed by using the data integration method according to the correlation between the high-frequency and low-frequency fault point scan tests to comprehensively integrate the characteristics and timing information of the high-frequency and low-frequency fault scan tests to reflect the scan test situation of the entire integrated circuit, and finally obtain the integrated circuit scan test integration data.

[0133] The present invention firstly pre-processes and standardizes the high-frequency fault asynchronous test data of the integrated circuit and the low-frequency fault timing test data of the integrated circuit, so as to realize the unified format and specification of the data, thereby obtaining the high-frequency fault asynchronous test standard data and the low-frequency fault timing test standard data, which can ensure the consistency and comparability of the data and provide a reliable basis for subsequent analysis and comparison. The process of pre-processing and standardization can play an important role in improving the quality of data and ensuring the consistency, and lays a foundation for further analysis and comprehensive utilization. Then, by using the timing data alignment algorithm, the high-frequency fault asynchronous test standard data and the low-frequency fault timing test standard data are subjected to timing alignment and synchronous analysis, which can solve the timing difference between the asynchronous data, thereby obtaining the high-frequency fault test timing synchronization data and the low-frequency fault test timing synchronization data, and this synchronous analysis process helps to eliminate the time difference between the data, so that the high-frequency and low-frequency fault test data are more consistent in time, and provide an accurate time reference for the subsequent comprehensive analysis, and can also improve the comparability of the data and the accuracy of the analysis, so that the data is more practical and has practical guiding significance. Finally, by integrating and analyzing the high-frequency fault test timing synchronization data and the low-frequency fault test timing synchronization data, the integrated data of the integrated circuit scan test can be obtained. These data combine the characteristics and timing information of high-frequency and low-frequency faults, and can provide a comprehensive understanding of the entire test process, revealing the correlation and combined effects between high-frequency and low-frequency faults, which provides a basis for deeper test optimization and performance improvement, enabling a more comprehensive and accurate understanding of the test results and performance characteristics of integrated circuits.

[0134] Preferably, the present invention further provides a system for integrated circuit scan testing, which is used to execute the integrated circuit scan testing method as described above, and the integrated circuit scan testing system comprises:

[0135] The integrated circuit test point processing module is used to perform multi-channel scan test design on the integrated circuit to obtain the integrated circuit multi-channel scan test path; perform test point screening and optimization processing on the integrated circuit multi-channel scan test path to obtain the integrated circuit scan test optimization point;

[0136] The scanning test point fault detection module is used to collect historical operation data of the integrated circuit scanning test optimization point to obtain the scanning test point historical operation data; perform fault degree detection on the scanning test point historical operation data to obtain the scanning test point historical operation fault degree value; compare and judge the integrated circuit scanning test optimization point corresponding to the scanning test point historical operation fault degree value according to the preset operation fault degree standard value to obtain the integrated circuit scanning test high-frequency fault point and the integrated circuit scanning test low-frequency fault point;

[0137] A high-frequency fault asynchronous scanning test module is used to perform an asynchronous scanning adjustment test on the high-frequency fault point of the integrated circuit scanning test when the integrated circuit scanning test optimization point is determined to be the high-frequency fault point of the integrated circuit scanning test, so as to obtain the asynchronous test data of the high-frequency fault of the integrated circuit;

[0138] A low-frequency fault high-speed timing test module is used to perform a high-speed timing scan test on the integrated circuit scan test low-frequency fault point when determining that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, so as to obtain the integrated circuit low-frequency fault timing test data;

[0139] The integrated test analysis module is used to perform integrated test analysis on the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain the integrated circuit scan test integrated data.

[0140] In summary, the present invention provides a system for integrated circuit scan testing, which is composed of an integrated circuit test point processing module, a scan test point fault detection module, a high-frequency fault asynchronous scan test module, a low-frequency fault high-speed timing test module and an integrated test analysis module, and can implement any integrated circuit scan test method described in the present invention, and is used to implement an integrated circuit scan test method by combining the operations between computer programs running on each module, and the internal structure of the system cooperates with each other, wherein the integrated circuit test point processing module is a key component, which is intended to design a multi-channel scan test path, so as to comprehensively evaluate the performance of the integrated circuit. Through the carefully designed multi-channel path, the module can improve the test efficiency and ensure that each key area of ​​the integrated circuit is covered. Its optimization processing function can further improve the test effect, ensure that high-quality scan test points are obtained, and provide a reliable data basis for subsequent modules. The scan test point fault detection module is the core part of the entire system, and provides valuable information for the scan test optimization point of the integrated circuit by collecting historical operation data. Through the fault degree detection, the operation fault state of the integrated circuit can be quantified, providing a basis for subsequent decision-making, and the high-frequency fault point and the low-frequency fault point can be accurately identified based on the preset operation fault degree standard value by using the comparison judgment function, providing a clear direction for the subsequent processing process. The high-frequency fault asynchronous scan test module focuses on the asynchronous scan adjustment test of high-frequency fault points. Through the fine test process, the module obtains the asynchronous test data of high-frequency faults of integrated circuits. These data are crucial for in-depth understanding of the performance of integrated circuits under high-frequency conditions and provide substantial support for performance optimization. The low-frequency fault high-speed timing test module focuses on the low-frequency fault points of integrated circuits and obtains relevant data through high-speed timing scan tests. These data can reveal the behavior of integrated circuits under low-frequency conditions and provide important clues for subsequent adjustments and optimizations. The synergy of the two modules enables the system to fully cope with faults at different frequencies, improving the comprehensiveness and practicality of the system. Finally, the integrated test analysis module integrates the high-frequency fault asynchronous test data and the low-frequency fault timing test data, and can provide users with comprehensive integrated circuit scan test integrated data, enabling users to have a more comprehensive and in-depth understanding of the performance and potential problems of integrated circuits. The modular design and collaborative work of the entire system make it a powerful tool that provides all-round support for the testing and optimization of integrated circuits, which can greatly reduce duplication of work and manpower investment, and can quickly and effectively provide a more accurate and efficient integrated circuit scan test process, thereby simplifying the system operation process of integrated circuit scan test.

[0141] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0142] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for scanning an integrated circuit, characterized in that: The following steps are involved: Step S1: Designing a multi-channel scan test path for an integrated circuit to obtain a multi-channel scan test path for the integrated circuit; Performing test point screening and optimization processing on the integrated circuit multi-channel scan test path to obtain the integrated circuit scan test optimization point; wherein step S1 includes the following steps: Step S11: performing multi-channel scanning processing on the integrated circuit using a multi-channel scanning technology to obtain a multi-channel scanning signal of the integrated circuit; Step S12: performing test excitation processing on the integrated circuit according to the integrated circuit multi-channel scanning signal to obtain integrated circuit multi-channel scanning test excitation feedback data; Step S13: dynamically performing scan test adjustment on the integrated circuit multi-channel scan signal according to the integrated circuit multi-channel scan test stimulus feedback data to generate an integrated circuit multi-channel scan test adjustment signal; Step S14: designing a scan test path for the integrated circuit based on the integrated circuit multi-channel scan test adjustment signal to obtain a multi-channel scan test path for the integrated circuit; Step S15: performing test point screening and optimization processing on the integrated circuit multi-channel scan test path to obtain the integrated circuit scan test optimization point; Step S2: collecting historical operation data of the integrated circuit scan test optimization point to obtain the scan test point historical operation data; performing fault degree detection on the scan test point historical operation data to obtain the scan test point historical operation fault degree value; comparing and judging the integrated circuit scan test optimization point corresponding to the scan test point historical operation fault degree value according to the preset operation fault degree standard value to obtain the integrated circuit scan test high-frequency fault point and the integrated circuit scan test low-frequency fault point; wherein step S2 includes the following steps: Step S21: collecting historical operation data of the integrated circuit scan test optimization point to obtain the historical operation data of the scan test point; Step S22: performing fault detection on the historical operation data of the scanning test points to obtain the historical operation fault data of the scanning test points; Step S23: Calculate the fault degree of the historical running fault data of the scanning test point using the running fault degree calculation formula to obtain the historical running fault degree value of the scanning test point; The calculation formula for the degree of operation failure is as follows: ； In the formula, For in time The historical operation fault degree value of the scan test point at The time variable parameters of the historical run fault data of the scan test point, is the external integral time variable parameter for fault severity calculation, is the internal integration time variable parameter for fault severity calculation, For scanning test point history run fault data in time The historical operating failure rate at is the weight parameter of historical operation failure impact, For scanning test point history run fault data in time The fault decay rate at Adjust the parameters for fault attenuation vibration amplitude, is the fault attenuation impact weight parameter, For scanning test point history run fault data in time The system load efficiency at is the system load impact weight parameter, Adjust parameters for system load changes, It is the correction value of the historical operation fault degree value of the scanning test point; Step S24: comparing and judging the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point according to the preset operation fault degree standard value; when the historical operation fault degree value of the scan test point is greater than or equal to the preset operation fault degree standard value, the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined as an integrated circuit scan test high-frequency fault point; when the historical operation fault degree value of the scan test point is less than the preset operation fault degree standard value, the integrated circuit scan test optimization point corresponding to the historical operation fault degree value of the scan test point is determined as an integrated circuit scan test low-frequency fault point; Step S3: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, an asynchronous scan adjustment test is performed on the integrated circuit scan test high-frequency fault point to obtain the integrated circuit high-frequency fault asynchronous test data; Step S4: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, a high-speed timing scan test is performed on the integrated circuit scan test low-frequency fault point to obtain the integrated circuit low-frequency fault timing test data; Step S5: integrating and analyzing the high-frequency fault asynchronous test data of the integrated circuit and the low-frequency fault timing test data of the integrated circuit to obtain integrated circuit scan test integrated data; wherein step S5 includes the following steps: Step S51: preprocessing and standardizing the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain high-frequency fault asynchronous test standard data and low-frequency fault timing test standard data; Step S52: using a timing data alignment algorithm to perform timing alignment and synchronization analysis on the high-frequency fault asynchronous test standard data and the low-frequency fault timing test standard data, so as to obtain high-frequency fault test timing synchronization data and low-frequency fault test timing synchronization data; Step S53: Integrate and analyze the high-frequency fault test timing synchronization data and the low-frequency fault test timing synchronization data to obtain integrated circuit scan test integration data.

2. The integrated circuit scan test method according to claim 1, characterized in that: Step S15 includes the following steps: Step S151: performing topological analysis on the multi-channel scan test path of the integrated circuit to obtain a multi-channel scan test path topological structure; Step S152: screening and marking test points on the multi-channel scan test path topology structure to obtain integrated circuit scan test points; Step S153: Calculate the coverage of the integrated circuit scan test points using a test coverage calculation formula to obtain an integrated circuit scan test coverage value; Step S154: Optimizing the integrated circuit scan test points based on the integrated circuit scan test coverage value to obtain the integrated circuit scan test optimization points.

3. The integrated circuit scan test method according to claim 2, characterized in that: The test coverage calculation formula in step S153 is specifically: ； In the formula, is the integrated circuit scan test coverage value, It is the lower limit of the test coverage area of ​​the integrated circuit scanning test points. The upper limit of the test coverage area of ​​the integrated circuit scan test points. The test coverage area spatial parameters for the integrated circuit scan test points, The number of test points scanned for the integrated circuit, For the The test coverage measurement parameter of the integrated circuit scan test point is 0 or 1. For the Test coverage weight parameters for integrated circuit scan test points, Scan test points for integrated circuits in the test coverage area space The total test point value within Scan test points for integrated circuits in the test coverage area space The total testable functional value within Scan the number of test patterns in the test points of the integrated circuit, Scan the test points for the integrated circuit The weight adjustment parameters of the test patterns, Scan test points for integrated circuits in the test coverage area space Total test pattern values ​​within, Scan test points for integrated circuits in the test coverage area space The test coverage complexity parameter within Correction value for integrated circuit scan test coverage value.

4. The integrated circuit scan test method according to claim 2, characterized in that: Step S154 includes the following steps: Step S1541: comparing and judging the integrated circuit scan test coverage value according to a preset test coverage threshold, when the integrated circuit scan test coverage value is greater than or equal to the preset test coverage threshold, determining the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value as an integrated circuit test high coverage point; Step S1542: performing redundant test reduction analysis on the integrated circuit test high coverage points to obtain the integrated circuit high coverage redundant test reduction points; performing edge fuzzy optimization on the integrated circuit high coverage redundant test reduction points to obtain the integrated circuit high coverage edge optimization points; Step S1543: when the integrated circuit scan test coverage value is less than a preset test coverage threshold, the integrated circuit scan test point corresponding to the integrated circuit scan test coverage value is determined as an integrated circuit test low coverage point; Step S1544: performing uncovered form detection on the low coverage points of the integrated circuit test to obtain uncovered form data of the integrated circuit test; performing dynamic test adjustment and optimization on the low coverage points of the integrated circuit test according to the uncovered form data of the integrated circuit test to obtain the low coverage dynamic optimization points of the integrated circuit; Step S1545: Integrate the integrated circuit high coverage edge optimization points and the integrated circuit low coverage dynamic optimization points to obtain the integrated circuit scan test optimization points.

5. The integrated circuit scan test method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test high-frequency fault point, a recurrence scan analysis is performed on the integrated circuit scan test high-frequency fault point to obtain high-frequency fault point recurrence characteristic data; Step S32: performing asynchronous testing on the high-frequency fault point of the integrated circuit scanning test according to the high-frequency fault point recurrence characteristic data to obtain initial asynchronous testing data of the high-frequency fault point; Step S33: performing waveform analysis on the initial asynchronous test data of the high-frequency fault point to obtain waveform change data of the asynchronous test of the high-frequency fault point; Step S34: Based on the high-frequency fault point asynchronous test waveform change data, a delay program is used to perform a dynamic delay adjustment test on the high-frequency fault point of the integrated circuit scan test to obtain the integrated circuit high-frequency fault asynchronous test data.

6. The integrated circuit scan test method according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: when it is determined that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, a high-speed timing analysis is performed on the integrated circuit scan test low-frequency fault point using a high-speed timing sampling technique to obtain high-speed timing characteristic data of the low-frequency fault point; Step S42: performing a timing pattern analysis on the high-speed timing characteristic data of the low-frequency fault point to obtain the high-speed timing pattern data of the low-frequency fault point; Step S43: Performing a dynamic timing scan test on the low-frequency fault point of the integrated circuit scan test according to the high-speed timing mode data of the low-frequency fault point to obtain the low-frequency fault timing test data of the integrated circuit.

7. A system for scanning and testing an integrated circuit, characterized in that: A method for performing an integrated circuit scan test as claimed in claim 1, wherein the integrated circuit scan test system comprises: The integrated circuit test point processing module is used to perform multi-channel scan test design on the integrated circuit to obtain the integrated circuit multi-channel scan test path; perform test point screening and optimization processing on the integrated circuit multi-channel scan test path to obtain the integrated circuit scan test optimization point; The scanning test point fault detection module is used to collect historical operation data of the integrated circuit scanning test optimization point to obtain the scanning test point historical operation data; perform fault degree detection on the scanning test point historical operation data to obtain the scanning test point historical operation fault degree value; compare and judge the integrated circuit scanning test optimization point corresponding to the scanning test point historical operation fault degree value according to the preset operation fault degree standard value to obtain the integrated circuit scanning test high-frequency fault point and the integrated circuit scanning test low-frequency fault point; A high-frequency fault asynchronous scanning test module is used to perform an asynchronous scanning adjustment test on the high-frequency fault point of the integrated circuit scanning test when the integrated circuit scanning test optimization point is determined to be the high-frequency fault point of the integrated circuit scanning test, so as to obtain the asynchronous test data of the high-frequency fault of the integrated circuit; A low-frequency fault high-speed timing test module is used to perform a high-speed timing scan test on the integrated circuit scan test low-frequency fault point when determining that the integrated circuit scan test optimization point is the integrated circuit scan test low-frequency fault point, so as to obtain the integrated circuit low-frequency fault timing test data; The integrated test analysis module is used to perform integrated test analysis on the integrated circuit high-frequency fault asynchronous test data and the integrated circuit low-frequency fault timing test data to obtain the integrated circuit scan test integrated data.

Images