Method, apparatus, device, and storage medium for designing a chip

Abstract

According to embodiments of the present disclosure, methods, apparatuses, devices and storage media for designing a chip are provided. The method includes selecting a first memory cell from a set of candidate memory cells for a designed chip, the first memory cell having a first transmission latency that is less than a threshold transmission latency. The method includes determining a timing margin associated with a signal path in the chip that includes the first memory cell. The method includes replacing the first memory cell with a second memory cell from the set of candidate memory cells in the chip based on the timing margin, the second memory cell having a higher voltage threshold than the first memory cell. In this way, the design cycle of the chip is not affected, and the power consumption of the final chip product is reduced.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure generally relate to the field of semiconductors, and in particular to a method, an apparatus, a device and a computer readable storage medium for designing a chip. BACKGROUND

[0002] With the development of Moore's law, the process of semiconductor is getting smaller and smaller. Currently, there are usually a large number of various semiconductor devices in a die of a chip, such as hundreds of millions of standard cells, tens of thousands of memory cells, and hundreds of hard intellectual property cores (IP cores), etc. Among these semiconductor devices, the leakage power consumption of the memory cells such as static random access memory (SRAM) accounts for a large proportion in the total leakage power consumption of the chip, for example, more than 30%. Therefore, reasonable selection of the memory cells to reduce the power consumption is important for chip design. SUMMARY

[0003] In a first aspect of the present disclosure, a method for designing a chip is provided. The method comprises: selecting a first memory cell from a set of candidate memory cells for the designed chip, the first memory cell having a first transmission delay less than a threshold transmission delay; determining a timing margin associated with a signal path in the chip including the first memory cell; and replacing the first memory cell with a second memory cell from the set of candidate memory cells in the chip based on the timing margin, the second memory cell having a higher voltage threshold than the first memory cell.

[0004] In a second aspect of the present disclosure, an apparatus for evaluating a designed chip is provided. The apparatus comprises: a memory cell selection module configured to select a first memory cell from a set of candidate memory cells for the designed chip, the first memory cell having a first transmission delay less than a threshold transmission delay; a timing margin determination module configured to determine a timing margin associated with a signal path in the chip including the first memory cell; and a memory cell replacement module configured to replace the first memory cell with a second memory cell from the set of candidate memory cells in the chip based on the timing margin, the second memory cell having a higher voltage threshold than the first memory cell.

[0005] In a third aspect of the present disclosure, an electronic device is provided. The device comprises at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit. The instructions, when executed by the at least one processing unit, cause the device to perform the method of the first aspect.

[0006] In a fourth aspect of the present disclosure, a computer readable storage medium is provided. The computer readable storage medium has stored thereon a computer program, the computer program being executable by a processor to implement the method of the first aspect.

[0007] It is to be understood that the content described in this section is not intended to limit key or critical features of the embodiments of the present disclosure, nor does it aim to restrict the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above-mentioned and other features and advantages of various embodiments of the present disclosure will become more apparent by reference to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, like reference numerals denote like elements, wherein:

[0009] Figure 1 A schematic diagram illustrating an example environment in which embodiments of the present disclosure can be implemented is shown;

[0010] Figure 2 A schematic diagram illustrating an example flow of storage unit determination according to some embodiments of the present disclosure is shown;

[0011] Figure 3 A schematic diagram illustrating a portion of an initial version chip according to some embodiments of the present disclosure is shown;

[0012] Figure 4 A schematic diagram illustrating derivation of timing margin according to some embodiments of the present disclosure is shown;

[0013] Figure 5 A flow diagram illustrating an example process of replacing storage units according to some embodiments of the present disclosure is shown;

[0014] Figure 6 A schematic diagram illustrating a portion of a designed chip according to some embodiments of the present disclosure is shown;

[0015] Figure 7 A flow diagram illustrating a process of designing a chip according to some embodiments of the present disclosure is shown;

[0016] Figure 8 A block diagram illustrating an apparatus for designing a chip according to some embodiments of the present disclosure is shown; and

[0017] Figure 9 A block diagram of an apparatus capable of implementing various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0018] Embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be interpreted as being limited to the embodiments set forth herein; rather, these embodiments are provided so as to more completely and thoroughly understand the present disclosure. It is understood that the drawings and embodiments of the present disclosure are for exemplary purposes only and are not intended to limit the scope of the present disclosure.

[0019] In the description of embodiments of the present disclosure, the term "includes" and its derivatives mean "including but not limited to". The term "based on" means "based, at least in part, on". The term "one embodiment" or "the embodiment" means "at least one embodiment". The term "some embodiments" means "at least some embodiments". Other explicit or implicit definitions can also be included below. The terms "first", "second", etc. can refer to different or the same objects. Other explicit and implicit definitions can also be included below.

[0020] As used herein, unless explicitly stated as a physical chip or chip product, the term "designed chip", "chip", "initial version chip" or similar terms refer to an electronic representation of a physical chip or chip product, such as a representation in an electronic design automation (EDA) tool. Similarly, unless explicitly stated, the term "cell" or "device" refers to an electronic representation of a physical cell or physical device.

[0021] As used herein, the term "static power consumption" refers to power consumption due to leakage current when a circuit is in a standby or inactive state. In this document, the terms "static power consumption" and "leakage power consumption" are used interchangeably.

[0022] As used herein, the term "standard cell" refers to a basic unit that provides a Boolean logic function or a storage function. Standard cells can include combinational logic cells, sequential logic cells, or other special cells, etc. Combinational logic cells can include, but are not limited to, inverters, buffers, AND gates, OR gates, multiplexers, arithmetic units, etc. Sequential logic cells can include, but are not limited to, flip-flops, registers, latches, etc.

[0023] Example Environment

[0024] Figure 1A schematic diagram showing an example environment 100 in which embodiments of the present disclosure can be implemented is shown. In the environment 100, a computing device 110 obtains a candidate memory cell set 101. The memory cells in the candidate memory cell set 101 satisfy the requirements of a designed chip on the memory cells. The requirements can relate to aspects such as size, data width, speed, functionality (e.g., repair functionality, dual-port functionality, hold time) of the memory cells, etc. In some embodiments, the candidate memory cell set 101 can be generated by the computing device 110. The computing device 110 can select the candidate memory cells that satisfy the requirements of the designed chip from a list of memory cells provided by a vendor according to the requirements of the designed chip on the memory cells. Alternatively, in some embodiments, the candidate memory cell set 101 can be received externally by the computing device 110.

[0025] The memory cells can be any suitable type of memory cells on-chip. For example, the memory cells can comprise SRAM. Alternatively, the memory cells can comprise other types of memory. The scope of the present disclosure is not limited in this respect.

[0026] A design system 120 for designing a chip is deployed in the computing device 110. The design system 120 generates a designed chip 102. The chip 102 comprises a plurality of memory cells 150-1, 150-2, 150-3, …, 150-N, which are also referred to individually or collectively as memory cells 150, where N is a positive integer. The design system 120 determines those memory cells 150 to be included in the chip 102 from the candidate memory cell set 101.

[0027] The memory cells have a variety of properties. The properties of the memory cells need to be considered by the design system 120 when selecting the memory cells 150. The memory cells have an intrinsic transfer delay TCQ, which indicates the transfer time from a clock port (CLK) to a data output port (Q) of the memory cell. The smaller the transfer delay, the faster the speed of the memory cell. There is a certain difference in length between the transmit clock path and the capture clock path, and there is also a certain delay in the propagation of the signal from the output port of the memory cell to the destination. In view of this, in order to meet the requirement of the setup time check, a certain margin needs to be left for the transfer delay TCQ compared to the clock period.

[0028] The memory cells also have a property TCC, which indicates the minimum clock period supported by the memory cell. The clock signal propagates from the clock source through the clock tree, and it takes a certain time for the flip between high and low levels, so the real period of the clock signal on the clock port of the memory cell can be smaller than the ideal period. In view of this, a certain margin also needs to be left for TCC compared to the clock period.

[0029] The storage cells also have voltage thresholds (VT). The input voltage corresponding to the midpoint of the sharp change transition region of the output voltage in the transfer characteristic curve is generally referred to as the voltage threshold. The storage cells can be classified according to the voltage thresholds. The candidate storage cell set 101 can include storage cells of any voltage threshold type.

[0030] In one example, the candidate storage cell set 101 can include storage cells of a low voltage threshold (LVT) type (which is also referred to simply as LVT storage cells) and storage cells of a standard voltage threshold (SVT) type (which is also referred to simply as SVT storage cells). The voltage threshold of the SVT storage cells is higher than the voltage threshold of the LVT storage cells. Alternatively or additionally, the candidate storage cell set 101 can include storage cells with higher voltage thresholds, such as storage cells of a high voltage threshold (HVT) type (which is also referred to simply as HVT storage cells). Alternatively or additionally, the candidate storage cell set 101 can include storage cells with lower voltage thresholds, such as storage cells of an extremely low voltage threshold (SLVT) type (which is also referred to simply as SLVT storage cells).

[0031] The lower the voltage threshold, the smaller the saturation current, so the faster the speed and the smaller the transmission delay. At the same time, the lower the voltage threshold, the larger the leakage current, and the larger the static power consumption. Therefore, compared with storage cells with high voltage thresholds, storage cells with low voltage thresholds have smaller transmission delays and larger static power consumptions. For example, for the different types of storage cells listed above, the transmission delays increase in the order of SLVT storage cells, LVT storage cells, SVT storage cells, and HVT storage cells. At the same time, the static power consumptions decrease in the order. It should be understood that the voltage threshold types listed above are merely exemplary and are not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, the candidate storage cell set 101 can include storage cells of any voltage threshold.

[0032] Although not shown, the designed chip 102 also includes other types of cells, such as combinational logic cells, sequential logic cells, and the like. Accordingly, the design system 120 can also determine other types of cells included in the chip 102 and their connection relationships. The design system 120 can be implemented, for example, as part of an EDA tool.

[0033] In the environment 100, the computing device 110 can be any type of computing device having computing capability, including an end device or a server device. The end device can be any type of mobile terminal, fixed terminal, or portable terminal including a mobile handset, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a game device, or any combination thereof, including accessories and peripherals of such devices or any combination thereof. The server device can include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0034] It should be understood that the structure and function of the environment 100 are described for illustrative purposes only and are not intended to imply any limitation on the scope of the present disclosure. Furthermore, Figure 1 The number of storage units shown in FIG. 1 is exemplary only and is not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, a designed chip can include any suitable number of storage units, and the storage units can have any suitable connection.

[0035] Taking SRAM as an example, in a conventional selection scheme, SRAM for a chip is selected from a selection range provided by a supplier on the premise that the demand for SRAM is met. In the selection, the margin for TCQ needs to be considered. On the one hand, if the margin for TCQ is too small, the selected SRAM can not meet the performance target in the later implementation process. In this case, re-selection needs to be performed, which will increase the design workload of the chip, and thus affect the manufacturing and listing of the chip product. On the other hand, if the margin for TCQ is too large, the SRAM with too fast speed will cause large leakage power consumption. This reduces the performance of the chip product in terms of power consumption.

[0036] Embodiments of the present disclosure propose a scheme for designing a chip. According to various embodiments of the present disclosure, in the early stage of chip design, a storage unit with a transmission delay less than a threshold transmission delay is selected. The threshold transmission delay can be set as small as possible to leave a proper margin for the transmission delay. In the later stage of chip design, a timing margin associated with a signal path including the selected storage unit is determined. Based on the timing margin, the selected storage unit is replaced with a storage unit with a higher voltage threshold.

[0037] In embodiments of the present disclosure, by properly reducing the threshold transmission latency in the preliminary selection, the margin for transmission latency can be properly increased, so that more storage cells of the lower voltage threshold type are selected. In the later stage, the storage cells with sufficient timing margin are replaced with storage cells of the higher voltage threshold type with lower power consumption. For example, LVT storage cells with sufficient timing margin can be replaced with SVT storage cells. In this way, neither the design cycle of the chip is affected, nor the power consumption of the final chip product is reduced. Embodiments of the present disclosure balance the speed and power consumption of the storage cells.

[0038] Some example embodiments of the present disclosure will be described below with continued reference to the accompanying drawings.

[0039] Example Storage Unit Determination Flow

[0040] Figure 2 A schematic diagram of an example flow 200 of storage cell determination is shown according to some embodiments of the present disclosure. As shown, the flow 200 can mainly include a cell preliminary selection process 210, an information extraction process 220, and a cell replacement process 230. Figure 2

[0041] In the cell preliminary selection process 210, the computing device 110 selects storage cells with transmission latency less than a threshold transmission latency from the candidate storage cell set 101 for the designed chip. In the following, the storage cells selected in the cell preliminary selection process 210 are also referred to as “preliminary selected storage cells”. The size of the threshold transmission latency reflects the size of the margin for transmission latency in the selection of storage cells. The smaller the threshold transmission latency, the greater the margin for transmission latency in the selection. Accordingly, a greater number of storage cells with lower voltage threshold can be selected. For example, a greater number of LVT storage cells can be selected.

[0042] The threshold transmission latency can be associated with the clock period of the chip. In some embodiments, the threshold transmission latency can be less than 90% of the clock period. By setting the threshold transmission latency to be of such size, the margin for TCQ is properly increased in the preliminary selection. In this way, storage cells with faster speed can be selected first. In some embodiments, the threshold transmission latency can be about equal to or equal to 70% of the clock period. By setting the threshold transmission latency to be of intermediate size, the margin for TCQ can be properly increased. Such threshold transmission latency of intermediate size further facilitates the balance between speed and power consumption. In some embodiments, the threshold transmission latency can be further reduced to select a greater number of fast storage cells. For example, the threshold transmission latency can be less than 70% of the clock period.

[0043] ​In addition to transmission latency, speed selection criteria may also include a TCC less than a threshold, which could be, for example, 90% of the clock cycle. Furthermore, in the initial cell selection process 210, the computing device 110 may also select memory cells based on their area and static power consumption. For example, the computing device 110 may first filter memory cells from the candidate memory cell set 101 that meet the speed requirements. Screening criteria for speed requirements may include a transmission latency less than a threshold transmission latency (e.g., 70% of the clock cycle) and a TCC less than the corresponding threshold (e.g., 90% of the clock cycle). Next, among the memory cells that meet the speed requirements, the computing device 110 may identify the shape with the smallest area and then select the memory cell with the lowest static power consumption from the memory cells having that shape.

[0044] The storage cell selection process described above is merely exemplary and is not intended to limit the scope of this disclosure. In embodiments of this disclosure, storage cells with transmission delays less than a threshold transmission delay can be selected from the candidate storage cell set 101 in any suitable manner.

[0045] It should be understood that during the initial cell selection process 210, the computing device 110 may also select other types of cells or devices in the chip, such as combinational logic cells and sequential logic cells. Through the initial cell selection process 210, an initial version chip 211 of the design can be obtained. The initial version chip 211 includes the selected memory cells, and in the initial version chip 211, these memory cells are connected to other cells or devices.

[0046] Figure 3 A schematic diagram of a portion of an initial version of chip 211 according to some embodiments of the present disclosure is shown. Figure 3 In the example, the selected memory cell 310 is an LVT-type memory cell and is connected to the sequential logic cell 314 via combinational logic 315. Combinational logic 315 includes combinational logic cells 311-1, 311-2, and 311-3, which are also individually or collectively referred to as combinational logic cell 311. Figure 3 In the example, combinational logic unit 311-1 is an SVT type AND gate, and combinational logic units 311-2 and 311-3 are SVT type buffers.

[0047] The selected memory cell 320 is an LVT-type memory cell and is connected to the sequential logic cell 324 via combinational logic 325. Combinational logic 325 includes combinational logic cells 321-1 and 321-2, which are also individually or collectively referred to as combinational logic cell 321. Figure 3 In the example, combinational logic unit 321-1 is an AND gate of type SVT, and combinational logic unit 321-2 is a buffer of type SVT.

[0048] It should be understood that, Figure 3 The illustrated portion of the initial version chip is exemplary only and is not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, the storage cells are not limited to Figure 3 the number and connection manner illustrated in FIG. 3.

[0049] With continued reference to Figure 2 In the information extraction process 220, the computing device 110 obtains storage cell information 221 from the candidate storage cell set 101. For example, the computing device 110 can, for each initial storage cell, count information of storage cells in the candidate storage cell set 101 that have the same specification as the initial storage cell but different voltage thresholds, including but not limited to attributes such as transmission latency, speed, and static power consumption. In some embodiments, the computing device 110 can count information of storage cells that have the same specification as the initial storage cell but higher voltage thresholds.

[0050] Additionally, in some embodiments, the computing device 110 can obtain standard cell information 222 from the standard cell library 201. For example, the computing device 110 can count, according to the classification of voltage thresholds, attributes such as speed, transmission latency, static power consumption, etc. of individual standard cells in the standard cell library.

[0051] In the cell replacement process 230, the computing device 110 updates the initial version chip 211 into the designed chip 102 using the storage cell information 221 and optionally the standard cell information 222. Specifically, the computing device 110 can determine timing margins associated with signal paths in the initial version chip 211 that include initial storage cells. In Figure 3 In the example of FIG. 3, the storage cell 310 is included in the signal path 301, and the storage cell 320 is included in the signal path 302. Accordingly, the computing device 110 can determine a timing margin associated with the signal path 301 and a timing margin associated with the signal path 302.

[0052] In some embodiments, the computing device 110 can determine a corresponding timing margin for each initial storage cell. In some embodiments, the computing device 110 can determine a corresponding timing margin for initial storage cells with lower voltage thresholds (e.g., LVT storage cells) because such initial storage cells are more likely to be replaced. In such embodiments, the computing device 110 can not determine a corresponding timing margin for initial storage cells with higher voltage thresholds (e.g., SVT storage cells or HVT storage cells) because such initial storage cells are less likely to be replaced or even have no possibility of being replaced.

[0053] In some embodiments, the computing device 110 can determine a timing margin associated with a signal path based on requirements of setup time checks. Specifically, the computing device 110 can determine a first delay Tl from a clock source of the signal path through a primary storage cell and combinational logic cell to a data port of a timing logic cell. The computing device 110 can also determine a second delay T2 from the clock source to a clock port of the timing logic cell. Based on the first delay Tl, the second delay T2, and a clock period, a timing margin of the signal path can be determined. For example, the timing margin can be equal to a sum of the second delay T2 and the clock period minus a sum of the first delay Tl and a setup time of the timing logic cell.

[0054] An example of timing margin determination is described with reference to Figure 4 For the storage cell 310, the first delay 401 is a delay from the clock source 410 through the storage cell 310, the combinational logic cell 311-1, the combinational logic cell 311-2, and the combinational logic cell 311-3 to the data port 411 of the timing logic cell 314. The second delay 402 is a delay from the clock source 410 to the clock port 412 of the timing logic cell 314. Based on the first delay 401, the second delay 402, a clock period of the clock source 410, and a setup time of the timing logic cell 314, a timing margin for the storage cell 310 can be determined.

[0055] Alternatively, in some embodiments, the computing device 110 can determine a timing margin associated with a signal path based on other conditions related to timing. For example, the timing margin can be determined based on requirements of hold time checks. Embodiments of the present disclosure are not limited in this respect. Furthermore, although only one signal path including a primary storage cell is described, it should be understood that a timing margin can be determined for all output paths of the primary storage cell, and the timing margins of all output paths are considered in the alternative.

[0056] The cell replacement process 230 is continued. Based on the determined timing margins, the computing device 110 replaces at least one of the primary storage cells with other storage cells in the candidate storage cell set 101. Herein, the storage cell used to replace a primary storage cell is also referred to as a target storage cell for illustration purposes only.

[0057] If the timing margin determined for a certain primary storage cell is greater than zero and the primary storage cell has a possibility of being replaced (e.g., a storage cell of LVT type), the computing device 110 can determine whether there exists a target storage cell in the candidate storage cell set 101 that can be used for the primary storage cell. Example embodiments of replacing a primary storage cell are described below with reference to Figure 5 ​

[0058] Since the pins and shapes of the storage units with different voltage threshold values are completely the same, the replacement of the storage units does not impact the logic design and the back-end physical design of the chip. Therefore, this way of replacing the voltage threshold values of the storage units after the early-stage transmission delay screening standard is added can save the leakage power consumption of the storage units and does not affect the design iteration period. Since the leakage power consumption of the storage units such as SRAM accounts for a relatively large proportion (for example, more than 30%) in the total leakage power consumption of the chip, the reduction of the leakage power consumption of the storage units is beneficial to reducing the total leakage power consumption of the chip product.

[0059] Replacement of Storage Units

[0060] Figure 5 A flowchart of an example process 500 of replacing storage units according to some embodiments of the present disclosure is shown. At block 510, for a preselected storage unit with timing margin, the computing device 110 selects a target storage unit from the candidate storage unit set 101. If the preselected storage unit in a signal path is a storage unit with a lower voltage threshold value, and there is timing margin in the path, the computing device 110 can determine a storage unit with the same specification but a higher voltage threshold value as the target storage unit according to the storage unit information 221. For example, if the preselected storage unit is an LVT type storage unit, the computing device 110 can determine a storage unit of the SVT type with the same specification as the target storage unit according to the storage unit information 221.

[0061] In some embodiments, the candidate storage unit set 101 can include multiple storage units (for example, SVT storage units and HVT storage units) with the same specification as the preselected storage unit and a higher voltage threshold value. In this case, the computing device 110 can select a target storage unit from these storage units based on the voltage threshold values of the multiple storage units respectively. For example, the computing device 110 can select a storage unit with the highest voltage threshold value (for example, an HVT storage unit) from these storage units as the target storage unit to perform the process 500. If the target storage unit cannot replace the preselected storage unit, the computing device 110 can select a storage unit with the second highest voltage threshold value (for example, an SVT storage unit) from these storage units as the target storage unit to perform the process 500. In this way, a storage unit with the highest possible voltage threshold value can be used for the designed chip, which can reduce the static power consumption of the chip product as much as possible.

[0062] The process 500 continues. At block 520, the computing device 110 determines an amount of first latency change that would be caused by replacing the candidate storage cell with the target storage cell based on the transmission latency of the candidate storage cell and the transmission latency of the target storage cell. The difference between the two transmission latencies can be used as the amount of first latency change. The target storage cell has a higher voltage threshold than the candidate storage cell, which means that the transmission latency of the target storage cell is greater than the transmission latency of the candidate storage cell. Thus, the amount of first latency change has a positive value, i.e., the amount of first latency change is a latency increment.

[0063] The computing device 110 replaces the candidate storage cell with the target storage cell based at least on a comparison of the amount of first latency change with the timing margin. At block 530, the computing device 110 determines whether the amount of first latency change is less than the timing margin. If it is determined that the amount of first latency change is less than the timing margin, the process 300 can proceed to block 540. It can be appreciated that if multiple timing margins are determined for the candidate storage cell (e.g., the timing margin for all output paths), then the amount of first latency change should be less than these timing margins. At block 540, the computing device 110 replaces the candidate storage cell with the target storage cell in the designed chip 102.

[0064] Reference is now made to Figure 6 . Figure 6 A schematic diagram of a portion of the designed chip 102 is shown in accordance with some embodiments of the present disclosure. By comparing Figure 3 and Figure 6 It can be seen that the LVT type storage cell 310 in the initial version chip 211 is replaced with the SVT type storage cell 610. Meanwhile, the combinational logic cell 311 on the signal path where the storage cell 310 is located remains unchanged.

[0065] Reference is now made to Figure 5 In some embodiments, if it is determined at block 530 that the amount of first latency change is not less than the timing margin, the process 500 ends or block 520 is performed for another target storage cell that can replace the candidate storage cell.

[0066] In some embodiments, if it is determined at block 530 that the amount of first latency change is not less than the timing margin, the combinational logic cell on the signal path that includes the candidate storage cell can be replaced. Accordingly, the process 500 proceeds to block 550.

[0067] At block 550, the computing device 110 determines a second delay change amount that would be caused by replacing the first combinational logic cell in the signal path with at least a second combinational logic cell. The second combinational logic cell has a lower voltage threshold than the first combinational logic cell. The second combinational logic cell can be from the standard cell library 201. For example, the computing device 110 can select, according to the standard cell information 222, a combinational logic cell of the same type as the first combinational logic cell but with a lower voltage threshold as the second combinational logic cell. The voltage threshold of the second combinational logic cell is lower than the first combinational logic cell, which means that the propagation delay of the second combinational logic cell is less than the first combinational logic cell. Thus, the value of the second delay change amount is negative. That is, the second delay change amount is a delay decrement.

[0068] At block 560, the computing device 110 determines whether the sum of the first delay change amount and the second delay change amount is less than the timing slack. That is, the computing device 110 determines whether replacing the combinational logic cell can compensate for the delay increase caused by replacing the storage cell. If the sum of the first delay change amount and the second delay change amount is determined to be less than the timing slack at block 560, i.e., replacing the combinational logic cell can compensate for the delay increase caused by replacing the storage cell, the process 500 proceeds to block 570. It can be appreciated that if multiple timing slacks are determined for the primary storage cell (e.g., the timing slacks of all the output paths), the sum of the first delay change amount and the second delay change amount should be less than these timing slacks.

[0069] At block 570, the computing device 110 replaces the primary storage cell with the target storage cell. At block 580, the computing device 110 replaces the first storage cell with at least the second storage cell.

[0070] The signal path in which the primary storage cell is located can include more than one combinational logic cell. If replacing one of the combinational logic cells cannot compensate for the delay increase caused by replacing the storage cell, the computing device 110 can replace multiple or even all of the combinational logic cells. In some embodiments, timing logic cells in the signal path can also be further replaced.

[0071] Figure 6 An example is shown. By comparing Figure 3 and Figure 6 It can be seen that the LVT type storage cell 320 in the initial version chip 211 is replaced with the SVT type storage cell 620. At the same time, the SVT type combinational logic cells 321-1 and 321-2 on the signal path in which the storage cell 320 is located are replaced with the combinational logic cells 621-1 and 621-2, respectively.

[0072] It should be appreciated that, Figure 6The portion of the designed chip shown is merely exemplary and is not intended to limit the scope of this disclosure. In embodiments of this disclosure, the type, number, etc., of the replaced memory cells and logic cells are not limited to... Figure 6 Examples.

[0073] In this embodiment, replacing the standard cell allows the memory cell to be replaced without violating timing requirements. The power saving from replacing the memory cell outweighs the loss from replacing the standard cell. In this way, more initial memory cells can be replaced, thereby saving more power in the chip product.

[0074] The above is for reference only. Figure 5 An example embodiment is described that replaces the initial selected memory cell based on a comparison of a first delay change and a timing margin. Alternatively, in some embodiments, the initial selected memory cell can be replaced in other ways. For example, the maximum transmission delay for the target memory cell can be determined based on the timing margin and the transmission delay of the initial selected memory cell. The computing device 110 can then replace the initial selected memory cell by determining from the candidate memory cell set 101 memory cells with transmission delays less than the maximum transmission delay and voltage thresholds higher than those of the initial selected memory cell, based on memory cell information 221.

[0075] Example Process

[0076] Figure 7 A flowchart of a chip design process 700 according to some embodiments of the present disclosure is shown. Process 700 can be implemented at computing device 110. Reference is made below. Figure 1 To describe process 700.

[0077] In block 710, computing device 110 selects a first memory cell from candidate memory cell set 101 for the designed chip. The first memory cell has a first transmission delay less than a threshold transmission delay. For example, the delay TCQ from the clock port to the output port is less than the threshold transmission delay.

[0078] In some embodiments, the threshold transmission delay is less than 90% of the clock cycle. In some embodiments, the threshold transmission delay is equal to or approximately equal to 70% of the clock cycle.

[0079] In block 720, computing device 110 determines timing margins associated with signal paths in the chip that include the first memory cell. Timing margins can be determined for each selected memory cell.

[0080] In some embodiments, the timing margin is related to a setup time check. The computing device 110 can determine a first latency of data from a clock source of a signal path to pass through a first storage cell and a combinational logic cell in the signal path to a data port of a timing logic cell. The computing device 110 can determine a second latency of the clock from the clock source to a clock port of the timing logic cell. The computing device 110 can determine the timing margin based on the first latency, the second latency, and a clock period of the chip.

[0081] At block 730, the computing device 110 replaces the first storage cell with a second storage cell in the candidate storage cell set 101 in the chip based on the timing margin. The second storage cell has a higher voltage threshold than the first storage cell.

[0082] In some embodiments, the computing device 110 can select a plurality of storage cells from the candidate storage cell set 101, the selected storage cells being of the same specification as the first storage cell and having a higher voltage threshold than the first storage cell. The computing device 110 can select the second storage cell from the plurality of storage cells based on the respective voltage thresholds of the plurality of storage cells.

[0083] In some embodiments, the computing device 110 can determine an amount of first latency change that would be caused by replacing the first storage cell with the second storage cell based on the first transmission latency and a second transmission latency of the second storage cell. The computing device 110 can replace the first storage cell with the second storage cell based at least on a comparison of the first amount of latency change to the timing margin.

[0084] In some embodiments, the computing device 110 can replace the first storage cell with the second storage cell if it is determined that the first amount of latency change is less than the timing margin.

[0085] In some embodiments, the computing device 110 can determine a second amount of latency change that would be caused by replacing at least the first combinational logic cell in the signal path with a second combinational logic cell having a lower voltage threshold than the first combinational logic cell if it is determined that the first amount of latency change is greater than the timing margin. The computing device 110 can replace the first storage cell with the second storage cell if it is determined that a sum of the first amount of latency change and the second amount of latency change is less than the timing margin. In some embodiments, the computing device 110 can also replace at least the first combinational logic cell with the second combinational logic cell.

[0086] In some embodiments, the first storage cell and the second storage cell comprise SRAM.

[0087] Example Apparatus and Device

[0088] Figure 8A schematic structural block diagram of an apparatus 800 for designing a chip in accordance with certain embodiments of the present disclosure is shown. The apparatus 800 can be implemented as or included in the computing device 110. Various modules / components in the apparatus 800 can be implemented by hardware, software, firmware, or any combination thereof.

[0089] As shown, the apparatus 800 includes a storage unit selection module 810 configured to select a first storage unit for a chip being designed from a set of candidate storage units, the first storage unit having a first transmission latency that is less than a threshold transmission latency. The apparatus 800 also includes a timing margin determination module 820 configured to determine a timing margin associated with a signal path in the chip that includes the first storage unit. The apparatus 800 also includes a storage unit replacement module 830 configured to replace, based on the timing margin, the first storage unit with a second storage unit from the set of candidate storage units in the chip, the second storage unit having a higher voltage threshold than the first storage unit.

[0090] In some embodiments, the storage unit replacement module 830 includes a first latency change amount determination module configured to determine, based on the first transmission latency and a second transmission latency of the second storage unit, a first latency change amount that would result from replacing the first storage unit with the second storage unit, and a margin comparison module configured to replace the first storage unit with the second storage unit based at least on a comparison of the first latency change amount and the timing margin.

[0091] In some embodiments, the margin comparison module is further configured to replace the first storage unit with the second storage unit if it is determined that the first latency change amount is less than the timing margin.

[0092] In some embodiments, the margin comparison module is further configured to determine, if it is determined that the first latency change amount is greater than the timing margin, a second latency change amount that would result from replacing at least a first combinational logic unit in the signal path with a second combinational logic unit having a lower voltage threshold than the first combinational logic unit, and to replace the first storage unit with the second storage unit if it is determined that a sum of the first latency change amount and the second latency change amount is less than the timing margin.

[0093] In some embodiments, the apparatus 800 further includes a combinational logic unit replacement module configured to replace at least the first combinational logic unit with the second combinational logic unit.

[0094] In some embodiments, the threshold transmission latency is less than 90% of a clock period.

[0095] In some embodiments, the apparatus 800 further includes: an information utilization module configured to select a plurality of storage cells from a candidate storage cell set, wherein the selected storage cells have the same specifications as the first storage cell and have a higher voltage threshold than the first storage cell; and a target cell selection module configured to select a second storage cell from the plurality of storage cells based on the respective voltage thresholds of the plurality of storage cells.

[0096] In some embodiments, the timing margin determination module 820 includes: a first delay determination module configured to determine a first delay from the clock source of the signal path through the first memory cell and the combinational logic cell in the signal path to the data port of the timing logic cell; a second delay determination module configured to determine a second delay from the clock source to the clock port of the timing logic cell; and a timing margin calculation module configured to determine a timing margin based on the first delay, the second delay, and the clock cycle of the chip.

[0097] In some embodiments, the first storage unit and the second storage unit include SRAM.

[0098] Figure 9 A block diagram illustrating a computing device 900 in which one or more embodiments of the present disclosure may be implemented is shown. It should be understood that... Figure 9 The computing device 900 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. Figure 9 The computing device 900 shown can be used to implement Figure 1 The computing device 110.

[0099] like Figure 9 As shown, computing device 900 is in the form of a general-purpose computing device. Components of computing device 900 may include, but are not limited to, one or more processors or processing units 910, memory 920, storage devices 930, one or more communication units 940, one or more input devices 950, and one or more output devices 960. Processing unit 910 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 920. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capability of computing device 900.

[0100] Computing device 900 typically includes multiple computer storage media. Such media can be any accessible media that is accessible to computing device 900, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 920 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 930 can be removable or non-removable media and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data (e.g., training data for training) and can be accessed within computing device 900.

[0101] The computing device 900 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 9 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 920 may include computer program product 925 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0102] The communication unit 940 enables communication with other computing devices via a communication medium. Additionally, the components of the computing device 900 can function as a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, the computing device 900 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0103] Input device 950 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 960 can be one or more output devices, such as a monitor, speaker, printer, etc. Computing device 900 can also communicate as needed with one or more external devices (not shown) via communication unit 940. These external devices, such as storage devices, display devices, etc., can communicate with one or more devices that enable user interaction with computing device 900, or with any device (e.g., network card, modem, etc.) that enables computing device 900 to communicate with one or more other computing devices. Such communication can be performed via input / output (I / O) interfaces (not shown).

[0104] According to an example implementation of the present disclosure, a computer readable storage medium is provided having computer executable instructions stored thereon, where the computer executable instructions are executed by a processor to implement the method described above. According to an example implementation of the present disclosure, a computer program product is also provided that is tangibly stored on a non-transitory computer readable medium and includes computer executable instructions, where the computer executable instructions are executed by a processor to implement the method described above.

[0105] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0106] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0107] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0108] The computer program product of the present disclosure can have a signal including said computer program. This signal can be electronic, electromagnetic, optical, or any other suitable type of signal. Such a signal can be provided through a communication connection, such as electrical wiring, optical fiber, wireless interface, etc. Examples of computer program products include computer program implemented on a personal computer, server, or other networked device. A non-transitory computer readable medium, such as a floppy disk, CD-ROM, DVD-ROM, Blu-ray Disc, hard disk drive, or any other suitable non-transitory computer readable medium can store the computer program product.

[0109] Various implementations of the disclosure have been described in detail above. The foregoing description is exemplary and explanatory only, and is not intended to be exhaustive or to limit various implementations of the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings without departing from the scope and spirit of the disclosure. It is intended that the scope of the disclosure be limited only by the claims and the equivalents thereof. The use of the terms "including," "containing," "comprising," "having," "in involving," "portions," "elements," "components," "steps," "phases," "processes," "operations," "steps," "stages," "procedures," "methods," "mechanisms," "devices," "systems," "apparatuses," "units," "means," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "apparatuses," "units," "devices," "systems," "

Claims

1. A method of designing a chip, comprising: selecting a first storage unit for a chip being designed from a set of candidate storage units, a first propagation delay of the first storage unit being less than a threshold propagation delay; determining a timing margin associated with a signal path in the chip that includes the first storage unit; determining, based on the first propagation delay and a second propagation delay of a second storage unit in the set of candidate storage units, a first delay change amount that would result from replacing the first storage unit with the second storage unit in the chip, the second storage unit having a higher voltage threshold than the first storage unit; in response to the first delay change amount being greater than the timing margin, determining a second delay change amount that would result from replacing at least a first combinational logic unit in the signal path with a second combinational logic unit, the second combinational logic unit having a lower voltage threshold than the first combinational logic unit; in response to a sum of the first delay change amount and the second delay change amount being less than the timing margin, replacing the first storage unit with the second storage unit; and replacing at least the first combinational logic unit with the second combinational logic unit.

2. The method of claim 1, further comprising: if it is determined that the first delay change amount is less than the timing margin, replacing the first storage unit with the second storage unit.

3. The method of claim 1, wherein the threshold propagation delay is less than 90% of a clock period.

4. The method of claim 1, further comprising: selecting a plurality of storage units from the set of candidate storage units, the selected storage units being of the same type as the first storage unit and having higher voltage thresholds than the first storage unit; and selecting the second storage unit from the plurality of storage units based on the respective voltage thresholds of the plurality of storage units.

5. The method of claim 1, wherein determining the timing margin comprises: determining a first delay from a clock source of the signal path to a data port of a sequential logic unit in the signal path through the first storage unit and combinational logic units in the signal path; determining a second delay from the clock source to a clock port of the sequential logic unit; and determining the timing margin based on the first delay, the second delay, and a clock period of the chip.

6. The method of claim 1, wherein the first storage unit and the second storage unit comprise static random access memory.

7. An apparatus for designing a chip, comprising: a storage unit selection module configured to select a first storage unit for a chip being designed from a set of candidate storage units, a first propagation delay of the first storage unit being less than a threshold propagation delay; a timing margin determination module configured to determine a timing margin associated with a signal path in the chip that includes the first storage unit; and a delay change determination module configured to determine, based on the first propagation delay and a second propagation delay of a second storage unit in the set of candidate storage units, a first delay change amount that would result from replacing the first storage unit with the second storage unit in the chip, the second storage unit having a higher voltage threshold than the first storage unit. ​ a first latency change amount determination module configured to determine a first latency change amount that would be caused by replacing the first memory cell with a second memory cell in the chip based on the first transmission latency and a second transmission latency of a second memory cell in the candidate memory cell set, the second memory cell having a higher voltage threshold than the first memory cell; a margin comparison module configured to determine a second latency change amount that would be caused by replacing at least a first combinational logic cell in the signal path with a second combinational logic cell having a lower voltage threshold than the first combinational logic cell in response to the first latency change amount being greater than the timing margin, and replace the first memory cell with the second memory cell in response to a sum of the first latency change amount and the second latency change amount being less than the timing margin; and a combinational logic cell replacement module configured to replace at least the first combinational logic cell with the second combinational logic cell.

8. An electronic device, comprising: at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions which when executed by the at least one processing unit cause the electronic device to perform the method according to any one of claims 1-6.

9. A computer-readable storage medium having stored thereon a computer program, the computer program being executable by a processor to implement the method according to any one of claims 1-6.

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