A cache address circuit based on magnetic random access memory
By employing hierarchical storage and comparison in the cache address circuit, and utilizing decoders and tri-state gates, the problem of misreading and miswriting in magnetic random access memory is solved, thereby improving data reliability and reducing power consumption.
Patent Information
- Application Number
- CN202311781037.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-21
- Publication Date
- 2026-08-04
- Estimated Expiration
- 2043-12-21
AI Technical Summary
Existing magnetic random access memories suffer from misreading and writing problems in the cache address circuit, leading to a decrease in data reliability.
A cache address circuit based on magnetic random access memory is adopted. By combining a decoder and a tri-state gate, hierarchical storage and comparison of tags are realized, reducing the number of reads and lowering the probability of misreading.
It improves the data reliability of the cache address circuit, reduces power consumption, and reduces unnecessary comparison operations.
Smart Images
Figure CN117831582B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer system storage technology, and in particular to a cache address circuit based on magnetic random access memory. Background Technology
[0002] With advancements in technology, computer processors have achieved increasingly higher frequencies and operating speeds. However, main memory, in order to balance storage capacity and power consumption, has lagged behind in frequency increases and read speeds. The invention of cache primarily aimed to address this speed difference between the computer processor and main memory. As temporary storage located between the processor and main memory, it stores frequently accessed data and instructions, thereby significantly improving the performance of the computer system.
[0003] Caching is an indispensable module in computer architecture. For decades, static random-access memory (SRAM) has been the primary memory for caching due to its fast read speed and reliability. However, as manufacturing processes continue to shrink, the disadvantages of SRAM have become more apparent, such as high leakage current and decreased reliability. Magnetic random-access memory (MRAM) possesses characteristics such as non-volatility, low leakage power, and high durability. However, due to limitations in materials, structure, and manufacturing technology, existing MRAMs still suffer from susceptibility to misreading and miswriting. Summary of the Invention
[0004] The main objective of this application is to propose a cache address circuit based on magnetic random access memory (MRM) to reduce the number of reads from the MRM, thereby reducing the probability of false reads and improving the data reliability of the cache address circuit.
[0005] To achieve the above objectives, one aspect of this application provides a cache address circuit based on a magnetic random access memory, the circuit comprising: a decoder, a magnetic random access memory array, and multiple tri-state gates;
[0006] The magnetic random access memory array is used for hierarchical storage of tags;
[0007] The decoder is used to select the tag stored in the magnetic random access memory array;
[0008] The tri-state gate is used to receive the hit signals output by each of the tags in the magnetic random access memory array, and to send the cached data of the corresponding channel to the bus.
[0009] In some embodiments, the magnetic random access memory array includes a plurality of magnetic random access memory cells, a plurality of registers, and a buffer;
[0010] The magnetic random access memory unit is used to store the tag;
[0011] The buffer is used to output a high level after charging;
[0012] The register is configured to output a high level when the requested tag matches the tag selected by the decoder.
[0013] In some embodiments, the magnetic random access memory array includes multiple array element circuits;
[0014] Each array element circuit includes multiple unit circuits, each unit circuit includes multiple levels of unit sub-circuits, and each level of unit sub-circuit includes multiple magnetic random access memory units.
[0015] The unit sub-circuits in each of the unit circuits have a sequential order, and the output of each unit sub-circuit is connected to the input of a register; the register corresponding to the last unit sub-circuit is used as the endpoint register, and the output of each endpoint register is connected to a tri-state gate. The outputs of all the other registers except the endpoint register are connected to the input of the next unit sub-circuit.
[0016] In some embodiments, the input of each buffer is connected to the output of the last stage of the unit sub-circuit of each unit circuit, the output of each buffer is connected to the input of one of the endpoint registers, and the output of each endpoint register is connected to one of the tri-state gates.
[0017] In some embodiments, each of the magnetic random access memory cells includes a plurality of spin-orbit torque magnetic tunnel junctions and a plurality of transistors;
[0018] The spin-orbit torque magnetic tunnel junction is used to store the tag.
[0019] The transistor is used to control the reading and writing of the spin-orbit torque magnetic tunnel junction.
[0020] In some embodiments, each of the magnetic random access memory cells includes a first spin-orbit torque magnetic tunnel junction, a second spin-orbit torque magnetic tunnel junction, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, all of which are NMOS transistors;
[0021] Wherein, the gate of the first transistor is connected to the first read word line, the drain is connected to the input terminal of the magnetic random access memory cell, and the source is connected to the first port of the first spin-orbit torque magnetic tunnel junction.
[0022] The gate of the second transistor is connected to the second read word line, the drain is connected to the input terminal of the magnetic random access memory cell, and the source is connected to the first port of the second spin-orbit torque magnetic tunnel junction.
[0023] The gates of the third, fourth, and fifth transistors are all connected to the write word line; the drain of the third transistor is connected to the bit line, and the source is connected to the output terminal of the magnetic random access memory cell; the drain of the fourth transistor is connected to the first port of the first spin-orbit torque magnetic tunnel junction, and the source is connected to the source line; the drain of the fifth transistor is connected to the second port of the second spin-orbit torque magnetic tunnel junction, and the source is connected to the source line.
[0024] The output terminal of the magnetic random access memory unit is connected to the second port of the first spin-orbit torque magnetic tunnel junction and the first port of the second spin-orbit torque magnetic tunnel junction.
[0025] In some embodiments, the decoder includes a group decoder and a tag decoder;
[0026] The group decoder is used to select a group of array element circuits as the target array element circuit from each group of array element circuits according to the requested address.
[0027] The tag decoder is used to select the spin-orbit torque magnetic tunnel junction corresponding to the target tag in the target array circuit; wherein the target tag is the tag requested in the request address, and the magnetic random access memory unit includes a plurality of the spin-orbit torque magnetic tunnel junctions.
[0028] In some embodiments, the magnetic random access memory array includes multiple array element circuits;
[0029] Each array element circuit includes 8 unit circuits, each unit circuit includes 4 levels of unit sub-circuits, and each level of unit sub-circuit includes 8 magnetic random access memory units.
[0030] Each of the aforementioned registers is an 8-bit register.
[0031] To achieve the above objectives, another aspect of the embodiments of this application proposes a circuit system, which includes a cache address circuit based on a magnetic random access memory as described above.
[0032] To achieve the above objectives, another aspect of the embodiments of this application proposes an electronic device, which includes a processor and a cache, the cache including a cache address circuit based on a magnetic random access memory as described above.
[0033] The embodiments of this application include at least the following beneficial effects:
[0034] The magnetic random access memory array of this application can hierarchically store tags. When the decoder selects a tag to access the cache address circuit, it performs hierarchical comparison on the tags of the requested address, and then sends the hit signal obtained from the hierarchical comparison to a tri-state gate, thereby determining whether to send the cached data to the bus. This scheme does not require reading and comparing tags for all addresses, reducing the number of reads and thus reducing the probability of misreading data when accessing the cache address circuit, improving the data reliability of the cache address circuit. Moreover, hierarchical comparison of tags can save a lot of unnecessary comparison operations, greatly reducing the power consumption of the cache address circuit. Attached Figure Description
[0035] Figure 1 An example structural diagram of a spin-orbit torque magnetic tunnel junction provided in this application embodiment;
[0036] Figure 2 An example structural diagram of a cache address circuit based on a magnetic random access memory provided in an embodiment of this application;
[0037] Figure 3 Example structural diagrams and working principle diagrams of MRAM cells provided in embodiments of this application;
[0038] Figure 4 This is a structural diagram of the first-level cell sub-circuit in the MRAM array provided in the embodiments of this application;
[0039] Figure 5 The signal simulation waveform diagram of the cache address circuit provided in the embodiment of this application during operation. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.
[0041] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”
[0042] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0044] Before providing a detailed description of the embodiments of this application, some of the nouns and terms used in the embodiments of this application will be explained first. The nouns and terms used in the embodiments of this application shall be interpreted as follows:
[0045] Spin-orbit Torque-Magnetic Tunnel Junction (SOT-MTJ) is a four-layer electronic device. Its specific structure can be found in [reference needed]. Figure 1From top to bottom, the layers are: a free layer, an oxide layer, a reference layer, and a heavy metal layer. The free layer stores information, and its magnetization direction can be switched by the write current. The magnetization direction of the reference layer is fixed. When the magnetization direction of the free layer is the same as that of the reference layer, it is called a parallel state (P); otherwise, it is called an anti-parallel state (AP). In the P and AP states, the SOT-MTJ exhibits low resistance and high resistance, respectively, which can be used to represent binary "0" and "1" in digital circuits. The SOT-MTJ is a three-port device with three external interfaces, a, b, and c. In the embodiments of this application, ports a, b, and c can correspond to the first, second, and third ports of the SOT-MTJ, respectively. For write operations, the write current flows through the heavy metal layer. Depending on the direction of the write current (i.e., the current flows from a to b, or the current flows from b to a), the SOT-MTJ switches to the P and AP states, respectively. For read operations, the SOT-MTJ can be considered as a resistor. The read current flows sequentially through the free layer, oxide layer, reference layer, and heavy metal layer (i.e., the current flows from c to a, or from c to b). Based on the magnitude of the read current, the magnitude of the equivalent resistance of the SOT-MTJ can be obtained, and thus the data stored in the SOT-MTJ can be obtained.
[0046] Reading and writing data is particularly critical during the process of accessing the cache address circuit (for ease of description, the cache address circuit in this embodiment can be simply referred to as the cache). This is because each time the cache is accessed, the tags of all paths within the target cache group need to be read and compared. Only when every bit of a tag in one path matches the tag in the requested address is it considered a cache hit, and the next operation on the cache can proceed. Frequent use and reading of tags greatly increases the probability of misreading of the magnetic random access memory. Therefore, in order to further improve the data reliability of the cache address circuit based on magnetic random access memory, it is necessary to further design the structure and reading method of the cache address circuit to address its susceptibility to misreading and miswriting.
[0047] In view of this, embodiments of this application provide a cached address circuit based on magnetic random access memory (MRMemory). This cached address circuit may include a decoder, a MRMemory array, and multiple tri-state gates. The MRMemory array of this application can hierarchically store tags. When the decoder selects a tag to access the cached address circuit, it performs hierarchical comparisons on the tags of the requested address, and then sends the hit / miss signals obtained from the hierarchical comparisons to the tri-state gates, thereby determining whether to send the cached data to the bus. This scheme eliminates the need to read and compare tags for all addresses, reducing the number of reads and thus lowering the probability of misreading data when accessing the cached address circuit, thereby improving the data reliability of the cached address circuit.
[0048] Reference Figure 2This application provides an example structural diagram of a cache address circuit based on a magnetic random access memory. It should be noted that... Figure 2 The circuit shown is only one optional circuit structure according to an embodiment of this application. Figure 2 This does not constitute a limitation on this application.
[0049] The cached address circuit in this application embodiment may include: a decoder, a magnetic random access memory array, and multiple tri-state gates;
[0050] The magnetic random access memory array is used for hierarchical storage of tags;
[0051] The decoder is used to select the tag stored in the magnetic random access memory array;
[0052] The tri-state gate is used to receive the hit signals output by each of the tags in the magnetic random access memory array, and to send the cached data of the corresponding channel to the bus.
[0053] Specifically, the tri-state gate can be used to receive hit / miss signals from a magnetic random access memory array (MRAM array). The tri-state gate can be activated by the hit signal and send the cached data of the path corresponding to the hit signal to the bus.
[0054] Furthermore, the magnetic random access memory array includes multiple magnetic random access memory cells, multiple registers, and buffers;
[0055] The magnetic random access memory unit is used to store the tag;
[0056] The buffer is used to output a high level after charging;
[0057] The register is configured to output a high level when the requested tag matches the tag selected by the decoder.
[0058] Specifically, the buffer in this embodiment can be composed of two cascaded inverters.
[0059] Next, the magnetic random access memory array will be described in more detail, which includes multiple array element circuits.
[0060] Each array element circuit includes multiple unit circuits, each unit circuit includes multiple levels of unit sub-circuits, and each level of unit sub-circuit includes multiple magnetic random access memory units.
[0061] The unit sub-circuits in each of the unit circuits have a sequential order, and the output of each unit sub-circuit is connected to the input of a register; the register corresponding to the last unit sub-circuit is used as the endpoint register, and the output of each endpoint register is connected to a tri-state gate. The outputs of all the other registers except the endpoint register are connected to the input of the next unit sub-circuit.
[0062] As an optional implementation, the input of each buffer is connected to the output of the last stage of the unit sub-circuit of each unit circuit, the output of each buffer is connected to the input of one of the endpoint registers, and the output of each endpoint register is connected to one of the tri-state gates.
[0063] As an optional implementation, each of the magnetic random access memory cells includes multiple spin-orbit torque magnetic tunnel junctions and multiple transistors;
[0064] The spin-orbit torque magnetic tunnel junction is used to store the tag.
[0065] The transistor is used to control the reading and writing of the spin-orbit torque magnetic tunnel junction.
[0066] As an optional implementation, each of the magnetic random access memory cells includes a first spin-orbit torque magnetic tunnel junction, a second spin-orbit torque magnetic tunnel junction, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, all of which are NMOS transistors;
[0067] Wherein, the gate of the first transistor is connected to the first read word line, the drain is connected to the input terminal of the magnetic random access memory cell, and the source is connected to the first port of the first spin-orbit torque magnetic tunnel junction.
[0068] The gate of the second transistor is connected to the second read word line, the drain is connected to the input terminal of the magnetic random access memory cell, and the source is connected to the first port of the second spin-orbit torque magnetic tunnel junction.
[0069] The gates of the third, fourth, and fifth transistors are all connected to the write word line; the drain of the third transistor is connected to the bit line, and the source is connected to the output terminal of the magnetic random access memory cell; the drain of the fourth transistor is connected to the first port of the first spin-orbit torque magnetic tunnel junction, and the source is connected to the source line; the drain of the fifth transistor is connected to the second port of the second spin-orbit torque magnetic tunnel junction, and the source is connected to the source line.
[0070] The output terminal of the magnetic random access memory unit is connected to the second port of the first spin-orbit torque magnetic tunnel junction and the first port of the second spin-orbit torque magnetic tunnel junction.
[0071] As an optional implementation, the decoder includes a group decoder and a tag decoder;
[0072] The group decoder is used to select a group of array element circuits as the target array element circuit from each group of array element circuits according to the requested address.
[0073] The tag decoder is used to select the spin-orbit torque magnetic tunnel junction corresponding to the target tag in the target array circuit; wherein the target tag is the tag requested in the request address, and the magnetic random access memory unit includes a plurality of the spin-orbit torque magnetic tunnel junctions.
[0074] As an optional implementation, the magnetic random access memory array includes multiple array element circuits;
[0075] Each array element circuit includes 8 unit circuits, each unit circuit includes 4 levels of unit sub-circuits, and each level of unit sub-circuit includes 8 magnetic random access memory units.
[0076] Each of the aforementioned registers is an 8-bit register.
[0077] The implementation methods of the embodiments of this application will be described in detail below.
[0078] First, the overall structure of the cache address circuit in the embodiments of this application will be described. Optionally, refer to... Figure 2 The cache address circuit may include a decoder, a magnetic random access memory array (MRAM array) and multiple tri-state gates.
[0079] The decoder may include a group decoder and a tag decoder. The group decoder is used to select the required array element circuit from each group of array element circuits according to the request address. The tag decoder decodes the tag in the request address into a binary combination in (0, 1) or (1, 0) format, which is used to select the SOT-MTJ in the magnetic random access memory cell (MRAM cell).
[0080] The MRAM array in this embodiment can be used to store cache tags. Each cache has 8 channels, and each channel has 32-bit tags. The 32-bit tags are divided into 4 levels: [7-0] for level 1, [15-8] for level 1, [23-16] for level 1, and [31-24] for level 1. The output of each level is connected to an 8-bit register. This is for hierarchical comparison. Only when the tag of the previous level completely matches the requested tag will the comparison of the next level be triggered. If, after 4 levels of comparison, a tag in one channel completely matches the requested tag, a hit signal will be output in the corresponding bit of register 3.
[0081] The tri-state gate in this embodiment can be used to receive the hit signal from the MRAM array and send the cached data of the path corresponding to the hit signal to the bus.
[0082] Next, the MRAM cell of this embodiment will be described. Figure 3 Example structural diagrams of MRAM cells and their working principles for reading and writing are provided.
[0083] The MRAM cell in this embodiment may include two SOT-MTJs and five transistors, denoted as T1 to T5. The SOT-MTJs can be used to store data. The two SOT-MTJs are always in opposite states, and a combination of (0, 1) represents binary 0, while a combination of (1, 0) represents binary 1. Transistors T1 to T5 are used to control the reading and writing of the SOT-MTJs; T1 to T5 are all NMOS transistors.
[0084] The specific connection relationships of each component in the MRAM cell can include: the gate of transistor T1 is connected to read word line A, the drain is connected to the input terminal, and the source is connected to port a of the first SOT-MTJ; the gate of transistor T2 is connected to read word line B, the drain is connected to the input terminal, and the source is connected to port a of the second SOT-MTJ. The gates of transistors T3 to T5 are all connected to write word lines; the drain of transistor T3 is connected to the bit line, and the source is connected to the output terminal (the output terminal is connected to both port b of the first SOT-MTJ and port a of the second SOT-MTJ); the drain of transistor T4 is connected to port a of the first SOT-MTJ, and the source is connected to the source line; the drain of transistor T5 is connected to port b of the second SOT-MTJ, and the source is connected to the source line.
[0085] During a write operation, a high-level signal is applied to the write word line, turning on the three transistors T3-T5 connected to the write word line. The bit line and source line are then configured with high and low levels respectively, depending on the data to be written. When writing 0, a high-level signal is applied to the bit line and a low-level signal to the source line, with current flowing from the bit line to the source line. Therefore, the write current for the first SOT-MTJ flows from b to a, and its state is written as low-impedance. The write current for the second SOT-MTJ flows from a to b, and its state is written as high-impedance. When writing 1, a low-level signal is applied to the bit line and a high-level signal to the source line, with current flowing from the source line to the bit line. Therefore, the write current for the first SOT-MTJ flows from a to b, and its state is written as high-impedance. The write current for the second SOT-MTJ flows from b to a, and its state is written as low-impedance.
[0086] During a read operation, a low-level signal is applied to the write word line, turning off transistors T3-T5. Simultaneously, the levels applied to read word line A and read word line B are opposite, ensuring that only one of T1 and T2 is conducting. The read current flows in from the input port, through one of the SOT-MTJs, and out from the output port.
[0087] To further illustrate the structure and operation of the cache address circuit in this embodiment, Figure 4 The diagram shows the structure of the first-level cell sub-circuit in the MRAM array.
[0088] Specifically, the MRAM array in this embodiment may include MRAM cells, registers, and buffers. The operation of the cached address circuit may include: First, the tag decoder decodes the request tag. If the request tag is 0, it is decoded as (1, 0); if the request tag is 1, it is decoded as (0, 1). Each bit of the decoding signal controls the 8-channel tag array simultaneously. The decoder output is connected to the read word line A and read word line B of the MRAM cell, respectively. If the request tag matches a tag cached in the first-level cell sub-circuit, the low-resistance SOT-MTJ in the corresponding MRAM cell will be selected; otherwise, the high-resistance SOT-MTJ in the corresponding MRAM cell will be selected. This continues until all bits of the request tag match tags in the cache, at which point all 8 MRAM cells in series in that channel will select the low-resistance SOT-MTJ. When the tag array is charged using a charging source, the channel with a higher matching degree will have a faster charging speed due to its lower equivalent resistance.
[0089] In this embodiment, the buffer can be constructed from two cascaded inverters connected to the last bit output of each unit circuit. Therefore, the circuit with lower equivalent resistance will always charge to the inverter's toggling threshold first and output a high-level signal at the buffer output first.
[0090] In this embodiment, the 8-bit register is connected to the output of the buffer. The rising edge of clock 0 triggers the signal between the point where all 8 SOT-MTJ bits are in a low-impedance state and the point where only one SOT-MTJ bit is in a high-impedance state. Therefore, the register can only output a high-level signal on that path and serve as a charging source for the next stage circuit when all 8 tags of the cached address match the tag of the requested address. If none of the tags of all 8 cached addresses match the tag of the requested address, the register will not sample any high-level signal when clock 0 is triggered, and therefore cannot charge the next stage, ending the charging process of the MRAM array and reducing the number of reads from the cached address circuit.
[0091] The cache address circuit in this embodiment can eliminate the need for a sensitive amplifier. Instead, it classifies the tags and compares them based on differences in charging speed. Eliminating the sensitive amplifier saves circuit resources, while the hierarchical comparison eliminates many unnecessary comparison operations, significantly reducing power consumption. During a cache access process, clocks 0 through 3 are triggered sequentially. If a path in the cache group contains data from the requested address, each register level will output a high-level signal sequentially, and the corresponding bit in flip-flop 3 will also output a high level, indicating a hit, and the corresponding data will be sent to the bus. If the cache group does not contain data from the requested address, none of the 8 bits of register 3 will output a high level, indicating a miss, and the cache access process will end.
[0092] The following sections will provide a detailed introduction and explanation of the solutions in the embodiments of this application, using more specific application examples:
[0093] In this embodiment, it is assumed that in a 64-bit computer system, the L2 cache has a capacity of 1MB, a total of 1024 sets, each set contains 8 ways, the block size is 64 bytes, and the mapping method is 8-way set-dependent. The cache request address is 48 bits, including 10 bits for the set address, 3 bits for the way address, 3 bits for the block address, and 32 bits for the tag address.
[0094] First, the group decoder decodes the group information in the request address and selects the corresponding group in the cache. Then, the tag decoder decodes the tag information, converting the "0" in the binary information into a (1, 0) combination control signal; and converting the "1" in the binary information into a (0, 1) combination control signal, which is then used to control all 8 tags in the selected group. The decoded control signals are connected to read word line A and read word line B respectively, ensuring that only one of transistors T1 and T2 is always turned on.
[0095] Depending on whether the cache contains the data from the requested URL, a single cache access process can be categorized into two cases: a cache hit and a cache miss.
[0096] In a hit scenario, if the cached address circuit stores the data from the requested address, then there is one and only one tag that completely matches all 32 bits of the tag in the requested address. Assuming that path 1 contains the data from the requested address, the waveform simulation is as follows... Figure 5 As shown. Charging begins at time T1, and the output voltage of each channel of the MRAM array gradually increases. However, due to differences in equivalent resistance, channels with higher matching have a faster charging speed. Therefore, channel 1, being perfectly matched, has the lowest equivalent resistance and the fastest charging speed. Its connected buffer flips first, outputting a high-level signal. Clock 0 is triggered at time T2, recording the high-level output of channel 1 and using it as the charging source for the next stage. In this case, each register of channel 1 outputs a high level sequentially, and finally, a hit signal is output at the output of register 3, activating the corresponding tri-state gate and outputting data from the data array to the bus.
[0097] In the event of a cache miss, if the cache does not store the data for the requested address, then none of the 8 tags can completely match the data for the requested address. When clock 3 triggers register 3, there is no high-level signal output, indicating a cache miss and ending the current cache access process.
[0098] This application provides a cache address circuit based on magnetic random access memory (MRMemory). It uses a MRMemory array to hierarchically store tags. When the decoder selects a tag to access the cache address circuit, it performs hierarchical comparisons on the tags at the requested address. Then, the hit signal obtained from the hierarchical comparison is sent to a tri-state gate to determine whether to send the cached data onto the bus. This scheme eliminates the need to read and compare tags for all addresses, reducing the number of reads and thus lowering the probability of misreading data when accessing the cache address circuit, thereby improving the data reliability of the cache address circuit. Furthermore, hierarchical tag comparison eliminates many unnecessary comparison operations, significantly reducing the power consumption of the cache address circuit.
[0099] This application also provides a circuit system, which includes a cache address circuit based on a magnetic random access memory as described above.
[0100] This application also provides an electronic device, which includes a processor and a cache, the cache including a cache address circuit based on a magnetic random access memory as described above.
[0101] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0102] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer circuit elements than shown, or combine certain circuit elements, or different circuit elements.
[0103] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0104] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0105] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.
Claims
1. A cache address circuit based on a magnetic random access memory, characterized in that, The circuit includes: a decoder, a magnetic random access memory array, and multiple tri-state gates; The magnetic random access memory array is used for hierarchical storage of tags; The decoder is used to select the tag stored in the magnetic random access memory array; The tri-state gate is used to receive the hit signal output by each of the tags in the magnetic random access memory array, and send the cached data of the corresponding channel to the bus. The magnetic random access memory array includes multiple magnetic random access memory cells, multiple registers, and buffers; The magnetic random access memory unit is used to store the tag; The buffer is used to output a high level after charging; The register is configured to output a high level when the requested tag matches the tag selected by the decoder; The magnetic random access memory array includes multiple array element circuits; Each array element circuit includes multiple unit circuits, each unit circuit includes multiple levels of unit sub-circuits, and each level of unit sub-circuit includes multiple magnetic random access memory units. The unit sub-circuits in each stage of the unit circuit have a sequential order. The output of each stage of the unit sub-circuit is connected to the input of a register. The register corresponding to the last stage of the unit sub-circuit is used as the endpoint register. The output of each endpoint register is connected to a tri-state gate. The outputs of all the other registers except the endpoint register are connected to the input of the corresponding next stage of the unit sub-circuit. The input of each buffer is connected to the output of the last stage of the unit sub-circuit of each unit circuit, the output of each buffer is connected to the input of one of the endpoint registers, and the output of each endpoint register is connected to one of the tri-state gates.
2. The cache address circuit based on a magnetic random access memory according to claim 1, characterized in that, Each of the magnetic random access memory cells includes multiple spin-orbit torque magnetic tunnel junctions and multiple transistors; The spin-orbit torque magnetic tunnel junction is used to store the tag. The transistor is used to control the reading and writing of the spin-orbit torque magnetic tunnel junction.
3. The cache address circuit based on a magnetic random access memory according to claim 1, characterized in that, Each of the magnetic random access memory cells includes a first spin-orbit torque magnetic tunnel junction, a second spin-orbit torque magnetic tunnel junction, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, all of which are NMOS transistors; Wherein, the gate of the first transistor is connected to the first read word line, the drain is connected to the input terminal of the magnetic random access memory cell, and the source is connected to the first port of the first spin-orbit torque magnetic tunnel junction. The gate of the second transistor is connected to the second read word line, the drain is connected to the input terminal of the magnetic random access memory cell, and the source is connected to the first port of the second spin-orbit torque magnetic tunnel junction. The gates of the third, fourth, and fifth transistors are all connected to the write word line; the drain of the third transistor is connected to the bit line, and the source is connected to the output terminal of the magnetic random access memory cell; the drain of the fourth transistor is connected to the first port of the first spin-orbit torque magnetic tunnel junction, and the source is connected to the source line; the drain of the fifth transistor is connected to the second port of the second spin-orbit torque magnetic tunnel junction, and the source is connected to the source line. The output terminal of the magnetic random access memory unit is connected to the second port of the first spin-orbit torque magnetic tunnel junction and the first port of the second spin-orbit torque magnetic tunnel junction.
4. The cache address circuit based on a magnetic random access memory according to claim 1, characterized in that, The decoder includes a group decoder and a tag decoder; The group decoder is used to select a group of array element circuits as the target array element circuit from each group of array element circuits according to the requested address. The tag decoder is used to select the spin-orbit torque magnetic tunnel junction corresponding to the target tag in the target array circuit; wherein the target tag is the tag requested in the request address, and the magnetic random access memory unit includes a plurality of the spin-orbit torque magnetic tunnel junctions.
5. The cache address circuit based on a magnetic random access memory according to claim 1, characterized in that, The magnetic random access memory array includes multiple array element circuits; Each array element circuit includes 8 unit circuits, each unit circuit includes 4 levels of unit sub-circuits, and each level of unit sub-circuit includes 8 magnetic random access memory units. Each of the aforementioned registers is an 8-bit register.
6. A circuit system, characterized in that, The circuit system includes a cache address circuit based on a magnetic random access memory as described in any one of claims 1 to 5.
7. An electronic device, characterized in that, The electronic device includes a processor and a cache, the cache including a cache address circuit based on a magnetic random access memory as described in any one of claims 1 to 5.