Shallow trench isolation unit and preparation method thereof, semiconductor device and preparation method thereof

Abstract

The present invention provides a shallow trench isolation unit and a preparation method thereof, a semiconductor device and a preparation method thereof. The preparation method of the shallow trench isolation unit forms a shallow trench isolation structure with a preset step height on a substrate, and forms a silicon nitride protection layer on the isolation layer of the shallow trench isolation structure; the silicon nitride protection layer is used to protect the isolation layer, so that the isolation layer is not lost in the subsequent process, so that the shallow trench isolation structure maintains the preset step height; and the silicon nitride layer is removed in the dry etching of the gate sidewall. Therefore, the present invention can effectively and accurately control the step height of the shallow trench isolation structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a shallow trench isolation unit and a preparation method thereof, a semiconductor device and a preparation method thereof. Background Art

[0002] As the integration of large-scale integrated circuits continues to increase, most of the isolation trenches between active areas of components of 0.18um and below are made using shallow trench isolation (STI) technology.

[0003] In the preparation process of shallow trench isolation structure, step height adjustment is a very critical process. Generally speaking, the height of the isolation layer (usually silicon dioxide) of the shallow trench isolation structure must be higher than the active area, and the step height of the shallow trench isolation structure needs to be controlled within a set height range. This is because the step height of the shallow trench isolation structure has a great influence on the dry etching after the polysilicon deposition is completed. Due to the anisotropy of dry etching, if the step height of the shallow trench isolation structure is too high or too low, it will cause polysilicon to remain at the edge of the junction between the active area and the shallow trench isolation structure (such as Figure 1 as well as Figure 2 As shown), resulting in a short circuit in the semiconductor device circuit.

[0004] In addition, considering that after the shallow trench isolation structure is prepared, it will go through multiple pickling steps (for example, using a mixed acid solution containing hot phosphoric acid and dilute hydrofluoric acid to remove silicon nitride, multiple pickling to remove photoresist during well area ion implantation, pickling to remove pad silicon dioxide layer, pickling to remove natural oxide layer before thick gate oxide layer growth, pickling to remove thick gate oxide layer and photoresist, pickling to remove natural oxide layer before thin gate oxide layer growth, etc.), these steps will have a greater impact on the step height of the shallow trench isolation structure. Therefore, it is very important to control the final step height.

[0005] At present, the commonly used method for controlling step height in the industry is to calculate the amount of damage to the silicon dioxide layer of the shallow trench isolation structure caused by each pickling, and infer how to set the initial step height based on the damage. However, this method has too many interference factors. Due to the instability caused by the fluctuation of the machine, different batches of products may have different amounts of damage to the silicon dioxide of the shallow trench isolation structure during each pickling process. Therefore, this method is difficult to achieve effective and precise control of the step height, and short circuit problems caused by polysilicon residues are prone to occur, which will have a great impact on the performance and yield of the chip. In addition, monitoring the amount of damage to the silicon dioxide of the shallow trench isolation structure during the pickling process requires adding multiple steps to measure the thickness of the silicon dioxide, which increases the cost of chip manufacturing.

[0006] Therefore, how to achieve effective and precise control of the step height of the shallow trench isolation structure has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0007] The present invention provides a shallow trench isolation unit and a preparation method thereof, a semiconductor device and a preparation method thereof, and an electronic device, so as to solve the problem of how to effectively and accurately control the step height of a shallow trench isolation structure.

[0008] According to a first aspect of the present invention, a method for preparing a shallow trench isolation unit is provided, comprising:

[0009] providing a substrate;

[0010] forming a shallow trench isolation structure on the substrate, wherein the shallow trench isolation structure comprises a shallow trench and an isolation layer filled in the shallow trench, wherein the shallow trench isolation structure has a preset step height;

[0011] A silicon nitride protective layer is formed on the surface of the isolation layer to protect the isolation layer so that the shallow trench isolation structure maintains a preset step height in a subsequent process; and the silicon nitride protective layer is removed during dry etching of the gate sidewall; wherein the silicon nitride protective layer is formed on the surface of the isolation layer, specifically comprising:

[0012] Depositing a silicon nitride film on the substrate, wherein the silicon nitride film covers the isolation layer and other areas of the substrate;

[0013] A first patterned mask layer is formed on the silicon nitride film, and the silicon nitride film is etched using the first patterned mask layer as a mask to remove the silicon nitride film in other areas and only retain the silicon nitride film corresponding to the isolation layer to form the silicon nitride protective layer.

[0014] Optionally, forming the shallow trench isolation structure on the substrate includes forming the shallow trench on the substrate and filling an isolation layer in the shallow trench, wherein forming the shallow trench on the substrate specifically includes:

[0015] forming a first stop layer on the substrate in a direction away from the substrate, wherein the first stop layer comprises a pad silicon dioxide layer and a pad silicon nitride layer sequentially formed in a direction away from the substrate;

[0016] A second patterned mask layer is formed on the substrate, and the first portion of the substrate and the first portion of the first stop layer are selectively etched using the second patterned mask layer as a mask to form a shallow trench in the substrate.

[0017] Optionally, after forming the shallow trench in the substrate, the method further includes:

[0018] The first portion of the pad silicon nitride layer is etched back to expose the first portion of the pad silicon dioxide layer.

[0019] Optionally, a size of the silicon nitride protection layer defined on the first patterned mask layer is larger than a size of the groove defined on the second patterned mask layer.

[0020] Optionally, filling the isolation layer in the shallow trench specifically includes:

[0021] forming a lining silicon dioxide layer on the surface of the shallow trench;

[0022] Depositing a silicon dioxide layer on the substrate, wherein the silicon dioxide layer fills the shallow trench and covers other areas of the substrate;

[0023] Performing a planarization process on the surface of the substrate, wherein the pad silicon nitride layer serves as a stop layer for the planarization process;

[0024] The isolation layer in the shallow trench is etched, and the thickness of the isolation layer is adjusted to a first set value so that the shallow trench isolation structure has a preset step height.

[0025] Optionally, forming the lining silicon dioxide layer on the surface of the shallow trench specifically includes:

[0026] The lining silicon dioxide layer is formed on the surface of the shallow trench by high temperature annealing.

[0027] Optionally, etching the isolation layer so that the shallow trench isolation structure has a preset step height specifically includes:

[0028] The isolation layer is wet-etched using a mixed acid solution containing hydrofluoric acid to remove a portion of the isolation layer, so that the shallow trench isolation structure has a preset step height.

[0029] According to a second aspect of the present invention, a shallow trench isolation unit is provided, comprising:

[0030] substrate;

[0031] A shallow trench isolation structure is formed on the substrate; the shallow trench isolation structure comprises a shallow trench and an isolation layer filled in the shallow trench, wherein the shallow trench isolation structure has a preset step height;

[0032] A silicon nitride protective layer is formed on the surface of the isolation layer and is used to protect the isolation layer so that the shallow trench isolation structure maintains a preset step height during subsequent process steps; and the silicon nitride protective layer is removed during dry etching of the gate sidewall.

[0033] According to a third aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0034] Prepare a shallow trench isolation unit using the method for preparing a shallow trench isolation unit according to any one of the first aspects of the present invention;

[0035] A process for forming a gate and its sidewalls is performed to prepare a semiconductor device; wherein the silicon nitride protective layer is used to protect the isolation layer so that the shallow trench isolation structure maintains a preset step height during the process of preparing the semiconductor device, and the silicon nitride protective layer is removed during the dry etching of the gate sidewalls.

[0036] According to a fourth aspect of the present invention, there is provided a semiconductor device manufactured using the method for manufacturing a semiconductor device according to the third aspect of the present invention.

[0037] In a shallow trench isolation unit and a preparation method thereof, a semiconductor device and a preparation method thereof provided by the present invention, a shallow trench isolation structure with a preset step height is formed on a substrate, and a silicon nitride protection layer is formed on the isolation layer of the shallow trench isolation structure; the silicon nitride protection layer is used to protect the isolation layer so that the isolation layer is not lost in the subsequent process, thereby maintaining the preset step height of the shallow trench isolation structure; and the silicon nitride layer is removed in the dry etching of the gate sidewall. Thus, the present invention can effectively and accurately control the step height of the shallow trench isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 It is a schematic diagram of the effect of polysilicon residue caused by excessively high step height of the shallow trench isolation structure in the prior art;

[0040] Figure 2 It is a schematic diagram of the effect of polysilicon residue caused by too low step height of shallow trench isolation structure in the prior art;

[0041] Figure 3It is a schematic flow chart of a method for preparing a shallow trench isolation unit provided by an embodiment of the present invention;

[0042] Figure 4-Figure 16 A schematic diagram of a device structure formed by the main steps of a method for preparing a shallow trench isolation unit provided in one embodiment of the present invention;

[0043] Fig.17 The process diagram of the method for preparing a semiconductor device provided by one embodiment of the present invention is as follows Figure 1 ;

[0044] Figure 18-Figure 26 It is a schematic diagram of a device structure corresponding to the main steps of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0045] Fig. 27 Schematic diagram of a method for preparing a semiconductor device according to another embodiment of the present invention Figure 2 ;

[0046] Figure 28-30 is a schematic diagram of a device structure corresponding to the main steps of a method for preparing a semiconductor device provided by another embodiment of the present invention;

[0047] Description of reference numerals:

[0048] 11- substrate;

[0049] 12- pad silicon dioxide layer;

[0050] 13- pad silicon nitride layer;

[0051] 14- shallow groove;

[0052] 15- lining silicon dioxide layer;

[0053] 161-silicon dioxide layer;

[0054] 16- isolation layer;

[0055] 17-silicon nitride protective layer;

[0056] 18-a first patterned mask layer;

[0057] 181-photoresist;

[0058] 182- a third patterned mask layer;

[0059] 19-thick gate oxide layer;

[0060] 20-thin gate oxide layer;

[0061] 211-polysilicon material;

[0062] 21-polysilicon layer;

[0063] 22-silicon dioxide protective layer;

[0064] 23-First silicon nitride layer. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0067] In view of the problem that it is difficult to effectively and accurately control the step height of a shallow trench isolation structure in the prior art, the present invention provides a shallow trench isolation unit and a preparation method thereof, a semiconductor device and a preparation method thereof, and an electronic device. The preparation method of the shallow trench isolation unit forms a shallow trench isolation structure with a preset step height on a substrate, and forms a silicon nitride protective layer on the isolation layer of the shallow trench isolation structure; the silicon nitride protective layer is used to protect the isolation layer so that the isolation layer is not lost in the subsequent process, thereby maintaining the preset step height of the shallow trench isolation structure; and the silicon nitride layer is removed in the dry etching of the gate sidewall. Thus, the present invention can effectively and accurately control the step height of the shallow trench isolation structure.

[0068] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0069] Please refer to Figure 3 , combined with Figure 4-Figure 16 According to an embodiment of the present invention, a method for preparing a shallow trench isolation unit is provided, comprising:

[0070] S11: providing a substrate 11.

[0071] In one implementation, the substrate 11 is a silicon substrate. Of course, the present invention is not limited to the specific material of the substrate, and it may also be a SiC substrate, etc. Those skilled in the art may select a suitable substrate material as needed.

[0072] S12: forming a shallow trench isolation structure on the substrate 11, wherein the shallow trench isolation structure comprises a shallow trench 14 and an isolation layer 16 filled in the shallow trench, wherein the shallow trench isolation structure has a preset step height.

[0073] In one embodiment, forming the shallow trench isolation structure in step S12 specifically includes the following steps:

[0074] S121: forming a first stop layer on the substrate 11 in a direction away from the substrate 11, wherein the first stop layer comprises a pad silicon dioxide layer 12 and a pad silicon nitride layer 13 sequentially formed in a direction away from the substrate 11; a schematic diagram of the device structure after forming the pad silicon dioxide layer 12 is shown in FIG. Figure 4 As shown, the schematic diagram of the device structure after forming the pad silicon nitride layer 13 is as shown Figure 5 shown.

[0075] The pad silicon dioxide layer 12 can reduce the stress of the pad silicon nitride layer 13 on the surface of the substrate 11 , and the pad silicon dioxide layer 12 is not affected by hot phosphoric acid, so it can be used as a stop layer for removing the pad silicon nitride layer 13 in subsequent steps.

[0076] The pad silicon nitride layer 13 can be used as a hard mask for dry etching of the active area; in some examples, the thickness of the pad silicon nitride layer 13 is a second set value, and the thickness of the pad silicon nitride layer 13 determines the initial step height of the shallow trench isolation structure, and the initial step height is greater than the preset step height.

[0077] S122: forming a second patterned mask layer on the first stop layer, and using the second patterned mask layer as a mask, selectively etching a first portion of the first stop layer and a first portion of the substrate 11 to form a shallow trench 14 in the substrate 11; the schematic diagram of the device structure after forming the shallow trench 14 is as shown in FIG. Figure 6 shown.

[0078] Specifically, the second patterned mask layer can be a patterned photoresist layer, and specifically, a photoresist can be coated on the first stop layer, and the photoresist is exposed and developed to form the second patterned mask layer, and the second patterned mask layer is used to define the pattern of the shallow trench isolation region on the substrate 11; and the second patterned mask layer is used as a mask, and the first part of the first stop layer and the first part of the substrate 11 are selectively etched by dry etching to form a shallow trench 14 in the substrate 11. Of course, the present invention is not limited to this, and the second patterned mask layer is not limited to photoresist, and can also be other mask types.

[0079] S123 : filling the shallow trench 14 with an isolation layer 16 .

[0080] Among them, S123 specifically includes:

[0081] S1231: forming a lining silicon dioxide layer 15 on the surface of the shallow trench 14. The schematic diagram of the device structure after this step is completed is as follows: Figure 8 shown.

[0082] In a specific embodiment, the lining silicon dioxide layer 15 is formed on the surface of the shallow trench 14 by high temperature annealing; the lining silicon dioxide layer 15 can repair the lattice damage to the surface of the substrate 11 caused by plasma sputtering in the dry etching in step S122.

[0083] S1232: Depositing a silicon dioxide layer 161 on the substrate 11, wherein the silicon dioxide layer 161 fills the shallow trench 14 and covers other areas of the substrate 11; a schematic diagram of the device structure after this step is completed is shown in FIG. Fig. 9 shown.

[0084] Specifically, for example, a high aspect ratio thin film deposition technology can be used to deposit a silicon dioxide material on the substrate 11, and the silicon dioxide material fills the shallow trench 14 and covers other areas of the substrate 11 to form the silicon dioxide layer 161; wherein the silicon dioxide layer filling the shallow trench 14 is formed on the surface of the lining silicon dioxide layer 15, and the height of the silicon dioxide layer formed on the surface of the lining silicon dioxide layer 15 is higher than the pad silicon nitride layer 13.

[0085] The above-mentioned high aspect ratio thin film deposition technology can specifically be a HARP process, an eHARP process, a flow chemical vapor deposition (FCVD) technology, etc. The present invention is not limited to this, and technicians in this field can select a suitable process as needed.

[0086] S1233: Using the pad silicon nitride layer 13 as a stop layer, the surface of the substrate 11 is planarized to form an isolation layer 16 in the shallow trench 14. The schematic diagram of the device structure after the planarization process is as follows: Fig.10 shown.

[0087] Specifically, the planarization process is, for example, CMP. Of course, the present invention is not limited thereto, and other planarization process methods are also within the protection scope of the present invention.

[0088] S1234: Etching the isolation layer 16 in the shallow trench 14, adjusting the thickness of the isolation layer 16 to a first set value, so that the shallow trench isolation structure has a preset step height. The schematic diagram of the device structure after this step is completed is as shown in FIG. Fig.11 shown.

[0089] In a specific implementation, the isolation layer 16 may be wet-etched using a mixed acid solution containing hydrofluoric acid to remove a portion of the isolation layer 16 , so that the shallow trench isolation structure has a preset step height.

[0090] As a preferred implementation, after step S122 and before step S123, the following is further included:

[0091] S1221: etching back the first part of the pad silicon nitride layer 13 to expose the first part of the pad silicon dioxide layer 12. The schematic diagram of the device structure after this step is completed is as follows: Figure 7 As shown;

[0092] Specifically, a mixed acid solution containing hot phosphoric acid may be used to etch back the first portion of the pad silicon nitride layer 13 to expose the first portion of the pad silicon dioxide layer 12;

[0093] This is to improve the effect of subsequently filling the isolation layer into the shallow trench, reduce the undercutting of the filled isolation layer caused by multiple pickling in the subsequent process, and thus prevent the generation of parasitic transistor effect.

[0094] After the shallow trench isolation structure is formed on the substrate 11 by the above method, considering that there will be multiple pickling steps in the subsequent chip manufacturing process, these steps will have a great impact on the step height of the shallow trench isolation structure. Therefore, in one embodiment, the embodiment of the present invention also includes step S13 after step S12. S13: Form a silicon nitride protective layer 17 on the surface of the isolation layer 16 to protect the isolation layer 16 so that the shallow trench isolation structure maintains a preset step height during subsequent processes; and the silicon nitride protective layer is removed during the dry etching of the gate sidewall; wherein, forming the silicon nitride protective layer 17 on the surface of the isolation layer 16 specifically includes:

[0095] S131: Depositing a silicon nitride film on the substrate, wherein the silicon nitride film covers the isolation layer and other areas of the substrate; the schematic diagram of the device structure after this step is completed is as follows Fig.12 shown.

[0096] Specifically, the silicon nitride film may be deposited by, for example, atomic vapor deposition.

[0097] S132: forming a first patterned mask layer on the silicon nitride layer film, and etching the silicon nitride layer film using the first patterned mask layer as a mask to remove the silicon nitride layer film in other areas and retain only the silicon nitride layer film corresponding to the isolation layer to form the silicon nitride protective layer.

[0098] Wherein, in the case where the aforementioned steps S122 and S123 include S1221, the size of the silicon nitride protection layer 17 defined on the first patterned mask layer is larger than the size of the groove defined on the second patterned mask layer.

[0099] In one embodiment, S132 specifically includes:

[0100] S1321: Spin-coat photoresist 181 on the silicon nitride film. Fig.13 As shown;

[0101] In a specific implementation, the photoresist 181 includes a photolithography anti-reflection layer and a photoresist coated on the photolithography anti-reflection layer (not shown in the figure).

[0102] S1322: forming a first patterned mask layer 18 on the silicon nitride film, such as Fig.14 shown.

[0103] Specifically, a photoresist located in the isolation area of ​​the shallow trench 14 is exposed and developed using a photomask, wherein the photoresist is a negative photoresist; and then the unexposed photoresist is removed to form the first patterned mask layer 18 .

[0104] S1323: The silicon nitride layer film is etched using the first patterned mask layer 18 as a mask to remove the silicon nitride layer film in other areas, and only the silicon nitride layer film corresponding to the isolation layer 16 is retained to form the silicon nitride protective layer 17; the schematic diagram of the device structure after this step is completed is as follows: Fig.15 shown.

[0105] Specifically, the first patterned mask layer 18 is used as a mask, and a mixed acid solution containing hot phosphoric acid is used to wet etch away the silicon nitride film in other areas and the pad silicon nitride layer 13, leaving only the silicon nitride film corresponding to the isolation layer 16 to form the silicon nitride protective layer 17.

[0106] S1324: removing the first patterned mask layer 18. The schematic diagram of the device structure after this step is completed is as follows: Fig.16 shown.

[0107] Specifically, oxygen plasma ashing combined with inorganic oxidation is used to remove the first patterned mask layer 18. The oxygen plasma ashing combined with inorganic oxidation method includes: using oxygen to oxidatively decompose organic matter in the first patterned mask layer 18 (i.e., photoresist), and removing the photoresist residue on the surface of the silicon nitride protective layer 17 by a mixed acid solution containing dilute hydrofluoric acid, sulfuric acid, and SC1.

[0108] In the above steps, since only hot phosphoric acid solution will cause significant damage to silicon nitride in the chip manufacturing process, the pickling solution degumming process in step S1324 will not affect the silicon nitride protective layer 17. And since the subsequent process often uses a mixed acid solution containing dilute hydrofluoric acid for pickling, and the mixed acid solution containing dilute hydrofluoric acid hardly causes damage to the silicon nitride surface, the present invention can use the above-mentioned silicon nitride protective layer 17 in the subsequent process to protect the preset step height in the shallow trench isolation structure from being affected, thereby achieving the purpose of accurately controlling the step height of the shallow trench isolation structure.

[0109] In addition, please refer to Fig.16 Another embodiment of the present invention further provides a shallow trench isolation unit, comprising:

[0110] Substrate 11;

[0111] A shallow trench isolation structure is formed on the substrate 11; the shallow trench isolation structure comprises a shallow trench and an isolation layer 16 filled in the shallow trench, wherein the shallow trench isolation structure has a preset step height;

[0112] The silicon nitride protection layer 17 is formed on the surface of the isolation layer 16 to protect the isolation layer 16 so that the shallow trench isolation structure maintains a preset step height during subsequent processes; and the silicon nitride protection layer 17 is removed during the dry etching of the gate sidewall.

[0113] Please refer to Fig.17 , combined with Fig.16 , Figure 19-Figure 26 According to another embodiment of the present invention, there is also provided a method for preparing a semiconductor device, comprising:

[0114] S21: Prepare shallow trench isolation unit. The schematic diagram of the device structure after the shallow trench isolation unit is prepared is as follows: Fig.16 As shown; wherein, the process for preparing the shallow trench isolation unit is as shown in the above-mentioned method for preparing the shallow trench isolation unit.

[0115] S22: Execute a process for forming a gate and its sidewalls in preparing a semiconductor device; wherein the silicon nitride protective layer is used to protect the isolation layer so that the shallow trench isolation structure maintains a preset step height during the process of preparing the semiconductor device, and the silicon nitride protective layer is removed during the dry etching of the gate sidewalls.

[0116] In one embodiment, the gate forming process of preparing the semiconductor device in step S22 specifically includes the following steps:

[0117] S221: forming a well region.

[0118] Specifically, the semiconductor substrate 11 is ion-implanted multiple times using the patterned photoresist 181 as a masking layer for ion implantation to form a low-voltage N-type well region, a low-voltage P-type well region, a high-voltage N-type well region, and a high-voltage P-type well region; after the well regions are formed, the device Fig.19 As shown;.

[0119] In the process of forming the low voltage N-type well region, the low voltage P-type well region, the high voltage N-type well region and the high voltage P-type well region, the photoresist 181 needs to be used as a masking layer for ion implantation for many times (the device formed by the photoresist 181 as a masking layer can be, for example, Fig.18 As shown in the figure, after the corresponding well region is formed, an acid solution (e.g., a mixed acid solution containing dilute hydrofluoric acid, sulfuric acid, and SC1) is required to be used in the process of removing the photoresist 181. If there is no protection of the silicon nitride protection layer 17, the acid solution used in this process will damage the isolation layer 16, thereby affecting the step height of the shallow trench 14 isolation structure; and in the subsequent process steps, the acid solution containing dilute hydrofluoric acid will also damage the isolation layer 16 without the protection of the silicon nitride protection layer 17. It is under the protection of the silicon nitride protection layer 17 that the isolation layer 16 is not affected in these acid washing steps.

[0120] S222 : etching the pad silicon dioxide layer 12 to expose a first portion of the isolation layer 16 .

[0121] Specifically, the pad silicon dioxide layer 12 is etched with a solution containing dilute hydrofluoric acid to expose the first portion of the isolation layer 16; the schematic diagram of the device structure after etching the pad silicon dioxide layer 12 is as shown in FIG. Fig. 20 shown.

[0122] S223: depositing a thick gate oxide layer 19, wherein the thick gate oxide layer 19 covers the surface of the substrate 11. Fig.21 shown.

[0123] S224: forming a third patterned mask layer 182, wherein the third patterned mask layer 182 only covers the first portion of the deposited thick gate oxide layer 19; the schematic diagram of the device structure after forming the third patterned mask layer 182 is as shown in FIG. Fig. 22 shown.

[0124] S225: using the third patterned mask layer 182 as a mask, etching the first portion of the deposited thick gate oxide layer 19.

[0125] Specifically, a solution containing dilute hydrofluoric acid is used to wet-etch the first portion of the deposited thick gate oxide layer 19; the schematic diagram of the device structure after etching the first portion of the deposited thick gate oxide layer 19 is as shown in FIG. Fig.23 shown.

[0126] S226: removing the third patterned mask layer 182.

[0127] S227: depositing a thin gate oxide layer 20, wherein the thin gate oxide layer 20 covers the surface of the substrate 11; after the thin gate oxide layer 20 is deposited, the device is as follows Fig.24 shown.

[0128] S228: depositing polysilicon material 211, wherein the polysilicon material 211 wraps the shallow trench isolation unit and covers the surface of the thick gate oxide layer 19 and the thin gate oxide layer 20; after the polysilicon material 211 is deposited, the device is as follows: Fig.25 as shown.

[0129] S229 : selectively etching the first portion of the polysilicon material 211 to form a polysilicon layer 21 .

[0130] In one example, dry etching can be used to selectively etch the first portion of the polysilicon material 211 to form a polysilicon layer 21; after the polysilicon layer 21 is formed, the device is as follows: Fig.26 shown.

[0131] In summary, the dense silicon nitride protection layer 17 deposited on the surface of the isolation layer 16 can effectively protect the shallow trench isolation structure with a preset step height. In subsequent processes, there is no need to repeatedly measure the step height of the shallow trench isolation structure, which simplifies the chip manufacturing steps.

[0132] And because the shallow trench isolation structure has a precisely preset step height, there will be no device short-circuit problem caused by polysilicon residue in the subsequent process, ensuring the stable performance and yield of the semiconductor devices produced.

[0133] In one implementation, please refer to Fig. 27 The process of preparing the sidewall spacer of the semiconductor device in step S22 specifically includes the following steps:

[0134] S231 : oxidizing the surface of the polysilicon layer 21 to form a silicon dioxide protection layer 22 on the surface of the polysilicon layer 21 .

[0135] In one example, a high-temperature thermal oxidation method can be used to oxidize the surface of the polysilicon layer 21, and a silicon dioxide protective layer 22 can be formed on the surface of the polysilicon layer 21 to reduce the stress of the first silicon nitride layer 23 deposited in the subsequent process on the polysilicon layer 21; the thickness of the silicon dioxide protective layer 22 can be set to a relatively small value; after the silicon dioxide protective layer 22 is formed, the device such as Fig.28 shown.

[0136] S232 : depositing a first silicon nitride layer 23 .

[0137] Specifically, a first silicon nitride layer 23 is deposited on the substrate 11; the first silicon nitride layer 23 includes a first portion covering the silicon nitride protection layer 17, a second portion covering the side wall of the isolation layer 16, a third portion covering the surface of the thick gate oxide layer 19, a fourth portion covering the surface of the thin gate oxide layer 20, a fifth portion covering the surface of the polysilicon layer 21, and a sixth portion covering the side wall of the polysilicon layer 21; wherein the first silicon nitride layer 23 covering the polysilicon layer 21 is formed on the surface of the silicon dioxide protection layer 22; after the first silicon nitride layer 23 is deposited, the device is as follows Fig.29 shown.

[0138] S233: Dry-etching the first silicon nitride layer 23 to remove a first portion thereof covering the silicon nitride protection layer 17, a second portion covering the side wall of the isolation layer 16, a third portion covering the surface of the thick gate oxide layer 19, a fourth portion covering the surface of the thin gate oxide layer 20, a fifth portion covering the surface of the polysilicon layer 21, and the silicon nitride protection layer 17. The schematic diagram of the device structure after dry-etching the first silicon nitride layer 23 is shown in FIG. Fig.30 As shown. It can be seen that the silicon nitride protection layer 17 is removed during the dry etching of the gate sidewall. Therefore, the present invention adds a silicon nitride protection layer 17 to protect the isolation layer in the shallow trench isolation structure, so that the shallow trench isolation structure has a precisely preset step height, and no additional process is required to remove the silicon nitride protection layer 17; thus, the complexity of the subsequent semiconductor device preparation process is not caused while achieving the precise control of the step height of the shallow trench isolation structure.

[0139] Of course, the preparation process of the semiconductor device also includes other processes. The present invention only provides processes related to the shallow trench isolation structure. Other processes are prior arts and will not be described in detail in the present invention.

[0140] In addition, the present invention also provides a semiconductor device, which is prepared using the above-mentioned method for preparing the semiconductor structure.

[0141] In summary, the embodiment of the present invention forms a shallow trench isolation structure with a preset step height on a substrate, and forms a silicon nitride protection layer on the isolation layer of the shallow trench isolation structure; the silicon nitride protection layer is used to protect the isolation layer so that the isolation layer is not lost in the subsequent process, thereby maintaining the preset step height of the shallow trench isolation structure; and the silicon nitride layer is removed during the dry etching of the gate sidewall. Therefore, the present invention can effectively and accurately control the step height of the shallow trench isolation structure.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a shallow trench isolation unit, characterized in that: include: providing a substrate; forming a shallow trench isolation structure on the substrate, wherein the shallow trench isolation structure comprises a shallow trench and an isolation layer filled in the shallow trench, wherein the shallow trench isolation structure has a preset step height; Wherein, forming the shallow trench isolation structure on the substrate includes forming the shallow trench on the substrate and filling an isolation layer in the shallow trench; wherein, forming the shallow trench on the substrate specifically includes: forming a first stop layer on the substrate in a direction away from the substrate, wherein the first stop layer comprises a pad silicon dioxide layer and a pad silicon nitride layer sequentially formed in a direction away from the substrate; forming a second patterned mask layer on the substrate, and selectively etching a first portion of the substrate and a first portion of the first stop layer using the second patterned mask layer as a mask to form a shallow trench in the substrate; A silicon nitride protective layer is formed on the surface of the isolation layer to protect the isolation layer so that the shallow trench isolation structure maintains a preset step height in a subsequent process; and the silicon nitride protective layer is removed during dry etching of the gate sidewall; wherein the silicon nitride protective layer is formed on the surface of the isolation layer, specifically comprising: Depositing a silicon nitride film on the substrate, wherein the silicon nitride film covers the isolation layer and other areas of the substrate; A first patterned mask layer is formed on the silicon nitride layer film, and the silicon nitride layer film and the pad silicon nitride layer are etched using the first patterned mask layer as a mask to remove the silicon nitride layer film and the pad silicon nitride layer in other areas, leaving only the silicon nitride layer film corresponding to the isolation layer to form the silicon nitride protective layer.

2. The method for preparing a shallow trench isolation unit according to claim 1, characterized in that: After forming the shallow trench in the substrate, the method further includes: The first portion of the pad silicon nitride layer is etched back to expose the first portion of the pad silicon dioxide layer.

3. The method for preparing a shallow trench isolation unit according to claim 2, characterized in that: The size of the silicon nitride protection layer defined on the first patterned mask layer is larger than the size of the trench defined on the second patterned mask layer.

4. The method for preparing a shallow trench isolation unit according to claim 2, characterized in that: Filling the isolation layer in the shallow trench specifically includes: forming a lining silicon dioxide layer on the surface of the shallow trench; Depositing a silicon dioxide layer on the substrate, wherein the silicon dioxide layer fills the shallow trench and covers other areas of the substrate; Performing a planarization process on the surface of the substrate, wherein the pad silicon nitride layer serves as a stop layer for the planarization process; The isolation layer in the shallow trench is etched, and the thickness of the isolation layer is adjusted to a first set value so that the shallow trench isolation structure has a preset step height.

5. The method for preparing a shallow trench isolation unit according to claim 4, characterized in that: Forming the lining silicon dioxide layer on the surface of the shallow trench specifically includes: The lining silicon dioxide layer is formed on the surface of the shallow trench by high temperature annealing.

6. The method for preparing a shallow trench isolation unit according to claim 4, characterized in that: Etching the isolation layer so that the shallow trench isolation structure has a preset step height specifically includes: The isolation layer is wet-etched using a mixed acid solution containing hydrofluoric acid to remove a portion of the isolation layer, so that the shallow trench isolation structure has a preset step height.

7. A shallow trench isolation unit, characterized in that: Prepared by the method for preparing a shallow trench isolation unit according to any one of claims 1 to 6, comprising: substrate; A shallow trench isolation structure is formed on the substrate; the shallow trench isolation structure comprises a shallow trench and an isolation layer filled in the shallow trench, wherein the shallow trench isolation structure has a preset step height; A silicon nitride protective layer is formed on the surface of the isolation layer and is used to protect the isolation layer so that the shallow trench isolation structure maintains a preset step height during subsequent process steps; and the silicon nitride protective layer is removed during dry etching of the gate sidewall.

8. A method for preparing a semiconductor device, characterized in that: include: Prepare a shallow trench isolation unit using the method for preparing a shallow trench isolation unit according to any one of claims 1 to 6; A process for forming a gate and its sidewalls is performed to prepare a semiconductor device; wherein the silicon nitride protective layer is used to protect the isolation layer so that the shallow trench isolation structure maintains a preset step height during the process of preparing the semiconductor device, and the silicon nitride protective layer is removed during the dry etching of the gate sidewalls.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured using the method for manufacturing a semiconductor device according to claim 8.

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