A Fractional Frequency Phase-Locked Loop Based on Phase Interpolation and Sampling

Abstract

The present disclosure provides a fractional frequency phase-locked loop based on phase interpolation and sampling, the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop; the charge pump module is charged and discharged according to the reference clock signal, and the frequency locking module is controlled to perform frequency locking, and the frequency locking module outputs clock waveform signals of multiple phases to the phase interpolation module; the phase interpolation module interpolates the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selects the target clock waveform signal from the clock waveform signal and sends it to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines the sampling voltage and outputs it to the transconductance amplifier, and the transconductance amplifier converts the sampling voltage into the control current of the frequency locking module to control the frequency of the frequency locking module. The noise of the phase-locked loop can be effectively reduced, and the area is small.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular to a fractional frequency phase-locked loop based on phase interpolation and sampling. Background Art

[0002] A phase-locked loop is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to produce a target frequency. The frequency and phase of the oscillation signal inside the loop are controlled by an external reference signal, so that the output signal frequency automatically tracks the input signal frequency.

[0003] At present, subsampling technology can reduce the noise within the bandwidth of the phase-locked loop, but it is mainly used in integer phase-locked loops. In order to realize a fractional frequency phase-locked loop, the general practice is to add a time digital converter (TDC) module after the input clock, and use the fractional sigma-delta modulator to control the TDC module to realize fractional frequency division. However, this method requires the TDC module to have a high precision, otherwise it will introduce high noise and consume a lot of power. In addition, when realizing fractional frequency division, the bandwidth of the phase-locked loop must also be relatively low to suppress the noise of the fractional sigma-delta modulator, which also causes a large area problem. Summary of the invention

[0004] The disclosed embodiments at least provide a fractional-frequency phase-locked loop based on phase interpolation and sampling, which can effectively reduce the low-frequency phase noise of the phase-locked loop and suppress the sigma delta noise, thereby reducing the overall noise of the phase-locked loop while having a relatively small area.

[0005] The disclosed embodiment provides a fractional frequency phase-locked loop based on phase interpolation and sampling, comprising: a charge pump module, a frequency locking module, a phase interpolation module, a fractional sigma-delta modulator, a sampling circuit and a transconductance amplifier;

[0006] The sampling circuit, the transconductance amplifier, the frequency locking module and the phase interpolation module are connected in sequence; the charge pump module is connected in parallel between the input end of the sampling circuit and the output end of the transconductance amplifier; the fractional sigma-delta modulator is connected to the phase interpolation module;

[0007] The input of the sampling circuit and the charge pump module is a reference clock signal, and the output of the frequency locking module is used as the clock output of the phase-locked loop;

[0008] The charge pump module performs charging and discharging according to the reference clock signal, controls the frequency locking module to perform frequency locking, and the frequency locking module outputs clock waveform signals of multiple phases to the phase interpolation module;

[0009] The phase interpolation module interpolates the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signal and sends it to the sampling circuit;

[0010] The sampling circuit samples the rising edge of the target clock waveform signal, determines a sampling voltage, and outputs the sampling voltage to the transconductance amplifier, which converts the sampling voltage into a control current of the frequency locking module to control the frequency of the frequency locking module.

[0011] In an optional implementation, the charge pump module includes a frequency detector and a charge pump;

[0012] The frequency detector generates an upper switch control signal and a lower switch control signal according to the input reference clock signal;

[0013] The charge pump performs charging and discharging according to the upper switch control signal and the lower switch control signal.

[0014] In an optional implementation, the frequency locking module includes: a low-pass filter and a ring oscillator, wherein:

[0015] The low-pass filter receives the charge and discharge signal of the charge pump module and converts the charge and discharge signal into a control voltage of the ring oscillator;

[0016] The ring oscillator starts to oscillate after receiving the control voltage to achieve frequency locking.

[0017] In an optional implementation, the fractional sigma-delta modulator includes a sigma-delta modulation unit and an accumulator;

[0018] The input of the fractional sigma-delta modulator is a control word signal, wherein the control word signal consists of an integer part and a fractional part;

[0019] After adding the preset deviation signal to the decimal part of the control word signal, the decimal control signal for controlling the phase interpolation module to perform phase interpolation is output through the accumulator, wherein the deviation signal is used to control the decimal part interval range of the control word signal.

[0020] In an optional implementation, the phase interpolation module includes: a timing controller, a decoder, a current digital-to-analog converter, and an interpolation capacitor;

[0021] The decoder converts the fractional control signal into a control signal for the current digital-to-analog converter, wherein the control signal is used to control the output current of the current digital-to-analog converter;

[0022] The current digital-to-analog converter outputs current to charge the interpolation capacitor, and the voltage change speed of the interpolation capacitor is affected according to the size of the output current to achieve phase interpolation;

[0023] After receiving the clock waveform signal output by the frequency locking module, the timing controller resets the voltage value of the interpolation capacitor according to the clock waveform signal, and after the reset stops, the interpolation capacitor starts to charge.

[0024] In an optional implementation, the sampling circuit includes a first delay unit, a second delay unit, a first inverter, a second inverter, a first transmission gate, a second transmission gate, and a sampling capacitor;

[0025] The first delay unit is connected to the first inverter; the second delay unit is connected to the second inverter; an input end of the second delay unit is connected between the first delay unit and the first inverter;

[0026] One end of the first transmission gate is connected to the phase interpolation module, and the other end is connected to the second transmission gate; the second transmission gate is connected to the transconductance amplifier;

[0027] One end of the sampling capacitor is connected between the first transmission gate and the second transmission gate, and the other end of the sampling capacitor is grounded;

[0028] The control terminal of the first transmission gate is connected to the first delay unit, and the inverse control terminal of the first transmission gate is connected to the first inverter;

[0029] A control terminal of the second transmission gate is connected to the second delay unit, and an inverting control terminal of the second transmission gate is connected to the second inverter.

[0030] In an optional implementation, the reference clock signal is input to the first delay unit, the first delay unit outputs a sampling clock signal, and then the second delay unit processes and outputs a holding clock signal;

[0031] The first transmission gate samples the target clock waveform signal according to the sampling clock signal, and keeps the sampled voltage in the sampling capacitor;

[0032] After the sampling is completed, the holding clock signal is released, and the sampled voltage on the sampling capacitor is output to the transconductance amplifier.

[0033] The embodiment of the present disclosure further provides a control method of a fractional frequency phase-locked loop based on phase interpolation and sampling, which is applied to the fractional frequency phase-locked loop based on phase interpolation and sampling as described in any of the above embodiments, wherein the fractional frequency phase-locked loop comprises: the charge pump module, the frequency locking module, the phase interpolation module, the fractional sigma-delta modulator, the sampling circuit and the transconductance amplifier, and the method comprises:

[0034] Inputting reference clock signals to the sampling circuit and the charge pump module respectively, and outputting the clock from the output end of the frequency locking module;

[0035] Controlling the charge pump module to charge and discharge according to the reference clock signal, controlling the frequency locking module to lock the frequency, and having the frequency locking module output clock waveform signals of multiple phases to the phase interpolation module;

[0036] Controlling the phase interpolation module to interpolate the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selecting a target clock waveform signal from the clock waveform signal to send to the sampling circuit;

[0037] The sampling circuit is controlled to sample the rising edge of the target clock waveform signal, determine a sampling voltage, and output the sampling voltage to the transconductance amplifier, which converts the sampling voltage into a control current of the frequency locking module to control the frequency of the frequency locking module.

[0038] An embodiment of the present disclosure also provides an electronic device, including: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory through the bus, and when the machine-readable instructions are executed by the processor, the control method of the fractional-frequency phase-locked loop based on phase interpolation and sampling, or steps in any possible implementation of the control method of the fractional-frequency phase-locked loop based on phase interpolation and sampling is performed.

[0039] An embodiment of the present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the control method of the fractional-frequency phase-locked loop based on phase interpolation and sampling or the steps of any possible implementation of the control method of the fractional-frequency phase-locked loop based on phase interpolation and sampling is executed.

[0040] The embodiments of the present disclosure also provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the above-mentioned control method of a fractional-frequency phase-locked loop based on phase interpolation and sampling, or the steps in any possible implementation of the above-mentioned control method of a fractional-frequency phase-locked loop based on phase interpolation and sampling.

[0041] The embodiment of the present disclosure provides a fractional frequency phase-locked loop based on phase interpolation and sampling, including: the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop; the charge pump module is charged and discharged according to the reference clock signal, the frequency locking module is controlled to perform frequency locking, and the frequency locking module outputs a plurality of phases of clock waveform signals to the phase interpolation module; the phase interpolation module interpolates the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selects the target clock waveform signal from the clock waveform signal and sends it to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines the sampling voltage, and outputs the sampling voltage to the transconductance amplifier, and the transconductance amplifier converts the sampling voltage into the control current of the frequency locking module to control the frequency of the frequency locking module. The low-frequency phase noise of the phase-locked loop can be effectively reduced, and the noise of sigma delta can be suppressed at the same time, so that the overall noise of the phase-locked loop is reduced, and at the same time, the area is relatively small.

[0042] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic structural diagram of a fractional frequency phase-locked loop based on phase interpolation and sampling provided by an embodiment of the present disclosure is shown;

[0045] Figure 2 A schematic structural diagram of a fractional sigma-delta modulator provided by an embodiment of the present disclosure is shown;

[0046] Figure 3A schematic diagram of the structure of a phase interpolation module provided by an embodiment of the present disclosure is shown;

[0047] Figure 4 A schematic diagram of the structure of a sampling circuit provided by an embodiment of the present disclosure is shown;

[0048] Figure 5 A flow chart of a control method of a fractional frequency phase-locked loop based on phase interpolation and sampling provided by an embodiment of the present disclosure is shown;

[0049] Figure 6 A schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0051] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0052] The term "and / or" herein only describes an association relationship, indicating that three relationships may exist. For example, A and / or B may represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set consisting of A, B, and C.

[0053] According to research, subsampling technology can reduce the noise within the bandwidth of the phase-locked loop, but it is mainly used in integer phase-locked loops. In order to realize a fractional frequency-division phase-locked loop, the general practice is to add a time-to-digital converter (TDC) module after the input clock, and use a fractional sigma-delta modulator to control the TDC module to realize fractional frequency division. However, this method requires the TDC module to have a high precision, otherwise it will introduce high noise and consume a lot of power. In addition, when realizing fractional frequency division, the bandwidth of the phase-locked loop must also be relatively low to suppress the noise of the fractional sigma-delta modulator, which also causes a large area problem.

[0054] Based on the above research, the present disclosure provides a fractional frequency phase-locked loop based on phase interpolation and sampling, including: the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop; the charge pump module is charged and discharged according to the reference clock signal, the frequency locking module is controlled to perform frequency locking, and the frequency locking module outputs multiple phases of clock waveform signals to the phase interpolation module; the phase interpolation module interpolates the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selects the target clock waveform signal from the clock waveform signal and sends it to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines the sampling voltage, and outputs the sampling voltage to the transconductance amplifier, and the transconductance amplifier converts the sampling voltage into the control current of the frequency locking module to control the frequency of the frequency locking module. It can effectively reduce the low-frequency phase noise of the phase-locked loop, suppress the noise of sigma delta, reduce the overall noise of the phase-locked loop, and have a relatively small area.

[0055] To facilitate understanding of this embodiment, firstly, a fractional frequency phase-locked loop based on phase interpolation and sampling disclosed in the embodiment of the present disclosure is described in detail, see Figure 1 , which is a schematic diagram of the structure of a fractional-frequency phase-locked loop 100 based on phase interpolation and sampling provided in an embodiment of the present disclosure.

[0056] like Figure 1 As shown in the figure, the fractional frequency phase-locked loop 100 based on phase interpolation and sampling includes: a charge pump module 110, a frequency locking module 120, a phase interpolation module 130, a fractional sigma-delta modulator 140, a sampling circuit 150 and a transconductance amplifier 160. The charge pump module 110 includes a frequency detector 111 and a charge pump 112; the frequency locking module 120 includes: a low-pass filter 121 and a ring oscillator 122.

[0057] Specifically, the sampling circuit 150, the transconductance amplifier 160, the frequency locking module 120 and the phase interpolation module 130 are connected in sequence; the charge pump module 110 is connected in parallel between the input end of the sampling circuit 150 and the output end of the transconductance amplifier 160; and the fractional sigma-delta modulator 140 is connected to the phase interpolation module 130.

[0058] In a specific implementation, the inputs of the sampling circuit 150 and the charge pump module 110 are reference clock signals, and the output end of the frequency locking module 120 is used as the clock output of the fractional frequency phase-locked loop 100 based on phase interpolation and sampling.

[0059] Here, the charge pump module 110 performs charging and discharging according to the input reference clock signal, and controls the frequency locking module 120 to perform frequency locking. After the frequency is locked, the frequency locking module 120 outputs clock waveform signals of multiple phases to the phase interpolation module 130 .

[0060] Specifically, the reference clock signal is input to the phase frequency detector 111, which generates an upper switch control signal UP and a lower switch control signal DN of the charge pump 112 according to the input reference clock signal; the charge pump 112 is charged and discharged according to the upper switch control signal UP and the lower switch control signal DN.

[0061] Here, the clock signal output by the phase interpolation module 130 is also input to the frequency detector 111. The frequency detector 111 uses the reference clock signal as the reference signal and the clock signal output by the phase interpolation module 130 as the signal to be locked. The frequency and phase difference between the reference clock signal and the clock signal output by the phase interpolation module 130 are then compared and output in the form of voltage.

[0062] When the phase of the signal to be locked lags, the detector 111 outputs an upper switch control signal UP to drive the charge pump 112 to output a positive voltage pulse; when the phase of the signal to be locked leads, the detector 111 outputs a lower switch control signal DN to drive the charge pump 112 to output a negative voltage pulse.

[0063] It should be noted that the phase of the clock waveform signal output by the frequency locking module 120 can be set according to actual needs and is not specifically limited here.

[0064] Furthermore, the low-pass filter 121 receives the charge and discharge signals of the charge pump 112 in the charge pump module 110 and converts the charge and discharge signals into the control voltage of the ring oscillator 122; the ring oscillator 122 starts to oscillate after receiving the control voltage output by the low-pass filter 121 to achieve frequency locking.

[0065] Furthermore, the phase interpolation module 130 interpolates the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator 140 , and selects a target clock waveform signal from the clock waveform signal and sends it to the sampling circuit 150 .

[0066] Here, the phase interpolation module 130 uses the fractional signal generated by the fractional sigma-delta modulator 140 to interpolate the phase to make the phase of the waveform signal more refined. At the same time, among the multiple phase clock waveform signals output by the frequency locking module 120, a certain phase clock waveform signal is selected as the target clock waveform signal to be output to the sampling circuit 150.

[0067] It should be noted that the selection of the target clock waveform signal can be set according to actual needs and is not specifically limited here.

[0068] Furthermore, after receiving the target clock waveform signal output by the phase interpolation module 130, the sampling circuit 150 samples the rising edge of the target clock waveform signal, determines the sampling voltage, and outputs the sampling voltage to the transconductance amplifier 160. The transconductance amplifier 160 converts the sampling voltage into a control current of the frequency locking module 120 to control the frequency of the ring oscillator 122 in the frequency locking module 120.

[0069] The transconductance amplifier 160 compares the sampled voltage with a preset reference voltage and converts it into a control current. The preset reference voltage can be set according to actual needs and is not specifically limited here.

[0070] As a possible implementation, see Figure 2 , which is a schematic diagram of the structure of a fractional sigma-delta modulator 140 provided in an embodiment of the present disclosure.

[0071] like Figure 2 As shown in FIG. 1 , the fractional sigma-delta modulator 140 includes a sigma-delta modulation unit 141 and an accumulator 142 .

[0072] In a specific implementation, the input of the fractional sigma-delta modulator 140 is a control word signal, wherein the control word signal consists of an integer part and a fractional part. After the fractional part of the control word signal is added with a preset deviation signal, after passing through the accumulator 142, a fractional control signal for controlling the phase interpolation module 130 to perform phase interpolation is output, wherein the deviation signal is used to control the fractional part interval range of the control word signal.

[0073] As another possible implementation, see Figure 3, which is a schematic diagram of the structure of a phase interpolation module 130 provided in an embodiment of the present disclosure.

[0074] like Figure 3 As shown in , the phase interpolation module 130 includes: a timing controller 131 , a decoder 132 , a current digital-to-analog converter 133 and an interpolation capacitor 134 .

[0075] In a specific implementation, the decoder 132 converts the fractional control signal output by the fractional sigma-delta modulator 140 into a control signal of the current digital-to-analog converter 133 , wherein the control signal is used to control the output current of the current digital-to-analog converter 133 .

[0076] Furthermore, the current digital-to-analog converter 133 outputs current to charge the interpolation capacitor 134 , and the voltage change speed of the interpolation capacitor 134 is affected according to the magnitude of the output current, so as to achieve phase interpolation.

[0077] Here, due to the different current magnitudes of the current digital-to-analog converter 133, the voltage of the interpolation capacitor 134 changes at different speeds, thereby achieving phase interpolation.

[0078] After receiving the clock waveform signal output by the ring oscillator 122 in the frequency locking module 120 , the timing controller 131 resets the voltage value of the interpolation capacitor 134 according to the clock waveform signal. After the reset stops, the interpolation capacitor 134 starts to charge.

[0079] It should be noted that the integer control signal output by the fractional sigma-delta modulator 140 is input to the timing controller 131. The timing controller 131 also outputs a clock signal, which is transmitted to the frequency and phase detector 111 for use as a signal to be locked.

[0080] As another possible implementation, see Figure 4 , which is a schematic diagram of the structure of a sampling circuit 150 provided in an embodiment of the present disclosure.

[0081] like Figure 4 As shown in , the sampling circuit 150 includes a first delay unit 151 , a second delay unit 152 , a first inverter 153 , a second inverter 154 , a first transmission gate 155 , a second transmission gate 156 and a sampling capacitor 157 .

[0082] Specifically, the first delay unit 151 is connected to the first inverter 153; the second delay unit 152 is connected to the second inverter 154; the input end of the second delay unit 152 is connected between the first delay unit 151 and the first inverter 153; one end of the first transmission gate 155 is connected to the phase interpolation module 130, and the other end is connected to the second transmission gate 156; the second transmission gate 156 is connected to the transconductance amplifier 160; one end of the sampling capacitor 157 is connected between the first transmission gate 155 and the second transmission gate 156, and the other end of the sampling capacitor 157 is grounded; the control end of the first transmission gate 155 is connected to the first delay unit 151, and the inverse control end of the first transmission gate 155 is connected to the first inverter 153; the control end of the second transmission gate 156 is connected to the second delay unit 152, and the inverse control end of the second transmission gate 156 is connected to the second inverter 154.

[0083] In a specific implementation, a reference clock signal is input to the first delay unit 151, which outputs a sampling clock signal, which is then processed by the second delay unit 152 to output a holding clock signal; the first transmission gate 155 samples the target clock waveform signal input by the phase interpolation module 130 according to the sampling clock signal output by the first delay unit 151, and holds the sampled voltage in the sampling capacitor 157; after the sampling is completed, the holding clock signal is released, and the sampling voltage on the sampling capacitor 157 is output to the transconductance amplifier 160.

[0084] Here, the sampling clock signal is passed through the first inverter 153 to generate an inverted sampling clock signal; the holding clock signal is passed through the second inverter 154 to generate an inverted holding clock signal.

[0085] Among them, the sampling clock signal is transmitted to the control end of the first transmission gate 155, and the inverted sampling clock signal is transmitted to the inverted control end of the first transmission gate 155; the holding clock signal is transmitted to the control end of the second transmission gate 156, and the inverted holding clock signal is transmitted to the inverted control end of the second transmission gate 156.

[0086] The embodiment of the present disclosure provides a fractional frequency phase-locked loop based on phase interpolation and sampling, including: the input of the sampling circuit and the charge pump module is a reference clock signal, and the output end of the frequency locking module is used as the clock output of the phase-locked loop; the charge pump module is charged and discharged according to the reference clock signal, the frequency locking module is controlled to perform frequency locking, and the frequency locking module outputs a plurality of phases of clock waveform signals to the phase interpolation module; the phase interpolation module interpolates the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selects the target clock waveform signal from the clock waveform signal and sends it to the sampling circuit; the sampling circuit samples the rising edge of the target clock waveform signal, determines the sampling voltage, and outputs the sampling voltage to the transconductance amplifier, and the transconductance amplifier converts the sampling voltage into the control current of the frequency locking module to control the frequency of the frequency locking module. The low-frequency phase noise of the phase-locked loop can be effectively reduced, and the noise of sigma delta can be suppressed at the same time, so that the overall noise of the phase-locked loop is reduced, and at the same time, the area is relatively small.

[0087] Further, a control method of a fractional frequency phase-locked loop based on phase interpolation and sampling disclosed in an embodiment of the present disclosure is introduced in detail. The execution subject of the control method of the fractional frequency phase-locked loop based on phase interpolation and sampling provided in the embodiment of the present disclosure is generally a computer device with a certain computing capability, and the computer device includes, for example: a terminal device or a server or other processing device, and the terminal device can be a user equipment (User Equipment, UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. In some possible implementations, the control method of the fractional frequency phase-locked loop based on phase interpolation and sampling can be implemented by a processor calling a computer-readable instruction stored in a memory.

[0088] See also Figure 5 FIG. 1 is a flow chart of a control method of a fractional frequency phase-locked loop based on phase interpolation and sampling provided by an embodiment of the present disclosure, wherein the method is applied to the above Figure 1-Figure 4 Any fractional frequency phase-locked loop based on phase interpolation and sampling, the method comprises steps S501-S504, wherein:

[0089] S501 , inputting reference clock signals to the sampling circuit and the charge pump module respectively, and controlling the output end of the frequency locking module to output clock.

[0090] S502, controlling the charge pump module to charge and discharge according to the reference clock signal, controlling the frequency locking module to perform frequency locking, and having the frequency locking module output clock waveform signals of multiple phases to the phase interpolation module.

[0091] S503, control the phase interpolation module to interpolate the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and select a target clock waveform signal from the clock waveform signal to send to the sampling circuit.

[0092] S504, control the sampling circuit to sample the rising edge of the target clock waveform signal, determine the sampling voltage, and output the sampling voltage to the transconductance amplifier, and the transconductance amplifier converts the sampling voltage into a control current of the frequency locking module to control the frequency of the frequency locking module.

[0093] The control method of a fractional frequency phase-locked loop based on phase interpolation and sampling provided by the embodiment of the present disclosure is provided by inputting a reference clock signal to a sampling circuit and a charge pump module respectively, and controlling the output end of the frequency locking module to output a clock. The charge pump module is controlled to charge and discharge according to the reference clock signal, the frequency locking module is controlled to perform frequency locking, and the frequency locking module outputs a clock waveform signal of multiple phases to the phase interpolation module. The phase interpolation module is controlled to interpolate the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and the target clock waveform signal is selected from the clock waveform signal and sent to the sampling circuit. The sampling circuit is controlled to sample the rising edge of the target clock waveform signal, determine the sampling voltage, and output the sampling voltage to the transconductance amplifier, and the transconductance amplifier converts the sampling voltage into a control current of the frequency locking module to control the frequency of the frequency locking module. The low-frequency phase noise of the phase-locked loop can be effectively reduced, and the noise of sigma delta can be suppressed at the same time, so that the overall noise of the phase-locked loop is reduced, and at the same time, the area is relatively small.

[0094] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0095] For descriptions of the processing flow of each module in the method and the interaction flow between each module, reference can be made to the relevant descriptions in the above system embodiment, which will not be described in detail here.

[0096] Corresponds to Figure 5The control method of the fractional frequency phase-locked loop based on phase interpolation and sampling in the embodiment of the present disclosure further provides an electronic device 600, such as Figure 6 FIG. 6 is a schematic diagram of the structure of an electronic device 600 provided in an embodiment of the present disclosure, including:

[0097] Processor 61, memory 62, and bus 63; memory 62 is used to store execution instructions, including memory 621 and external memory 622; memory 621 here is also called internal memory, which is used to temporarily store the operation data in processor 61, and the data exchanged with external memory 622 such as hard disk. Processor 61 exchanges data with external memory 622 through memory 621. When the electronic device 600 is running, the processor 61 communicates with the memory 62 through bus 63, so that the processor 61 executes Figure 5 The steps of the control method of the fractional frequency phase-locked loop based on phase interpolation and sampling.

[0098] The embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the control method of the fractional frequency phase-locked loop based on phase interpolation and sampling described in the above method embodiment are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0099] The present disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, the steps of the control method of the fractional-frequency phase-locked loop based on phase interpolation and sampling described in the above method embodiment can be executed. For details, please refer to the above method embodiment, which will not be repeated here.

[0100] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0101] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0102] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0103] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0104] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0105] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A fractional frequency phase-locked loop based on phase interpolation and sampling, characterized in that: include: Charge pump module, frequency locking module, phase interpolation module, fractional sigma-delta modulator, sampling circuit and transconductance amplifier; The sampling circuit, the transconductance amplifier, the frequency locking module and the phase interpolation module are connected in sequence; the charge pump module is connected in parallel between the input end of the sampling circuit and the output end of the transconductance amplifier; the fractional sigma-delta modulator is connected to the phase interpolation module; The input of the sampling circuit and the charge pump module is a reference clock signal, and the output of the frequency locking module is used as the clock output of the phase-locked loop; The charge pump module performs charging and discharging according to the reference clock signal, controls the frequency locking module to perform frequency locking, and the frequency locking module outputs clock waveform signals of multiple phases to the phase interpolation module; The phase interpolation module interpolates the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selects a target clock waveform signal from the clock waveform signal and sends it to the sampling circuit; The sampling circuit samples the rising edge of the target clock waveform signal to determine a sampling voltage, and outputs the sampling voltage to the transconductance amplifier, which converts the sampling voltage into a control current of the frequency locking module to control the frequency of the frequency locking module; The fractional sigma-delta modulator comprises a sigma-delta modulation unit and an accumulator; The input of the fractional sigma-delta modulator is a control word signal, wherein the control word signal consists of an integer part and a fractional part; After adding a preset deviation signal to the decimal part of the control word signal, the decimal control signal for controlling the phase interpolation module to perform phase interpolation is output through the accumulator, wherein the deviation signal is used to control the decimal part interval range of the control word signal; The phase interpolation module includes: a timing controller, a decoder, a current digital-to-analog converter and an interpolation capacitor; The decoder converts the fractional control signal into a control signal for the current digital-to-analog converter, wherein the control signal is used to control the output current of the current digital-to-analog converter; The current digital-to-analog converter outputs current to charge the interpolation capacitor, and the voltage change speed of the interpolation capacitor is affected according to the size of the output current to achieve phase interpolation; After receiving the clock waveform signal output by the frequency locking module, the timing controller resets the voltage value of the interpolation capacitor according to the clock waveform signal, and after the reset stops, the interpolation capacitor starts to charge.

2. The fractional frequency phase-locked loop according to claim 1, characterized in that: The charge pump module includes a frequency detector and a charge pump; The frequency detector generates an upper switch control signal and a lower switch control signal according to the input reference clock signal; The charge pump performs charging and discharging according to the upper switch control signal and the lower switch control signal.

3. The fractional frequency phase-locked loop according to claim 1, characterized in that: The frequency locking module includes: a low-pass filter and a ring oscillator, wherein: The low-pass filter receives the charge and discharge signal of the charge pump module and converts the charge and discharge signal into a control voltage of the ring oscillator; The ring oscillator starts to oscillate after receiving the control voltage to achieve frequency locking.

4. The fractional frequency phase-locked loop according to claim 1, characterized in that: The sampling circuit includes a first delay unit, a second delay unit, a first inverter, a second inverter, a first transmission gate, a second transmission gate and a sampling capacitor; The first delay unit is connected to the first inverter; the second delay unit is connected to the second inverter; an input end of the second delay unit is connected between the first delay unit and the first inverter; One end of the first transmission gate is connected to the phase interpolation module, and the other end is connected to the second transmission gate; The second transmission gate is connected to the transconductance amplifier; One end of the sampling capacitor is connected between the first transmission gate and the second transmission gate, and the other end of the sampling capacitor is grounded; The control terminal of the first transmission gate is connected to the first delay unit, and the inverse control terminal of the first transmission gate is connected to the first inverter; A control terminal of the second transmission gate is connected to the second delay unit, and an inverting control terminal of the second transmission gate is connected to the second inverter.

5. The fractional frequency phase-locked loop according to claim 4, characterized in that: The reference clock signal is input to the first delay unit, the first delay unit outputs a sampling clock signal, and then the second delay unit processes and outputs a holding clock signal; The first transmission gate samples the target clock waveform signal according to the sampling clock signal, and keeps the sampled voltage in the sampling capacitor; After the sampling is completed, the holding clock signal is released, and the sampled voltage on the sampling capacitor is output to the transconductance amplifier.

6. A control method for a fractional frequency phase-locked loop based on phase interpolation and sampling, characterized in that: The method is applied to the fractional frequency phase-locked loop based on phase interpolation and sampling as claimed in any one of claims 1 to 5, wherein the fractional frequency phase-locked loop comprises: the charge pump module, the frequency locking module, the phase interpolation module, the fractional sigma-delta modulator, the sampling circuit and the transconductance amplifier, and the method comprises: Inputting reference clock signals to the sampling circuit and the charge pump module respectively, and controlling the output end of the frequency locking module to output clock; Controlling the charge pump module to charge and discharge according to the reference clock signal, controlling the frequency locking module to lock the frequency, and having the frequency locking module output clock waveform signals of multiple phases to the phase interpolation module; Controlling the phase interpolation module to interpolate the phase of the clock waveform signal according to the fractional signal output by the fractional sigma-delta modulator, and selecting a target clock waveform signal from the clock waveform signal to send to the sampling circuit; Controlling the sampling circuit to sample the rising edge of the target clock waveform signal, determine a sampling voltage, and output the sampling voltage to the transconductance amplifier, so that the transconductance amplifier converts the sampling voltage into a control current of the frequency locking module to control the frequency of the frequency locking module; The fractional sigma-delta modulator comprises a sigma-delta modulation unit and an accumulator; The input of the fractional sigma-delta modulator is a control word signal, wherein the control word signal consists of an integer part and a fractional part; After adding a preset deviation signal to the decimal part of the control word signal, the decimal control signal for controlling the phase interpolation module to perform phase interpolation is output through the accumulator, wherein the deviation signal is used to control the decimal part interval range of the control word signal; The phase interpolation module includes: a timing controller, a decoder, a current digital-to-analog converter and an interpolation capacitor; The decoder converts the fractional control signal into a control signal for the current digital-to-analog converter, wherein the control signal is used to control the output current of the current digital-to-analog converter; The current digital-to-analog converter outputs current to charge the interpolation capacitor, and the voltage change speed of the interpolation capacitor is affected according to the size of the output current to achieve phase interpolation; After receiving the clock waveform signal output by the frequency locking module, the timing controller resets the voltage value of the interpolation capacitor according to the clock waveform signal, and after the reset stops, the interpolation capacitor starts to charge.

7. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the control method of the fractional-frequency phase-locked loop based on phase interpolation and sampling are performed as described in claim 6.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, executes the steps of the control method of a fractional frequency phase-locked loop based on phase interpolation and sampling as claimed in claim 6.

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