Method for manufacturing semiconductor device and plasma processing method

Abstract

In a three-dimensional structure of a GAA type FET or the like having a stacked channel of a fine line shape or a sheet shape stacked in a direction perpendicular to a substrate, a method is provided in which, in a manufacturing process of a device having a structure in which a gate is insulated and separated from a silicon substrate, the germanium composition of a silicon germanium sacrificial layer for forming a stacked channel and a silicon germanium sacrificial layer required for insulating and separating a gate-substrate is not changed, and the manufacturing process is not complicated. Therefore, after etching a stacked film composed of a silicon channel (4B) and a silicon germanium sacrificial layer (3B), a protective insulating film (9) is formed on the side wall of the above-mentioned stacked film by film formation / etching, and the above-mentioned process is repeated a plurality of times using different protective film materials. Thereafter, the silicon sacrificial layer (4A) and the silicon germanium sacrificial layer (3A) remaining in the lower portion are removed by isotropic etching to form a region in which the above-mentioned insulating separation film is filled. By performing the formation of the stacked film from the above-mentioned protective insulating film to the etching removal of the sacrificial layer using a continuous process of the same device, the simplification of the process can be achieved.

Description

Technical Field

[0001] This disclosure relates to methods for manufacturing semiconductor devices and plasma processing methods. Background Technology

[0002] To continuously improve the functionality and performance of integrated circuit chips, high integration of transistors is necessary and indispensable. High integration of transistors can be primarily achieved through transistor miniaturization. To achieve transistor miniaturization while maintaining or improving transistor performance, many improvements have been made to transistor structure and the materials used to construct them. Examples of these improvements include: the introduction of strain into the source and drain regions of metal oxide semiconductor field-effect transistors (MOSFETs); the introduction of highly dielectric gate insulating films and metal elements; and the introduction of new structures such as finned types from planar types.

[0003] Fin-type FETs have the following structure: by covering the periphery of a three-dimensional finned channel with a gate, gate controllability is improved, and the short-channel effect (i.e., increased leakage current) caused by the reduction in gate length accompanying transistor miniaturization can be suppressed. Furthermore, it is envisioned that if miniaturization continues, the channel will become a filamentary (wire) or sheet-like stack, becoming a gate all-around FET (GAA) where the channel is covered by the gate. In GAA-type FETs, by completely covering the periphery of the filamentary or sheet-like channel (nanofilament channel or nanosheet channel) with the gate, gate controllability can be further improved compared to Fin-type FETs, and short-channel effects can be further suppressed.

[0004] However, in GAA-type FETs, since the gate covering the channel is also connected to the semiconductor substrate, a FET is simultaneously formed on the semiconductor substrate side. Because the FET formed on the semiconductor substrate side has a planar structure with weaker gate control compared to the GAA type, it becomes a factor that degrades the transistor's characteristics.

[0005] Non-Patent Document 1 mentions the problem of transistor characteristic degradation of planar FETs, i.e. parasitic FETs, formed on the side of the aforementioned semiconductor substrate, and points out the necessity of setting an insulating film directly below the gate to isolate the gate from the semiconductor substrate.

[0006] Patent Document 1 discloses a specific process for forming an insulating separation film between the gate and the semiconductor substrate. Specifically, in a stacked structure consisting of a silicon (Si) channel for forming nanowire or nanosheet channels and a silicon-germanium (SiGe) sacrificial layer, a second SiGe sacrificial layer with a larger germanium (Ge) content than the SiGe sacrificial layer is formed. Furthermore, in the stacked structure where sidewalls are exposed midway through the process, the second SiGe sacrificial layer is selectively etched away, and the removed areas are filled with an insulating film. This allows for insulating separation between the nanowire or nanosheet channels and the silicon substrate.

[0007] Patent Document 2 discloses a process in which the sidewalls of a Si / SiGe stacked film used to form nanowire channels or nanosheet channels are covered with a protective film, and the second SiGe sacrificial layer, which exists only in the lower part of the SiGe / Si stacked structure, is removed while only exposing its sidewalls. The removed area is then filled with an insulating film. During the etching of the second SiGe sacrificial layer, since the protective film covers the SiGe sacrificial layer in the SiGe / Si stacked film, it is not necessary for the Ge composition of the second SiGe sacrificial layer to be higher than that of the SiGe sacrificial layer in the SiGe / Si stacked film, thus mitigating concerns about strain relaxation caused by introducing a high-Ge-content SiGe layer.

[0008] Prior art literature

[0009] Patent documents

[0010] Patent Document 1: U.S. Patent Application Publication No. 2019 / 0393351

[0011] Patent Document 2: U.S. Patent Application Publication No. 2020 / 0105756

[0012] Non-patent literature

[0013] Non-patent literature 1: J. Zhang, et al., “Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications”, Proceedings of IEDM 2019, pp. 250-253. Summary of the Invention

[0014] The problem that the invention aims to solve

[0015] When forming the insulating separation film between the gate and the semiconductor substrate disclosed in Patent Document 1, it is necessary to ensure that the Ge composition of the second SiGe sacrificial layer formed below the Si / SiGe stack used to form nanowire channels or nanosheet channels is greater than the Ge composition of the first SiGe sacrificial layer in the upper Si / SiGe stack, so as to have etching selectivity. Typically, the Ge composition of the first SiGe sacrificial layer in the upper Si / SiGe stack is set to 15-25%, and the Ge composition of the second SiGe sacrificial layer is set to 40-50%. In this case, the strain caused by the difference in lattice constants of Si and SiGe becomes larger in the second SiGe sacrificial layer, raising concerns about the potential for defects caused by strain relaxation. In a SiGe layer with a Ge composition of 50%, the critical film thickness for strain relaxation is approximately 20 nm or less at the standard epitaxial growth temperature (550°C to 600°C) used to form the SiGe layer. Considering factors such as strain during the deposition of the upper Si / SiGe stack, it is presumed that the thickness of the second SiGe sacrificial layer needs to be designed to be extremely thin, to within 10 nm. This extremely thin thickness is achieved from the perspective of ensuring sufficient process margin and effective insulating separation between the gate and the semiconductor substrate. Furthermore, after etching the second SiGe sacrificial layer and the upper Si / SiGe stack along the pattern formed by the gate and gate spacers formed on their upper surfaces in the vertical direction, the second SiGe sacrificial layer is removed. That is, when the second SiGe sacrificial layer is etched away, the sidewalls of the first SiGe sacrificial layer in the upper Si / SiGe stack are also exposed, thus the upper first SiGe sacrificial layer is also exposed to etching during the etching of the second SiGe sacrificial layer. Although the Ge composition differs in the two films, since they are the same SiGe layer, it is difficult to achieve complete etching selectivity. Therefore, when the second SiGe sacrificial layer is etched, a certain amount of the first SiGe sacrificial layer in the upper Si / SiGe stack is inevitably etched away as well. Therefore, there are concerns that this could negatively impact subsequent processes, leading to increased transistor leakage current and other adverse effects.

[0016] In contrast, the GAA-type FET process disclosed in Patent Document 2 employs the following method: after vertically etching the Si / SiGe stacked film and the lower second SiGe sacrificial layer along the pattern, an insulating film is deposited on the sidewalls. This insulating film protects only the upper Si / SiGe stacked film portion, exposing only the second SiGe sacrificial layer, which is then removed. During the etching of the second SiGe sacrificial layer, since the first SiGe sacrificial layer of the upper Si / SiGe stacked film is protected by the insulating film, the etching selectivity issue that was a concern in Patent Document 1 is resolved. Furthermore, since the Ge composition of the second SiGe sacrificial layer can be made equal to that of the first SiGe sacrificial layer of the upper Si / SiGe stacked film, concerns about strain relaxation are also reduced. Therefore, the thickness of the second SiGe sacrificial layer can be set to be thick, ensuring sufficient process margin, and concerns about transistor malfunctions due to strain relaxation are also reduced. However, compared to the process disclosed in Patent Document 1, the GAA-type FET process disclosed in Patent Document 2 raises concerns about a significant increase in the number of process steps. In Patent Document 2, the method of protecting only the upper Si / SiGe stacked film with the aforementioned insulating film while exposing only the second SiGe sacrificial layer is performed through the following process: First, after etching the Si / SiGe stacked film and the lower second SiGe sacrificial layer along a pattern in the vertical direction, an insulating film of a fixed thickness isotropically deposited to protect the etched sidewalls. Next, a coating film such as a spin-coated carbon film is used to fill the trenches formed by the pattern, and then the carbon film is etched a certain amount in the vertical direction. Therefore, the etching amount is adjusted so that the upper end of the etched carbon film is located between the upper and lower ends of the second SiGe sacrificial layer. Then, a film of titanium nitride (TiN) or the like is deposited on the carbon film, the trenches formed by the pattern are filled again, and the base carbon film is removed. If the insulating film exposed at this time is etched away in the horizontal direction, the sidewalls of the second SiGe sacrificial layer are exposed. Subsequently, the second SiGe sacrificial layer is selectively etched away. Finally, by etching away the TiN film and the insulating film, a structure in which only the second SiGe sacrificial layer is removed is obtained. The above process adds nine film formation / etching processes to the process disclosed in Patent Document 1, resulting in a significant increase in the number of process steps. Furthermore, when etching a certain amount of carbon film in the vertical direction, it is difficult to adjust the etching amount so that the upper end of the etched carbon film is located between the upper and lower ends of the second SiGe sacrificial layer whose sidewalls are covered by the insulating film, since there is no method to directly evaluate the relative position of the SiGe sacrificial layer and the upper end of the carbon film.

[0017] This disclosure provides a plasma processing method that, in the manufacturing process of a GAA-type FET in which the gate and semiconductor substrate are insulated and separated, can be continuously performed by the same apparatus: a process of patterning a Si / SiGe laminate and a second SiGe sacrificial layer formed thereunder, protecting its sidewalls with a laminate of insulating film, and etching away only the second SiGe sacrificial layer; and a process from the patterning process until the removal of the second SiGe sacrificial layer.

[0018] Methods for solving problems

[0019] The representative summary of this disclosure is briefly described below.

[0020] One embodiment of this disclosure is a method for manufacturing a semiconductor device or a plasma processing method, comprising: a first step of depositing a protective insulating film on a portion of a vertically etched sidewall of a semiconductor laminate; a second step of anisotropically etching the protective insulating film in a vertical direction to expose the surface of the semiconductor laminate; a third step of repeatedly performing the first and second steps using an insulating film material different from the protective insulating film to form a laminate of the protective insulating film on the sidewall; and a fourth step of isotropically etching away the semiconductor laminate present in the lower part of the protective insulating film.

[0021] Invention Effects

[0022] According to one embodiment of the present disclosure, in the manufacturing process of three-dimensional structured devices such as GAA-type FETs, in the process of suppressing the formation of planar parasitic FETs formed on the silicon substrate side by isolating the gate from the silicon substrate, the generation of defects can be suppressed, and by means of the device characteristics that allow for continuous processes of multiple steps to be performed in the same device, the increase in the number of process steps can be significantly suppressed.

[0023] Other topics and novel features will be identified from the description in this specification and the accompanying drawings. Attached Figure Description

[0024] Figure 1A This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0025] Figure 1B This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0026] Figure 1C This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0027] Figure 1DThis is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0028] Figure 1E This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0029] Figure 1F This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0030] Figure 1G This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0031] Figure 1H This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0032] Figure 1I This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0033] Figure 1J This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0034] Figure 1K This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0035] Figure 1L This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0036] Figure 1M This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0037] Figure 1N This is a top view showing the manufacturing process of the GAA-type FET of Embodiment 1, in which the gate is insulated from the semiconductor substrate.

[0038] Figure 2A This is an enlarged cross-sectional view showing the process of forming an insulating separation film between the gate and the semiconductor substrate in Example 1.

[0039] Figure 2B This is an enlarged cross-sectional view showing the process of forming an insulating separation film between the gate and the semiconductor substrate in Example 1.

[0040] Figure 2C This is an enlarged cross-sectional view showing the process of forming an insulating separation film between the gate and the semiconductor substrate in Example 1.

[0041] Figure 2D This is an enlarged cross-sectional view showing the process of forming an insulating separation film between the gate and the semiconductor substrate in Example 1.

[0042] Figure 3A This is a cross-sectional view of the device separation region in the manufacturing process of the GAA-type FET of Embodiment 1, which involves insulatingly separating the gate from the semiconductor substrate.

[0043] Figure 3B This is a cross-sectional view of the device separation region in the manufacturing process of the GAA-type FET of Embodiment 1, which involves insulatingly separating the gate from the semiconductor substrate.

[0044] Figure 3C This is a cross-sectional view of the device separation region in the manufacturing process of the GAA-type FET of Embodiment 1, which involves insulatingly separating the gate from the semiconductor substrate.

[0045] Figure 3D This is a cross-sectional view of the device separation region in the manufacturing process of the GAA-type FET of Embodiment 1, which involves insulatingly separating the gate from the semiconductor substrate.

[0046] Figure 3E This is a cross-sectional view of the device separation region in the manufacturing process of the GAA-type FET of Embodiment 1, which involves insulatingly separating the gate from the semiconductor substrate.

[0047] Figure 3F This is a cross-sectional view of the device separation region in the manufacturing process of the GAA-type FET of Embodiment 1, which involves insulatingly separating the gate from the semiconductor substrate.

[0048] Figure 4 This is a flowchart illustrating the manufacturing process of a GAA-type FET in Embodiment 1, which involves isolating the gate from the semiconductor substrate.

[0049] Figure 5 This is a diagram showing an example of the structure of a plasma processing device.

[0050] Figure 6A This is a top view showing the manufacturing process of the GAA-type FET in Embodiment 2, which involves isolating the gate from the semiconductor substrate.

[0051] Figure 6B This is a top view showing the manufacturing process of the GAA-type FET in Embodiment 2, which involves isolating the gate from the semiconductor substrate.

[0052] Figure 6CThis is a top view showing the manufacturing process of the GAA-type FET in Embodiment 2, which involves isolating the gate from the semiconductor substrate.

[0053] Figure 6D This is a top view showing the manufacturing process of the GAA-type FET in Embodiment 2, which involves isolating the gate from the semiconductor substrate.

[0054] Figure 7A This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0055] Figure 7B This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0056] Figure 7C This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0057] Figure 7D This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0058] Figure 7E This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0059] Figure 7F This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0060] Figure 7G This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0061] Figure 7H This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0062] Figure 7I This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0063] Figure 7J This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0064] Figure 7K This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0065] Figure 8 This is a flowchart illustrating the manufacturing process of the GAA-type FET in Embodiment 3, which involves isolating the gate from the semiconductor substrate.

[0066] Figure 9A This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0067] Figure 9B This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0068] Figure 9C This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0069] Figure 9D This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0070] Figure 9E This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0071] Figure 9F This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0072] Figure 9G This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0073] Figure 9H This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0074] Figure 9I This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate.

[0075] Figure 9J This is a cross-sectional view showing the manufacturing process of the GAA-type FET in Embodiment 4, which involves isolating the gate from the semiconductor substrate. Detailed Implementation

[0076] The embodiments of this disclosure will now be described based on the accompanying drawings. Furthermore, this disclosure is not limited to the embodiments described below, and various modifications can be made within the scope of its technical concept. In all the drawings used to illustrate the embodiments, the same reference numerals are used for components having the same function, and sometimes repeated descriptions are omitted. Moreover, many changes can be made to the content disclosed in this embodiment, such as changing the materials, the combination of manufacturing processes, etc. Furthermore, the drawings are not necessarily drawn to scale precisely; they are depicted schematically to emphasize important parts for logical clarity. Additionally, the drawings may sometimes show schematic representations compared to the actual method in order to make the explanation clearer, but these are only examples and are not intended to limit the interpretation of this disclosure.

[0077]

Example 1

[0078] In Example 1, a series of steps (also referred to as the step of forming a gate-semiconductor substrate insulating separation film 11, or the gate-semiconductor substrate insulating separation film formation step) for insulating separation between the gate and the semiconductor substrate in the manufacturing process (semiconductor device manufacturing method or plasma processing method) of a GAA-type FET (Gate All Around type Field Effect Transistor) as a semiconductor device, and the process of stacking multiple sidewall protective films made of different materials in the above steps are described in detail. First, using Figures 1A to 1N , Figures 2A to 2D , Figures 3A to 3F , Figure 4 The above process will be explained below. The semiconductor device manufacturing method or plasma processing method described in the embodiments is a method for forming a GAA-type FET, wherein the GAA-type FET has a stacked channel in the gate formation region, in which fine wire-shaped or sheet-shaped channels are stacked in a direction perpendicular to the substrate, and the gate is insulated and separated from the semiconductor substrate by an insulating film.

[0079] Figures 1A to 1N This is a top view showing the process from the step of isolating the gate from the semiconductor substrate to the completion of the FET structure in the manufacturing process of a GAA-type FET. Figures 1A to 1K This refers to a series of processes performed in relation to this embodiment, starting from the etching of the Si / SiGe (silicon / silicon germanium) stacked film until the removal of the second SiGe sacrificial layer and the removal of the sidewall protective insulating film. Figures 1L to 1M This refers to the process of filling an insulating film (filling the insulating film) in the region of the removed second SiGe sacrificial layer. This is used for insulating separation between the gate and the semiconductor substrate. Figure 1N This indicates a GAA-type FET structure that includes the aforementioned buried insulating film (between the gate and the substrate). Figures 2A to 2D Indicates in Figures 1D to 1GThe process shown includes an enlarged cross-sectional view of the area from the bottom of the Si / SiGe laminate up to the Si substrate. Figures 3A to 3F Indicates and Figures 1C to 1K The component separation region outside the FET channel region in the corresponding process, i.e., along Figure 1A The diagram shows the gate cross-section in the cross-section of the AA' line. Figure 4 express Figures 1A to 1K The flowchart shown illustrates a series of manufacturing processes.

[0080] exist Figure 1A In this process, a multilayer film is formed on a single-crystal Si substrate (semiconductor substrate) 1 by alternately stacking multiple single-crystal SiGe layers (first semiconductor layer) 3 and single-crystal Si layers (second semiconductor layer) 4. The multilayer film of SiGe layers 3 and Si layers 4 has a second SiGe sacrificial layer 3A at its bottom, and a Si sacrificial layer 4A on the second SiGe sacrificial layer 3A. A first SiGe sacrificial layer 3B and a Si channel 4B are then alternately and repeatedly stacked on the Si sacrificial layer 4A. The multilayer film of SiGe layers 3 and Si layers 4 is formed, for example, by epitaxial growth using a method such as chemical vapor deposition (CVD). The Ge composition in the SiGe layer 3 is designed to be identical in the second SiGe sacrificial layer 3A and the first SiGe sacrificial layer 3B. The Ge composition can be, for example, 15% to 40%. The second SiGe sacrificial layer 3A and each of the first SiGe sacrificial layers 3B are deposited to match the crystal lattice of the Si substrate 1. Each SiGe layer contains strain energy due to the difference in lattice constants between SiGe and Si. The film thickness of the second SiGe sacrificial layer 3A, the number of repetitions of the first SiGe sacrificial layers 3B and the Si channel 4B, and their respective film thicknesses need to be adjusted, along with the characteristics required for the FET, according to the condition that the film thickness does not exceed the critical film thickness at which the strain energy contained in the SiGe layers causes defects in the SiGe layer 3. Preferred film thicknesses, for example, are approximately 10–50 nm for the second SiGe sacrificial layer 3A, approximately 8–20 nm for the first SiGe sacrificial layer 3B, and approximately 5–10 nm for the Si channel 4B. The number of repetitions of the first SiGe sacrificial layer 3B and the Si channel 4B can, for example, be set to 3–6 layers respectively. Furthermore, the film thickness of the Si sacrificial layer 4A can, for example, be designed to be 5–20 nm. For example, hydrogen-diluted raw materials such as monosilane (SiH4), diethylsilane (Si2H6), and germanium hydride (GeH4) can be used for epitaxial growth based on CVD. Additionally, in Figure 1A In this case, the top layer can be set as Si channel 4B, or the first SiGe sacrificial layer 3B can be set as the top layer.

[0081] The SiGe layer 3 and Si layer 4 are laminated into a linear pattern when viewed from above. The width of this pattern can be adjusted to approximately 5–15 nm when forming fine-wire nanowire channels, and to approximately 10–100 nm when forming sheet-like nanosheet channels. Nanowire channels offer high gate-based controllability due to their short perimeter, while requiring a small drive current. On the other hand, while the gate-based controllability of nanosheet channels is slightly worse than that of nanowire channels, they can achieve a large drive current.

[0082] The channel shape is determined by the application of the necessary device. Linear patterns become periodic or based on a specific pattern. For example, when using a laser with argon fluoride (ArF) as the light source, self-aligned double patterning (SADP) can be used if the pattern period is, for example, 40 nm or more and 80 nm or less. Furthermore, self-aligned quadruple patterning (SAQP) can be used if the pattern period is, for example, 20 nm or more and 40 nm or less. Additionally, when performing exposure to extreme ultraviolet (EUV) light at a wavelength of 13.5 nm, single patterning can be used if the pattern period is, for example, up to 40 nm. SADP can be used if the pattern period is, for example, 20 nm or more and 40 nm or less.

[0083] After forming the laminated film pattern of SiGe layer 3 and Si layer 4, a device separation (STI) insulating film (referred to as STI insulating film) 2 is deposited in the trench of a portion of the patterned Si substrate 1 to form the device separation region. The STI insulating film 2 is then etched back to obtain... Figure 1A The structure of the insulating film 2 is shown. The STI insulating film 2 is formed, for example, using a CVD method. The material of the STI insulating film 2 can be silicon oxide (SiO2), silicon nitride oxide (SiON), silicon carbon oxide (SiCO), etc. The upper surface of the STI insulating film 2 after etching can be set in any location. As the most preferred method, the etching amount can be adjusted to be located between the upper and lower ends of the second SiGe sacrificial layer 3A.

[0084] On the laminated film pattern of SiGe layer 3 and Si layer 4, a dummy gate insulating film 5 composed of SiO2 or an insulating film based thereon, and a dummy gate 6 composed of amorphous Si or polycrystalline Si are formed, and then an insulating film hard mask 7 of SiO2, silicon nitride (Si3N4), SiON, etc., is formed. The dummy gate insulating film 5 can be formed, for example, by CVD, or by oxidizing SiGe layer 3 and Si layer 4 by thermal oxidation or plasma oxidation. The thickness of the dummy gate insulating film 5 is preferably set to the range of 1 to 3 nm. The dummy gate 6 and hard mask 7 can be formed, for example, by film formation methods such as CVD. The thickness of the dummy gate 6 and hard mask 7 is preferably adjusted to the range of 20 to 200 nm. The dummy gate insulating film 5, dummy gate 6, and hard mask 7 are patterned in a direction perpendicular to the pattern of the laminated film of SiGe layer 3 and Si layer 4. The aforementioned pattern is formed using techniques such as SADP and single exposure, corresponding to the gate spacing. For example, the gate spacing is set to 40–70 nm, and the width (i.e., gate length) of the dummy gate 6 is set to the range of 10–30 nm. The hard mask 7, the dummy gate 6, and the dummy gate insulating film 5 are etched along the pattern. Here, the etching of the hard mask 7 and the dummy gate 6 can, for example, use vertical etching based on dry etching. The etching of the dummy gate insulating film 5 can, for example, use isotropic etching utilizing either dry or wet etching. Furthermore, the etching of the dummy gate insulating film 5 may not be performed in a specific pattern. Figure 1A The process shown is carried out in this step, but in... Figure 1B The etching of the spacers is performed after the etching of the hard mask 7, the dummy gate 6, and the dummy gate insulating film 5. Then, the gate sidewall spacers (gate sidewall spacer film) 8 are deposited, for example by CVD, to obtain... Figure 1A The structure is shown. The gate sidewall spacer 8 can be, for example, a SiON film, a silicon carbon nitride oxide film (SiOCN), or a SiCO film, which are low relative permittivity films. The horizontal film thickness of the gate sidewall spacer 8 can be adjusted, for example, in the range of 5 to 15 nm.

[0085] from Figure 1A Starting from the configuration shown, anisotropic etching is performed on the gate sidewall spacer 8 in the vertical direction to obtain... Figure 1BThe structure is shown. Anisotropic etching of the gate sidewall spacer 8 can be performed, for example, using a mixture of tetrafluoromethane (CF4) and octafluorocyclobutane (C4F8) with added nitrogen (N2) gas when using a SiCO film for the gate sidewall spacer 8. When using a SiOCN film for the gate sidewall spacer 8, anisotropic etching of the gate sidewall spacer 8 can be performed, for example, using a mixture of fluoromethane (CH3F) and oxygen (O2) and helium (He) gas. The above etching is performed under conditions of selective etching to achieve a pattern for the stacked film pattern of SiGe layer 3 and Si layer 4. Figure 1A Without etching the dummy gate insulating film 5, the etching of the gate sidewall spacer 8 is performed under etching conditions where the dummy gate insulating film 5 is used as an obstacle. The etching depth is adjusted after etching so that the upper end of the gate sidewall spacer 8 is located between the upper and lower ends of the hard mask 7. That is, after this etching, the sidewalls of the dummy gate 6 are adjusted to be completely covered by the gate sidewall spacer 8. Figure 1B The process shown is equivalent to Figure 4 The process flow diagram is 101.

[0086] exist Figure 1C In this process, anisotropic etching is performed in the perpendicular direction along the sidewall of the gate sidewall spacer 8 to form the stacked film pattern of SiGe layer 3 and Si layer 4. The etching time is adjusted to etch the stacked film of the first SiGe sacrificial layer 3B and Si channel 4B, and the Si sacrificial layer 4A, preferably ending the etching with the second SiGe sacrificial layer 3A exposed. Through over-etching, the etching depth of the second SiGe sacrificial layer 3A can be adjusted, for example, to a range of 0–40 nm. In this etching, for example, chlorine (Cl2), CF4, or gases based thereon, or mixtures of these (Cl2 and CF4), or gases containing nitrogen trifluoride (NF3) and O2 in these (Cl2 and CF4) can be used. The etching of the stacked film of SiGe layer 3 and Si layer 4 in this process is... Figure 4 The process flow diagram is equivalent to 102, which can be carried out. Figure 1B After etching 101 of the gate sidewall spacer 8 shown, the etching is performed continuously within the chamber of the same device. Furthermore, in Figure 3A The image shows the device separation area outside the channel region of the FET after this process. Figure 1A The gate cross section at the AA' line.

[0087] Subsequently, a first protective insulating film 9 was deposited using a film deposition technique based on ALD (Atomic Layer Deposition) to obtain... Figure 1DThe structure is shown. A protective insulating film 9 is deposited on the upper surface and sidewalls of the hard mask 7 and the gate sidewall spacer 8, the sidewalls of the laminated film composed of the exposed first SiGe sacrificial layer 3B and Si channel 4B, the sidewalls of the Si sacrificial layer 4A, the upper surface of the second SiGe sacrificial layer 3A, and the STI insulating film 2. The material of the protective insulating film 9 is preferably a nitrogen-containing insulating film, considering the etch selectivity between the laminated film composed of SiGe layer 3 and Si layer 4 and the surrounding STI insulating film 2. It can be a film containing silicon and nitrogen, such as a Si3N4 film or a SiON film based thereon. The thickness of the protective insulating film 9 is controlled, for example, to approximately 2-3 nm. The ALD method has the advantage of being able to deposit thin films with good control even for complex shapes with many bumps and depressions. When the protective insulating film 9 is a Si3N4 film formed by ALD, the raw material for Si can be, for example, bis(tert-butylamino)silane (BTBAS), bis(diethylamino)silane (BDEAS), or dichlorosilane (SiH2Cl2), and the raw material for nitrogen can be N2 gas, a mixture of N2 gas and hydrogen (H2) gas, or ammonia (NH3) gas, or other nitrogen-containing gases. Alternatively, the protective insulating film 9 can be a film that does not contain nitrogen, such as SiO2, and can be formed by CVD or similar methods. In this process, the raw material containing... Figure 1D A magnified view of the film from the bottom of the first SiGe sacrificial layer 3B and Si channel 4B to the second SiGe sacrificial layer 3A. Figure 2A As shown, the laminated film consisting of the first SiGe sacrificial layer 3B and the Si channel 4B, and the sidewalls of the Si sacrificial layer 4A mostly have a slightly tapered shape that slopes vertically at the bottom of the pattern. This reflects... Figure 1C The dry etching characteristic shown in the pattern formation arises from the ease with which reaction products or raw material gases can deposit on the sidewalls during etching. The taper angle is controlled by the ion energy, etching gas, and etching chamber pressure during etching, but adjustments are also made considering potential damage to the second SiGe sacrificial layer 3A on the substrate. The angle between the aforementioned sidewall and the upper surface of the second SiGe sacrificial layer 3A ( Figure 2A θ1) is, for example, in the range of 80 to 90 degrees. Figure 1CRegarding the width of the trench pattern formed in the stacked film consisting of the first SiGe sacrificial layer 3B and the Si channel 4B and the Si sacrificial layer 4A, for example, if the gate pitch is set to 56 nm, the gate length is set to 20 nm, and the horizontal film thickness of the gate sidewall spacer 8 is set to 8 nm, then it becomes 20 nm. The width of the trench pattern is envisioned to be further reduced along with the miniaturization of the transistor, and in the future, for example, it is expected to be around 10 to 15 nm. In this case, considering the aforementioned taper angle, the width of the trench pattern at the bottom of the trench is envisioned to be, for example, less than 10 nm. If a protective insulating film 9 is formed using such a narrow pattern, then the vertical film thickness at the bottom of the trench is envisioned to be ( Figure 2A The t2) will be thicker than the horizontal film in the sidewall ( Figure 2A The thickness of the protective insulating film 9 on the sidewall of the pattern is thicker. If the horizontal thickness t1 of the protective insulating film 9 on the sidewall of the pattern is set to 2 to 3 nm, then the vertical thickness t2 of the film at the bottom of the groove is expected to be 3 to 6 nm. Figure 1D The process shown is equivalent to Figure 4 The process flow diagram at 103 can be continued... Figure 1C The etching 102 of the laminated film consisting of the first SiGe sacrificial layer 3B and the Si channel 4B, as well as the Si sacrificial layer 4A, is performed continuously in the chamber of the same device. Furthermore, Figure 3B This shows the device separation area outside the channel region of the FET after this process. Figure 1A The gate cross section in the AA' line.

[0088] exist Figure 1E In the illustrated process, the protective insulating film 9 is etched in the vertical direction. This etching is performed under selective etching conditions targeting the hard mask 7, the gate sidewall spacer 8, the second SiGe sacrificial layer 3A, and the STI insulating film 2. For example, if the protective insulating film 9 is a Si3N4 film, the etching gas can be a gas containing Cl2 or similar substances added to a mixture of halogen-based gases such as CF4 or C4F8 and O2, or a gas based thereon. Through this etching, the upper surface of the second SiGe sacrificial layer 3A is exposed. Figure 2B This is an enlarged view showing the process described above, including the layered film from the bottom of the first SiGe sacrificial layer 3B and the Si channel 4B to the second SiGe sacrificial layer 3A. In this etching, the etching time is determined considering the vertical thickness of the protective insulating film 9 at the bottom of the trench. Since the vertical thickness of the protective insulating film 9 at the bottom of the trench is greater than the horizontal thickness of the protective insulating film 9 on the sidewalls of the trench, a portion of the protective insulating film 9 on the sidewalls is also etched away at the bottom of the trench after etching, such as... Figure 2B As shown, it is possible that a portion of the Si sacrificial layer 4A and the first SiGe sacrificial layer 3B may be exposed. In this case, the lower part of the protective insulating film 9 is as follows... Figure 2BAs shown, the film has an eaves structure, and the angle θ2 between the sidewalls of the Si sacrificial layer 4A and the laminated film composed of the first SiGe sacrificial layer 3B and the Si channel 4B and the eaves is an acute angle of less than 90 degrees. Figure 3C This shows the device separation area outside the channel region of the FET after this process. Figure 1A The gate cross-section in the AA' line. The STI insulating film 2 is also etched slightly during the etching of the protective insulating film 9 due to over-etching. Figure 1E The process shown is equivalent to Figure 4 The process flow diagram, step 104, can continue... Figure 1D The film-forming process 103 of the protective insulating film 9 shown is carried out continuously in the chamber of the same device.

[0089] Following the above steps, using the ALD method, a second protective insulating film 10 is deposited on the first protective insulating film 9 to obtain... Figure 1F The structure shown is a laminated protective insulating film formed by a first protective insulating film 9 and a second protective insulating film 10. In the laminated protective insulating film, the lower layer is the first protective insulating film 9, and the upper layer is the second protective insulating film 10. The insulating film materials of the first protective insulating film 9 and the second protective insulating film 10 are set to different insulating film materials. The second protective insulating film 10 is deposited on the hard mask 7, the gate sidewall spacer 8, the upper surface and sidewall of the protective insulating film 9, the upper surface of the second SiGe sacrificial layer 3A, and the STI insulating film 2. An enlarged view including the laminated film after the deposition of the second protective insulating film 10, from the lower part of the first SiGe sacrificial layer 3B and the Si channel 4B to the second SiGe sacrificial layer 3A, is shown below. Figure 2C As shown. In Figure 2C In the middle, the horizontal thickness of the second protective insulating film 10 ( Figure 2C The thickness t3 can be set to be the same as the horizontal thickness t1 of the first protective insulating film 9 (t3 = t1), or it can be set to be thinner (t3 < t1). When the film thickness t1 is, for example, 2-3 nm, the film thickness t3 is preferably, for example, 1-3 nm. Figure 2BIn the process shown, with the lower part of the Si sacrificial layer 4A and the sidewall of the laminated film composed of the first SiGe sacrificial layer 3B and Si channel 4B exposed, the second protective insulating film 10 is also deposited on the eaves formed at the lower part of the first protective insulating film 9, and on the exposed Si sacrificial layer 4A and the sidewall of the laminated film composed of the first SiGe sacrificial layer 3B and Si channel 4B, through the raw material gas passing through the flow path a1. Furthermore, since the second protective insulating film 10 is deposited isotropically, the film formation at the lower part of the eaves of the first protective insulating film 9 overlaps with the film formation from the lower part of the eaves in the vertical direction and from the sidewall of the laminated film composed of the Si sacrificial layer 4A and the first SiGe sacrificial layer 3B and Si channel 4B in the horizontal direction, resulting in a film thickness of the second protective insulating film 10 ( Figure 2C The thickness t4) is thicker than the horizontal thickness t3 of the second protective insulating film 10 on the sidewall of the first protective insulating film 9. Furthermore, by setting the film thickness t3 to be thinner than the film thickness t1, the vertical thickness (t4) of the second protective insulating film 10 on the second SiGe sacrificial layer 3A is also thinner. Figure 2C The t5 value is equal to or smaller than the sum of the film thicknesses t3 and t1 (t3+t1=t5), or smaller than the sum of the film thicknesses t3 and t1 (t3+t1>t5). The second protective insulating film 10 is a film that can be formed isotropically with good control even for complex shapes with finer irregularities. The second protective insulating film 10 is a film containing aluminum and oxygen elements, such as an alumina (Al2O3) film or an aluminum oxynitride (AlON) film based thereon. In the case of forming an Al2O3 film, the aluminum (Al) raw material can be, for example, trimethylaluminum (TMA: Al(CH3)3), and the oxygen raw material can be vaporized water (H2O). The precursor composed of Al(CH3)3 has high reactivity with the hydroxyl groups (OH groups) formed on the surface due to the supply of H2O, thus enabling the formation of an Al2O3 film with good coverage even on uneven surfaces. Therefore, Al2O3 films with narrow openings Figure 2C The patterned interior is also isotropically formed. Furthermore, the second protective insulating film 10 can be an oxide film or a nitride film that does not use Al, and can be formed using methods such as CVD. Figure 1F as well as Figure 2C The process shown is equivalent to Figure 4 The process flow diagram, step 105, can continue... Figure 1E as well as Figure 2B The etching process 104 of the first protective insulating film 9 shown is performed continuously in the chamber of the same device. Furthermore, Figure 3D This shows the device separation area outside the channel region of the FET after this process. Figure 1A The gate cross section in the AA' line.

[0090] Next, in Figure 1G In the illustrated process, the second protective insulating film 10 is etched in the vertical direction. This etching is performed under selective etching conditions targeting the first protective insulating film 9, the hard mask 7, the gate sidewall spacer 8, the second SiGe sacrificial layer 3A, and the STI insulating film 2. For example, if the second protective insulating film 10 is an Al2O3 film, the etching gas can be, for example, boron trichloride (BCl3), a mixture of BCl3 and Cl2, or a gas formed by mixing argon (Ar), N2, and O2, or a gas based on these. Through this etching, the upper surface of the second SiGe sacrificial layer 3A is exposed. Figure 2D This is an enlarged view showing the process described above, from the bottom of the stacked film containing the first SiGe sacrificial layer 3B and the Si channel 4B to the second SiGe sacrificial layer 3A. During this etching process, even when ions generated from the etching gas are incident on the substrate 1 in a direction inclined from the vertical, the angle is changed by reflection from the sidewalls of the first protective insulating film 9. Figure 2D (a2). For example Figure 2C As shown, after the second protective insulating film 10 is formed, the opening pattern formed on the Si sacrificial layer 4A, the first SiGe sacrificial layer 3B, and the Si channel 4B results in a minimum opening width near the eaves of the first protective insulating film 9. Therefore, the etching gas ions reflected from the sidewalls of the aforementioned first protective insulating film 9 are almost completely consumed in the vertical etching of the second protective insulating film 10, and the second protective insulating film 10 deposited on the pattern sidewalls below the eaves is not etched. Through the above process, the upper part of the second SiGe sacrificial layer 3A can be opened while maintaining the sidewalls protecting the opening pattern formed on the Si sacrificial layer 4A, the first SiGe sacrificial layer 3B, and the Si channel 4B. Furthermore, Figure 3E This shows the device separation area outside the channel region of the FET after this process. Figure 1A The gate cross-section in the AA' line. Through over-etching during the etching of the second protective insulating film 10, the STI insulating film 2 is also etched at one point. Figure 1G as well as Figure 2D The process shown is equivalent to Figure 4 The process flow diagram, step 106, can continue... Figure 1F as well as Figure 2C The film-forming process 105 of the second protective insulating film 10 shown is performed continuously in the chamber of the same apparatus. Furthermore, Figure 4The cyclic processes shown in steps 103-104 and 105-106 (gas and film-forming conditions can also be changed) are not limited to two cycles, but can be repeated multiple times. That is, when considering the combination of the film-forming process (103, 105) as the first step and the etching process (104, 106) as the second step as one cycle, in... Figure 4 In this context, it means that the third process consists of two cycles combining the film-forming and etching processes (the first cycle being processes 103 and 104, and the second cycle being processes 105 and 106). In processes 103 and 104 of the first cycle, and processes 105 and 106 of the second cycle, the gas and film-forming conditions can be changed. Furthermore, the number of cycles for the film-forming (103, 105) and etching (104, 106) processes is not limited to two cycles; they can be repeated multiple times to form multiple cycles.

[0091] exist Figure 1H In the illustrated process (process 4), the second SiGe sacrificial layer 3A is etched in the vertical direction. This etching is performed under selective etching conditions targeting the second protective insulating film 10, the first protective insulating film 9, the hard mask 7, the gate sidewall spacer 8, the STI insulating film 2, and the Si substrate 1. The etching gas can be, for example, a halogen-containing gas such as HBr, CF2Cl2, trifluorobromomethane (CF3Br), or a gas containing 1-5% CF4 in HBr, or a mixture thereof, or a gas obtained by adding rare gases such as O2 or Ar, He, or inert gases such as N2, or a mixture thereof. Conditions such as the gas flow rate ratio, ion energy during etching, combination of etching gases, and pressure within the etching chamber can be adjusted to maintain the verticality of the etching of the second SiGe sacrificial layer 3A and to achieve an etching rate approximately 1 to 10 times that of the Si substrate 1. Figure 1H The process shown is equivalent to Figure 4 The process flow diagram, step 107, can continue... Figure 1G as well as Figure 2D The etching process 106 of the second protective insulating film 10 shown is carried out continuously in the chamber of the same device.

[0092] Next, in the process shown in FIG1T (process 4), the second SiGe sacrificial layer 3A is isotropically etched away. This etching is performed under selective etching conditions targeting the second protective insulating film 10, the first protective insulating film 9, the hard mask 7, the gate sidewall spacer 8, the STI insulating film 2, and the Si substrate 1 and the Si sacrificial layer 4A. The etching gas can be, for example, a fluorine-containing gas such as sulfur hexafluoride (SF6), CF4, or NF3, or a mixture thereof, or a gas obtained by adding rare gases such as O2 or Ar, He, or inert gases such as N2, or a mixture thereof. Conditions such as the gas flow rate ratio, ion energy during etching, combination of etching gases, and pressure within the etching chamber can be adjusted to ensure isotropic etching of the second SiGe sacrificial layer 3A, and the etching rate is, for example, approximately 1 to 200 times the etching rate of the Si substrate 1. Figure 1I The process shown is equivalent to Figure 4 The process flow diagram for step 108 can be continued... Figure 1H The vertical etching process 107 of the second SiGe sacrificial layer 3A shown is performed continuously in the chamber of the same apparatus. Furthermore, Figure 1I The step shown can be omitted. Figure 1H The vertical etching process 107 of the second SiGe sacrificial layer 3A shown below, followed by Figure 1G The etching 106 of the second protective insulating film 10 shown is performed continuously in the chamber of the same device.

[0093] exist Figure 1J In the illustrated process (step 4), the Si sacrificial layer 4A is isotropically etched away. This etching is performed under selective etching conditions targeting the second protective insulating film 10, the first protective insulating film 9, the hard mask 7, the gate sidewall spacer 8, the STI insulating film 2, and the first SiGe sacrificial layer 3B. The etching gas can be, for example, a fluorine-containing gas such as SF6, CF4, or NF3, or a mixture thereof with added H2, or gases such as O2 and N2, or a mixture thereof. Conditions such as the gas flow rate ratio, ion energy during etching, combination of etching gases, and pressure within the etching chamber can be adjusted to ensure isotropic etching of the Si sacrificial layer 4A, and the etching rate is, for example, approximately 1 to 100 times the etching rate of the first SiGe sacrificial layer 3B. Figure 1J The process shown is equivalent to Figure 4 The process flow diagram, step 109, can be continued... Figure 1I The etching removal process 108 of the second SiGe sacrificial layer 3A shown is performed continuously in the chamber of the same apparatus.

[0094] Figure 1KIn the illustrated process, the second protective insulating film 10 and the first protective insulating film 9 are removed sequentially by isotropic etching. The etching of the second protective insulating film 10 is performed under selective etching conditions targeting the first protective insulating film 9, the hard mask 7, the gate sidewall spacer 8, the STI insulating film 2, the lower surface of the first SiGe sacrificial layer 3B, and the Si substrate 1. For example, if the second protective insulating film 10 is an Al2O3 film, a mixture of O2, BCl3, and Ar, or a gas based thereon, can be used as the etching gas. This etching is performed for one to two times the etching time required to etch the thickness of the second protective insulating film 10, under conditions where the second protective insulating film 10 is substantially completely removed. Next, the second protective insulating film 10 is removed, and the first protective insulating film 9 is removed by isotropic etching. This etching is performed under selective etching conditions targeting the hard mask 7, the gate sidewall spacer 8, the STI insulating film 2, the lower surface and sidewalls of the first SiGe sacrificial layer 3B, the Si channel 4B, and the Si substrate 1. For example, when the protective insulating film 9 is a Si3N4 film, trifluoromethane (CHF3), difluoromethane (CH2F2), or CH3F gases can be used as the etching gas, or a mixture of carbon-fluorine based gases such as CF4 or C4F8 with H2, or gases based on these. Similar to the etching of the second protective insulating film 10, this etching is performed for 1 to 2 times the etching time required to etch the thickness of the first protective insulating film 9, under conditions where the first protective insulating film 9 is substantially completely removed. Through this process, the sidewalls of the first SiGe sacrificial layer 3B and the Si channel 4B are exposed. This process is equivalent to... Figure 4 The process flow diagram for step 110 can be continued... Figure 1J The etching removal process 109 of the Si sacrificial layer 4A shown is performed continuously in the chamber of the same apparatus. That is, from Figure 4 Vertical etching process 101 for gate sidewall spacers Figure 1B From step 110 until the isotropic etching removal process of the first and second protective insulating films. Figure 1K Until then, it can be carried out continuously in the chamber of the same device. Figure 3F Showing with Figure 1K The corresponding process, the component separation area outside the FET channel region ( Figure 1A The gate cross-section in the AA' line. Due to the vertical etching of the first protective insulating film 9 ( Figure 1E , Figure 3C ), and vertical etching of the second protective insulating film 10 ( Figure 1G , Figure 3E Due to the over-etching effect, the upper surface of the STI insulating film 2 has a curved shape in the region of the gap between adjacent gate sidewall spacers 8. For this shape, in order to deposit the interlayer insulating film ( Figure 1N The second interlayer insulating film (16) facilitates the deposition of an isotropic film, and at the bottom of the gap, the film density of the interlayer insulating film is kept constant. Therefore, it can suppress the formation of voids in the interlayer insulating film due to a decrease in film density.

[0095] Following the series of procedures mentioned above, in Figure 1L In the illustrated process, a gate-substrate separation insulating film 11 is deposited as a buried insulating film (first insulating film). The gate-substrate separation insulating film 11 is formed, for example, using a CVD method. After the gate-substrate separation insulating film 11 is formed, a planarization process is performed to planarize the surface of the gate-substrate separation insulating film 11 using chemical mechanical polishing (CMP) with a hard mask 7 as a barrier. The material of the gate-substrate separation insulating film 11 can be, for example, SiO2, SiON, SiCO, etc. Through the above film formation, the regions where the second SiGe sacrificial layer 3A and the Si sacrificial layer 4A exist are filled by the gate-substrate separation insulating film 11.

[0096] In the next process, the aforementioned gate-substrate separation insulating film 11 is etched back to obtain... Figure 1M The structure shown is such that, for example, the etching amount can be adjusted so that the upper surface of the gate-substrate separation insulating film 11 after etching back is located between the lower and upper surfaces of the bottommost first SiGe sacrificial layer 3B. Through this process, a structure is formed in which the stacked film composed of the first SiGe sacrificial layer 3B and the Si channel 4B is separated from the Si substrate 1 by the gate-substrate separation insulating film 11 (a structure in which the stacked film and the Si substrate 1 are separated by the gate-substrate separation insulating film 11). The gate-substrate separation insulating film 11 can be referred to as a buried insulating film 11.

[0097] Subsequently, it is obtained through a GAA-type FET fabrication process. Figure 1N The transistor structure shown is as follows. In this process, the transistor consists of the formation of the internal spacer 12 of the gate sidewall, the formation of the source and drain 15, the formation of the second interlayer insulating film 16, the etching and removal of the hard mask 7, the dummy gate 6, the dummy gate insulating film 5 and the first SiGe sacrificial layer 3B, the formation of the gate insulating film 13 and the gate metal 14, the formation of the contact barrier metal 17 and the contact metal 18, and then the subsequent metal wiring process.

[0098] The gate sidewall internal spacer 12 is formed, for example, by the following steps: after selectively isotropically etching the first SiGe sacrificial layer 3B relative to the Si channel 4B and other peripheral films to remove a portion of the first SiGe sacrificial layer 3B and form a trench, a low relative permittivity film is deposited in the trench formed in the first SiGe sacrificial layer 3B using a method such as CVD; and a portion of the low relative permittivity film is removed by isotropic etching. Thus, the gate sidewall internal spacer 12 formed inside the trench of the first SiGe sacrificial layer 3B can be obtained. The low relative permittivity film used to form the gate sidewall internal spacer 12 can be, for example, a SiCO film, SiOCN, or SiON film, and films based thereon, or laminates thereof. The isotropic etching of the first SiGe sacrificial layer 3B uses a method such as CVD to deposit a low relative permittivity film. Figure 1I Under the same conditions during the isotropic etching of the second SiGe sacrificial layer 3A shown, for example, the etching time can be adjusted so that the etching depth of the first SiGe sacrificial layer 3B is on the order of 1 to 10 nm. In the isotropic etching of low relative permittivity films, if the low relative permittivity film is, for example, a SiCO film, the etching gas can be, for example, a mixture of fluorine-containing gases such as CHF3, CH2F2, CH3F, and NF3 with N2 and O2, or a gas based thereon.

[0099] The source and drain 15 are formed, for example, by selectively epitaxially growing Si or SiGe on the sidewalls of the Si channel 4B. By performing patterning, different Si or SiGe films are formed in the n-type FET region and the p-type FET region, respectively. Here, Si doped with n-type impurities such as phosphorus (P) and arsenic (As) can be selectively grown in the n-type FET region, and SiGe doped with p-type impurities such as boron (B) can be selectively grown in the p-type FET region.

[0100] The second interlayer insulating film 16 is formed, for example, using a CVD method. The material for the second interlayer insulating film 16 can be, for example, SiO2, SiON, SiCO, etc. The etching removal of the hard mask 7, dummy gate 6, dummy gate insulating film 5, and first SiGe sacrificial layer 3B uses etching gases and etching conditions suitable for each material. When the hard mask 7 is a Si3N4 film, the etching gas can be, for example, CHF3, CH2F2, or CH3F. In the etching of the dummy gate 6, which is made of polysilicon (poly-Si), dry etching using gases such as SF6, CF4, or HBr, or gases based on these, or wet etching using tetramethylammonium hydroxide aqueous solution (TMAH) can be performed. The dummy gate insulating film 5 is removed, for example, by wet etching using an aqueous solution of hydrofluoric acid (HF), etc. In the subsequent etching removal of the first SiGe sacrificial layer 3B, a suitable etching gas and etching conditions can be used. Figure 1I The same conditions are applied during the isotropic etching of the second SiGe sacrificial layer 3A shown. For example, a high dielectric material such as hafnium oxide (HfO2) or Al2O3, or a stack of these high dielectric materials, can be used for the gate insulating film 13.

[0101] The gate metal 14 may, for example, comprise a p-work function control metal that determines the threshold voltage of a p-type FET, an n-work function control metal that determines the threshold voltage of an n-type FET, and a gate-fill metal. The p-work function control metal film may, for example, be titanium nitride (TiN) or tantalum nitride (TaN) film, or a metal compound having an equivalent work function. The n-work function control metal film may, for example, be titanium aluminum (TiAl) or a metal containing carbon (C), oxygen (O), nitrogen (N), etc., in TiAl, or a metal compound having an equivalent work function. The gate-fill metal film is deposited to reduce the metal resistance within the gate; for example, a material such as tungsten (W) can be used. These gate metals 14 are formed, for example, by CVD or ALD methods.

[0102] Patterning is performed to partially etch the second interlayer insulating film 16, thereby forming contact barrier metal 17 and contact metal 18 on the exposed portions of the source and drain 15 in the n-type FET region and p-type FET region. For example, TiN or TaN, or metals based on these, can be used for the contact barrier metal 17, and for example, W or cobalt (Co), can be used for the contact metal 18. The film thickness of the contact barrier metal 17 is designed, for example, to be in the range of 1–3 nm. Figure 1N In the GAA-type FET structure shown, the gate metal 14 and the Si substrate 1 are insulated and separated by the gate-substrate separation insulating film 11 to prevent the Si substrate 1 from operating as a parasitic FET.

[0103] The process of forming the gate-semiconductor substrate insulating separation film 11 is performed by a plasma processing apparatus equipped with ALD film formation function and anisotropic and isotropic etching control function. Figures 1A to 1N The process shown allows for continuous processing within the same plasma treatment unit. Figure 4 The series of processes shown, namely from Figure 1B Vertical etching of the gate sidewall spacers shown ( Figure 4 From 101 until Figure 1K The first and second protective insulating films shown are isotropically etched away. Figure 4 The plasma processing equipment can be any of the following: an etching apparatus using inductively coupled plasma (ICP), an etching apparatus using capacitively coupled plasma (CCP), or an etching apparatus using microwave electron cyclotron resonance (ECR) plasma.

[0104] As an example, Figure 5 The structure of a plasma processing apparatus 200 using microwave ECR plasma is shown. The plasma processing apparatus 200 has a processing chamber 201, which is connected to a vacuum exhaust device (not shown) via a vacuum exhaust port 202. During plasma processing, a vacuum of 0.1 to 10 Pa is maintained within the processing chamber 201. Furthermore, the processing chamber 201 is provided with: a window 203 that allows microwaves to pass through and provides an airtight seal; and a perforated plate 204 for further shielding ions. The perforated plate 204 divides the processing chamber 201 into an upper portion 201A and a lower portion 201B. The window 203 is made of a microwave-transmitting material, such as a dielectric material like quartz. The perforated plate 204 has multiple holes, and its material may include, for example, a dielectric material like quartz or alumina.

[0105] The gas supply mechanism includes a gas source 205, a gas supply device 206, and a gas inlet 207, supplying raw material gases for plasma processing. The gas source 205 can handle multiple types of gases required for processing. The gas supply device 206 includes a control valve for controlling the supply and cutoff of gas, and a mass flow controller for controlling the gas flow rate. Furthermore, the gas inlet 207 is located between the window 203 and the perforated plate 204.

[0106] A waveguide 209 for propagating electromagnetic waves is connected to the upper part of the processing chamber 201, and a high-frequency power supply 208 for plasma generation, serving as a high-frequency power source, is connected to the end of the waveguide 209. The high-frequency power supply 208 is a power source for generating electromagnetic waves for plasma generation, such as microwaves with a frequency of 2.45 GHz. The microwaves generated from the high-frequency power supply 208 propagate in the waveguide 209 and are incident into the processing chamber 201. The waveguide 209 has a vertical waveguide extending in the vertical direction and a waveguide converter that also bends the microwave direction by 90 degrees, thereby vertically incident the microwaves into the processing chamber 201. The microwaves propagate vertically within the processing chamber 201 via a window 203. A magnetic field generating coil 210 disposed on the outer periphery of the processing chamber 201 forms a magnetic field within the processing chamber 201. The microwaves oscillating from the high-frequency power supply 208 generate high-density plasma within the processing chamber 201 through interaction with the magnetic field formed by the magnetic field generating coil 210.

[0107] A sample stage 212 is disposed below the processing chamber 201 and opposite the window 203. The sample stage 212 is made of materials such as aluminum or titanium. The semiconductor substrate 211, serving as the sample, is mounted and held on the upper surface of the sample stage 212. Here, the waveguide 209, the processing chamber 201, the sample stage 212, and the semiconductor substrate 211 are aligned along their central axes. Furthermore, electrodes for electrostatically adsorbing the semiconductor substrate 211 are provided inside the sample stage 212, and the semiconductor substrate 211 is electrostatically adsorbed onto the sample stage 212 by applying a DC voltage. Further, to control the isotropic and anisotropic nature of the etching, a high-frequency voltage is applied to the sample stage 212 from a high-frequency bias power supply 213. The frequency of the applied high-frequency bias voltage can be set to, for example, 400 kHz.

[0108] Each mechanism of the plasma processing apparatus 200 is controlled by control signals 221 from the control unit 220. The control unit 220 controls each mechanism by instructing it to perform a given action according to the processing conditions (anisotropic etching, isotropic etching, ALD film deposition, etc.) executed by the plasma processing apparatus 200 using the control signals 221. For example, the control unit 220 controls the high-frequency power supply 208 for plasma generation and controls the ON-OFF state of the electromagnetic waves used for plasma generation. Furthermore, the control unit 220 controls the gas supply mechanism, adjusting the type and flow rate of the gas introduced into the processing chamber 201. The control unit 220 also controls the high-frequency bias power supply 213 and controls the intensity of the high-frequency voltage applied to the semiconductor substrate 211 on the sample stage 212.

[0109] When performing anisotropic etching using this plasma processing apparatus 200, the control unit 220 controls the magnetic field generating coil 210 to generate plasma in the lower part 201B of the processing chamber 201 below the porous plate 204. Since the porous plate 204 is fabricated in a dielectric, microwaves pass through the porous plate 204 and interact with the magnetic field in the lower part 201B of the processing chamber 201 to generate plasma. Furthermore, a high-frequency bias voltage is applied to the sample stage 212 on which the Si substrate 1, which serves as a semiconductor substrate 211, is placed. As a result, ions in the plasma are drawn toward the Si substrate 1 without being blocked by the porous plate 204, etc., enabling etching that maintains perpendicularity.

[0110] When performing isotropic etching using this plasma processing apparatus 200, the control unit 220 controls the magnetic field generating coil 210 so that the plasma generation position is the upper part 201A of the processing chamber 201 above the porous plate 204. Since the ions in the plasma generated in the upper part 201A of the processing chamber 201 are shielded by the porous plate 204, only free radicals from the plasma are supplied to the lower part 201B of the processing chamber. As a result, isotropic etching using free radicals can be performed.

[0111] When forming a film using the ALD method with this plasma processing apparatus 200, the following cyclic process under the control of the control unit 220 can be applied. For example, when forming a Si3N4 film using the ALD method, BTBAS or BDEAS as Si raw materials, or SiH2Cl2 as a gaseous gas, are used. When using BTBAS or BDEAS as liquid raw materials, the liquid raw materials are vaporized and sent to the gas line as a gaseous gas. The gaseous gas of the raw materials, together with Ar as a charge carrier gas, are sent into the processing chamber 201 and adsorbed onto the substrate surface as a Si precursor. Then, the unwanted precursor in the processing chamber 201 is vented using a cleaning gas such as Ar gas. Next, N2 gas, or a mixture of N2 gas and H2 gas, or a nitrogen-containing gas such as NH3 gas, is introduced into the processing chamber 201 for plasma formation, where it reacts with the substrate surface. Subsequently, an inert gas such as Ar is introduced into the processing chamber 201 again to clean the chamber and remove any unwanted gases. Through this series of processes, a Si3N4 film with atomic-layer thickness is deposited on the substrate surface. By repeating this series of processes (cyclic process implementation), an insulating thin film is formed using the ALD method. For example, in the case of forming an Al2O3 film using the ALD method, Al(CH3)3 can be used as the Al precursor, and vaporized H2O can be used as the oxygen feedstock. The same cyclic process as described above for Si3N4 is then performed to form the Al2O3 film.

[0112]

Example 2

[0113] In Example 2, the following method is provided: During the formation of a gate-semiconductor substrate insulating separation film ( Figure 6B When 311 (corresponding to the gate-semiconductor substrate insulating separation film 11 in Example 1) is used, it protects the Si channel sidewall.

[0114] Figure 6A The gate-semiconductor substrate insulating separation film formation process described in Example 1 is shown. Figures 1A to 1N The process shown is in conjunction with Figure 1J The diagram shown is identical to the one after the removal of the Si sacrificial layer 4A. In this embodiment, continuous processing is performed within the same plasma processing apparatus 200. Figure 4 Processes 101 to 109, that is, from Figure 1B The gate sidewall spacers shown are vertically etched up to... Figure 1J The Si sacrificial layer 4A shown is removed by isotropic etching, and then the Si substrate 1 is removed from the plasma apparatus 200.

[0115] After that, Figure 6B In the illustrated process, a gate-substrate separation insulating film 311 is deposited, and surface planarization is performed using CMP with a hard mask 307 as a barrier. The gate-substrate separation insulating film 311 is formed, for example, using a CVD method. The material of the gate-substrate separation insulating film 311 is, for example, SiO2, SiON, SiCO, etc. Through the above film formation, the region between the first SiGe sacrificial layer 303 and the Si substrate 301 is filled by the gate-substrate separation insulating film 311, and the gate-substrate separation insulating film 311 is also deposited on the sidewalls of the first protective insulating film 309 and the second protective insulating film 310.

[0116] exist Figure 6C In the illustrated process, the gate-substrate separation insulating film 311 is etched back in the vertical direction. The etching amount can be adjusted so that the upper surface of the gate-substrate separation insulating film 311 after etching back is located between the lower surface of the second protective insulating film 310 and the upper surface of the bottommost first SiGe sacrificial layer 303. During this etch-back process, since the sidewalls of the laminated film composed of the first SiGe sacrificial layer 303 and the Si channel 304 are protected by the first protective insulating film 309 and the second protective insulating film 310, the sidewalls of the Si channel 304 are not damaged by ions and free radicals during etch-back. Therefore, it is possible to fabricate a GAA-type FET in which the degradation of transistor characteristics caused by etching damage is suppressed.

[0117] Next, in Figure 6DIn the illustrated process, the second protective insulating film 310 and the first protective insulating film 309 are sequentially removed by isotropic etching. The etching conditions, excluding the etching time, can be the same as in Example 1. After etching, the second protective insulating film 310 and the first protective insulating film 309 may remain to fill the trench formed between the gate-substrate separation insulating film 311 and the first SiGe sacrificial layer 303. The etching times for the second protective insulating film 310 and the first protective insulating film 309 are adjusted so that the upper surfaces of the etched second protective insulating film 310 and the first protective insulating film 309 are approximately aligned with the upper surface of the gate-substrate separation insulating film 311. The presence of the remaining second protective insulating film 310 and the first protective insulating film 309 within the trench suppresses the formation of voids originating from the trench in subsequent processes.

[0118]

Example 3

[0119] In Example 3, a method is provided to simplify the formation process of the internal spacer (12 in Example 1) of the gate sidewall. Figures 7A to 7K A cross-sectional view of the process using this method is shown. Figure 8 A flowchart of a process using this method is shown.

[0120] Figure 7A Showing with Figure 1C The first SiGe sacrificial layer 3B shown is Figure 7A The middle is 402B) and Si channel 4B ( Figure 7A The image shows a cross-sectional view perpendicular to the gate direction corresponding to the anisotropic etching process of the stacked film composed of Si sacrificial layer 4A. The image also shows the etching process to the Si sacrificial layer 4A. Figure 1C Unlike other methods, etching stops on the Si sacrificial layer 403A. In this embodiment, it is preferable to stop etching on the top of the Si sacrificial layer 403A. Figure 7A In this process, after etching the stacked film consisting of the first SiGe sacrificial layer 402B and the Si channel 403B in the vertical direction, the etching ends with the Si sacrificial layer 403A exposed. Through over-etching, the depth to which the Si sacrificial layer 403A is etched can be adjusted, for example, to a range from 0 nm to approximately 90% of the thickness of the Si sacrificial layer 403A film. This process is equivalent to... Figure 8 The 502 process flow can continue... Figure 1B Etching of the gate sidewall spacer 8 shown ( Figure 8 (501), and carried out continuously in the chamber of the same device.

[0121] exist Figure 7BIn this process, the first SiGe sacrificial layer 402B is etched isotropically. The etching conditions are the same as in Example 1, performed under selective etching conditions targeting the hard mask 406, gate sidewall spacer 407, STI insulating film (not shown), and Si channel 403B and Si sacrificial layer 403A. The etching time is adjusted so that the etching depth is, for example, on the order of 1 to 10 nm. This process is equivalent to... Figure 8 The 503 process flow can continue... Figure 7A The anisotropic etching of the laminated film consisting of the first SiGe sacrificial layer 402B and the Si channel 403B is shown. Figure 8 (502), and carried out continuously in the chamber of the same device.

[0122] exist Figure 7C In this process, a first protective insulating film 408 is deposited using an ALD-based film deposition technique. The first protective insulating film 408 is deposited on the upper surface and sidewalls of the hard mask 406 and the gate sidewall spacer 407, the sidewalls of the stacked film composed of the first SiGe sacrificial layer 402B and the Si channel 403B, the upper surface of the Si sacrificial layer 403A, and an STI insulating film (not shown). Here, the aforementioned first protective insulating film 408 is deposited on... Figure 7B A film is also formed in the trenches created by isotropic etching of the first SiGe sacrificial layer 402B. In this region, films are also formed on the upper and lower surfaces of the exposed Si channel 403B. The material of the first protective insulating film 408 is preferably a nitrogen-containing insulating film, such as a Si3N4 film or a SiON film based thereon, considering the etching selectivity between the laminated film composed of the first SiGe sacrificial layer 402B and the Si channel 403B, the Si sacrificial layer 403A, and the surrounding STI insulating film (not shown). The film thickness of the first protective insulating film 408 is controlled, for example, to approximately 2-3 nm. The film formation conditions using the ALD method can be the same as in Example 1. This process is equivalent to... Figure 8 The 504 process flow can continue... Figure 7B The isotropic etching of the first SiGe sacrificial layer 402B shown ( Figure 8 (503), and carried out continuously in the chamber of the same device.

[0123] exist Figure 7DIn the illustrated process, the first protective insulating film 408 is etched in the vertical direction. This etching is performed under selective etching conditions for the hard mask 406, the gate sidewall spacer 407, the Si sacrificial layer 403A, and the STI insulating film (not shown). For example, if the first protective insulating film 408 is a Si3N4 film, the etching conditions shown in Example 1 can be used. After this process, the upper surface of the Si sacrificial layer 403A is exposed. The etching conditions are controlled such that after this etching, the residual film thickness of the Si sacrificial layer 403A is, for example, 10% to 100% of the initial film thickness of the Si sacrificial layer 403A. The horizontal distance between the opening region of the Si sacrificial layer 403A exposed after etching of the first protective insulating film 408 in this process and the first SiGe sacrificial layer 402B is different from that in Example 1. Figure 1E The situation becomes larger compared to that of the first protective insulating film 408. Therefore, even if the first protective insulating film 408 has been etched, it is still larger than that of the case where... Figure 2B The situation is also different; the sidewalls of the first SiGe sacrificial layer 402B are less likely to be exposed. This process is equivalent to... Figure 8 The 505 process flow can be continued... Figure 7C The first protective insulating film 408 shown is formed ( Figure 8 (504), and carried out continuously in the chamber of the same device.

[0124] Figure 7E In the process shown, a second protective insulating film 409 is formed on the first protective insulating film 408 using the ALD method. The second protective insulating film 409 is deposited on the hard mask 406, the gate sidewall spacer 407, the upper surface and sidewalls of the first protective insulating film 408, the upper surface of the Si sacrificial layer 403A, and the STI insulating film (not shown). Figure 7C After the first protective insulating film 408 is formed, if gaps remain due to the grooves created by the isotropic etching of the first SiGe sacrificial layer 402B, the second protective insulating film 409 is formed in this step to fill these gaps. Al2O3 films, AlON films, etc., which can be formed isotropically with good control even for complex shapes with finer textures, are used for the second protective insulating film 409. For example, in the case of forming an Al2O3 film, the same conditions as in Example 1 can be used. This step is equivalent to... Figure 8 The 506 process flow can continue... Figure 7D Anisotropic etching of the first protective insulating film 408 shown ( Figure 8 (505), and carried out continuously in the chamber of the same device.

[0125] exist Figure 7FIn the illustrated process, the second protective insulating film 409 is etched in the vertical direction. This etching is performed under selective etching conditions targeting the first protective insulating film 408, the hard mask 406, the gate sidewall spacer 407, the Si sacrificial layer 403A, and the STI insulating film (not shown). For example, if the protective insulating film 409 is an Al2O3 film, the etching conditions shown in Example 1 can be used. After this process, the upper surface of the Si sacrificial layer 403A is exposed. The etching conditions are controlled such that after this etching, the residual film thickness of the Si sacrificial layer 403A is, for example, 10% to 100% of the initial film thickness of the Si sacrificial layer 403A. Figure 7E In this process, since the second protective insulating film 409 is formed to fill the gaps formed on the sidewalls of the first protective insulating film 408, the distance between the sidewalls of the second protective insulating film 409 and the sidewalls of the Si channel 403B can be sufficiently maintained during the etching of the second protective insulating film 409 in this process, as well as the etching of the Si sacrificial layer 403A and the second SiGe sacrificial layer 402A following this process, thus providing sufficient protection for the corners of the sidewalls of the Si channel 403B. Without the second protective insulating film 409, when the thickness of the first protective insulating film 408 thins at the corners of the sidewalls of the Si channel 403B, there is a concern that the corners of the sidewalls of the Si channel 403B may be damaged during this process and the etching following this process. This process is equivalent to... Figure 8 The 507 process flow can continue... Figure 7E The second protective insulating film 409 shown is formed ( Figure 8 (506), and carried out continuously in the chamber of the same device.

[0126] exist Figure 7G In the illustrated process, the Si sacrificial layer 403A and the second SiGe sacrificial layer 402A are etched in the vertical direction. This etching is an anisotropic selective etching using the hard mask 406, the gate sidewall spacer 407, and the second protective insulating film 409 as masks. The Si sacrificial layer 403A and the second SiGe sacrificial layer 402A are etched vertically along the sidewall of the second protective insulating film 409. In this process, the etching ends at the point when the Si substrate 1 is exposed. The etching in this process is described in Example 1. Figure 1C This process can be performed under the same conditions as the anisotropic etching used when patterning the stacked SiGe layers 3 and Si layers 4. This process is equivalent to... Figure 8 The 508 process flow can continue... Figure 7F Anisotropic etching of the second protective insulating film 409 shown ( Figure 8 (507), and carried out continuously in the chamber of the same device.

[0127] exist Figure 7HIn the process shown, the second SiGe sacrificial layer 402A and the Si sacrificial layer 403A are sequentially removed by isotropic etching. The etching of the second SiGe sacrificial layer 402A can use selective etching conditions for the second protective insulating film 409, the first protective insulating film 408, the hard mask 406, the gate sidewall spacer 407, the STI insulating film (not shown), and the Si sacrificial layer 403A and the Si substrate 401, similar to Example 1. Figure 1I The etching of the Si sacrificial layer 403A can be performed under the same conditions as in Example 1. The etching of the Si sacrificial layer 403A can use selective etching conditions for the second protective insulating film 409, the first protective insulating film 408, the hard mask 406, the gate sidewall spacer 407, the STI insulating film (not shown), and the second SiGe sacrificial layer 402B. Figure 1J This process is performed under the same conditions as the one used. Figure 8 The process flow 509 can continue... Figure 7G Anisotropic etching of the Si sacrificial layer 403A and the second SiGe sacrificial layer 402A shown ( Figure 8 (508), and carried out continuously in the chamber of the same device.

[0128] exist Figure 7I In the illustrated process, the second protective insulating film 409 and the first protective insulating film 408 are sequentially removed by isotropic etching. The etching of the second protective insulating film 409 is performed under selective etching conditions targeting the first protective insulating film 408, the hard mask 406, the gate sidewall spacer 407, the STI insulating film (not shown), the lower surface of the first SiGe sacrificial layer 402B, and the Si substrate 401. For example, if the second protective insulating film 409 is an Al2O3 film, the etching conditions of Example 1 can be used. Figure 1K The etching of the first protective insulating film 408 is performed under selective etching conditions for the hard mask 406, gate sidewall spacer 407, STI insulating film (not shown), first SiGe sacrificial layer 402B, Si channel 403B, and Si substrate 401. For example, if the first protective insulating film 408 is a Si3N4 film, the etching conditions can use those of Example 1. Figure 1K The conditions shown are as follows. Through this process, the gate sidewall spacer 407, as well as the sidewalls of the first SiGe sacrificial layer 402B and the Si channel 403B, are exposed. Furthermore, the upper and lower surfaces of the Si channel 403B in the region of the trench formed by isotropic etching of the first SiGe sacrificial layer 402B are also simultaneously exposed. This process is equivalent to... Figure 8 The process flow diagram 510 can be continued... Figure 7H The etching removal of the second SiGe sacrificial layer 402A and Si sacrificial layer 403A shown ( Figure 8(509), can be performed continuously within the chamber of the same device. That is, it is possible to perform continuously within the chamber of the same device. Figure 8 The process flow shown involves vertical etching of 501 from the gate sidewall spacer. Figure 1B From 510 (until the first and second protective insulating films are isotropically etched away) Figure 7I )until.

[0129] Next, in Figure 7J In the process shown, a gate-substrate separation insulating film 410 is deposited, and surface planarization is performed using CMP with a hard mask 406 as a barrier. The gate-substrate separation insulating film 410 is formed, for example, using a CVD method. The material of the gate-substrate separation insulating film 410 is, for example, SiO2, SiON, SiCO, etc. Through the above film formation, the area between the lower surface of the first SiGe sacrificial layer 402B and the Si substrate 401 is filled by the gate-substrate separation insulating film 410, and the groove between the sidewall of the first SiGe sacrificial layer 402B and the upper and lower Si channels 403B is also filled by the gate-substrate separation insulating film 410.

[0130] exist Figure 7K In the illustrated process, anisotropic etching is performed in the vertical direction of the gate-substrate separation insulating film 410. The etching of the gate-substrate separation insulating film 410 is performed under selective etching conditions targeting the hard mask 406, the gate sidewall spacer 407, the STI insulating film (not shown), and the sidewalls of the Si channel 403B. The etching time is controlled so that the upper surface of the etched gate-substrate separation insulating film 410 is located between the lower and upper surfaces of the lowest layer of the first SiGe sacrificial layer 402B. Through this process, the groove between the sidewalls of the first SiGe sacrificial layer 402B and the upper and lower Si channels 403B is filled by the interlayer insulating film 410, allowing the formation of the internal spacer of the gate sidewall to occur simultaneously with the formation of the gate-substrate separation insulating film 410.

[0131] As described above, in this embodiment, the internal spacer of the gate sidewall can be formed simultaneously with the gate-semiconductor substrate insulating separator, simplifying the process steps. Furthermore, as... Figure 7D As shown, exposure of the first SiGe sacrificial layer 402B can be avoided during the etching of the protective insulating film. Furthermore, in this embodiment, the etching of the Si sacrificial layer 403A and the second SiGe sacrificial layer 402A is performed while the sidewalls of the stacked film of the first SiGe sacrificial layer 402B and the Si channel 403B have an uneven shape. However, as... Figure 7F As shown, by providing a second protective insulating film 409, damage to the corners of the sidewalls of the Si channel 403B can also be reduced.

[0132]

Example 4

[0133] In Example 4, a method is provided to also use the protective insulating film in the reinforcement of the internal spacers of the gate sidewall.

[0134] Figure 9A This demonstrates the use of the same process as in Example 3. Figure 7B The image shows a cross-sectional view of the first SiGe sacrificial layer 402B after isotropic etching. In this embodiment, etching was performed continuously within the chamber of the same device. Figure 8 After the gate sidewall spacer shown in 501 is vertically etched until the first SiGe sacrificial film shown in 503 is isotropically etched, the Si substrate 601 is removed from the device.

[0135] After that, Figure 9B In this process, for example, a low relative permittivity film 608 for forming the internal spacers of the gate sidewall is formed using a CVD method. For example, a SiCO film, SiOCN film, or SiON film, as well as films based thereon and their stacks, can be used for the low relative permittivity film 608. After this process, the Si substrate 601 is re-processed. Figure 9A The plasma treatment apparatus shown is used to perform the process. Figure 9C The following procedures.

[0136] exist Figure 9C In this process, isotropic etching of the low relative permittivity film 608 is performed to form the internal spacer of the gate sidewall. The etching is performed under the same conditions as in Example 1, and the etching time can be adjusted to expose the sidewall of the Si channel 603B. After this etching, it is envisioned that the sidewall of the internal spacer 608 of the gate sidewall has a curved shape.

[0137] exist Figure 9D In this process, a first protective insulating film 609 is deposited using an ALD-based film deposition technique. The first protective insulating film 609 is deposited on the upper surface and sidewalls of the hard mask 606 and the gate sidewall spacer 607, the sidewalls of the gate sidewall internal spacer 608, the sidewalls of the Si channel 603B, the upper surface of the Si sacrificial layer 603A, and an STI insulating film (not shown). The film deposition conditions for the first protective insulating film 609 can be the same as those in Example 1. Figure 1D The conditions shown are equivalent to those described above. This process can continue. Figure 9C The isotropic etching of the low relative permittivity film 608 shown is performed continuously in the chamber of the same device.

[0138] exist Figure 9EIn the illustrated process, the first protective insulating film 609 is etched in the vertical direction. This etching is performed under selective etching conditions for the hard mask 606, the gate sidewall spacer 607, the Si sacrificial layer 603A, and the STI insulating film (not shown). For example, if the first protective insulating film 609 is a Si3N4 film, the etching conditions shown in Example 1 can be used. After this process, the upper surface of the Si sacrificial layer 603A is exposed. The etching conditions are controlled such that after this etching, the residual film thickness of the Si sacrificial layer 603A is, for example, 10% to 100% of the initial film thickness of the Si sacrificial layer 603A.

[0139] exist Figure 9F In the process shown, a second protective insulating film 610 is formed on the first protective insulating film 609 using the ALD method. The second protective insulating film 610 is deposited on the hard mask 606, the gate sidewall spacer 607, the upper surface and sidewalls of the first protective insulating film 609, the upper surface of the Si sacrificial layer 603A, and the STI insulating film (not shown). Figure 9D After the first protective insulating film 609 is formed, if gaps remain due to the curved shape of the gate sidewall spacer 607, the second protective insulating film 610 is formed in this step to fill these gaps. For example, an Al2O3 film or an AlON film, which can be formed isotropically with good control even for complex shapes with finer irregularities, can be used for the second protective insulating film 610. In the case of forming an Al2O3 film, for example, the same conditions as in Example 1 can be used. This step can then proceed... Figure 9E The anisotropic etching of the first protective insulating film 609 shown is performed continuously in the chamber of the same device.

[0140] exist Figure 9G In the illustrated process, the second protective insulating film 610 is etched in the vertical direction. This etching is performed under selective etching conditions for the first protective insulating film 609, hard mask 606, gate sidewall spacer 607, Si sacrificial layer 603A, and STI insulating film (not shown). For example, if the protective insulating film 610 is an Al2O3 film, the etching conditions shown in Example 1 can be used. After this process, the upper surface of the Si sacrificial layer 603A is exposed. The etching conditions are controlled such that after this etching, the residual film thickness of the Si sacrificial layer 603A is, for example, 10% to 100% relative to the initial film thickness of the Si sacrificial layer 603A. This process can then proceed... Figure 9F The formation of the second protective insulating film 610 shown is carried out continuously in the chamber of the same device.

[0141] exist Figure 9HIn the illustrated process, the Si sacrificial layer 603A and the second SiGe sacrificial layer 602A are etched in the vertical direction. This etching is an anisotropic selective etching using the hard mask 606, the gate sidewall spacer 607, and the second protective insulating film 610 as masks. The Si sacrificial layer 603A and the second SiGe sacrificial layer 602A are etched vertically along the sidewalls of the second protective insulating film 610. In this process, the etching ends at the point when the Si substrate 601 is exposed. The etching in this process can be performed similarly to that in Example 1. Figure 1C The anisotropic etching of the SiGe layer 3 and Si layer 4 stacked film pattern is performed under the same conditions. This process can be continued... Figure 9G The anisotropic etching of the second protective insulating film 610 shown is performed continuously in the chamber of the same device.

[0142] exist Figure 9I In the process shown, the second SiGe sacrificial layer 602A and the Si sacrificial layer 603A are sequentially removed by isotropic etching. The etching of the second SiGe sacrificial layer 602A can use selective etching conditions for the second protective insulating film 609, the first protective insulating film 608, the hard mask 606, the gate sidewall spacer 607, the STI insulating film (not shown), and the Si sacrificial layer 603A and the Si substrate 601, similar to Example 1. Figure 1I The etching of the Si sacrificial layer 603A can be performed under the same conditions as in Example 1. The etching of the Si sacrificial layer 603A can use selective etching conditions for the second protective insulating film 610, the first protective insulating film 609, the hard mask 606, the gate sidewall spacer 607, the gate sidewall inner spacer 608, the STI insulating film (not shown), and the first SiGe sacrificial layer 602B. Figure 1J The process is carried out under the same conditions as the one used. This process can continue. Figure 9H The anisotropic etching of the Si sacrificial layer 603A and the second SiGe sacrificial layer 602A shown is performed continuously in the chamber of the same device.

[0143] exist Figure 9J In the illustrated process, isotropic etching of the second protective insulating film 610 and the first protective insulating film 609 is performed sequentially. The etching of the second protective insulating film 610 is performed under selective etching conditions targeting the first protective insulating film 609, the hard mask 606, the gate sidewall spacer 607, the STI insulating film (not shown), the lower surface of the first SiGe sacrificial layer 602B, and the Si substrate 601. For example, if the second protective insulating film 610 is an Al2O3 film, the etching conditions of Example 1 can be used. Figure 1KThe conditions shown are as follows. Here, the isotropic etching of the second protective insulating film 610 is performed by adjusting the etching time so that the sidewalls of the first protective insulating film 609 are exposed after etching, but it is preferable to adjust it so that the second protective insulating film 610 remains in the gaps caused by the curved shape of the sidewalls of the gate sidewall spacer 608. The etching of the first protective insulating film 609 can be performed under selective etching conditions for the second protective insulating film 610, the hard mask 606, the gate sidewall spacer 607, the STI insulating film (not shown), the gate sidewall spacer 608, the lower surface of the first SiGe sacrificial layer 602B, and the Si channel 603B and the Si substrate 601. For example, when the first protective insulating film 609 is a Si3N4 film, the etching conditions can be those of Example 1. Figure 1K The conditions are shown. In the etching process of this step, the etching time is adjusted so that the sidewalls of the gate sidewall spacer 607, the gate sidewall inner spacer 608, and the Si channel 603B are exposed; however, it is preferable to adjust it so that the second protective insulating film 610 and the first protective insulating film 609, which are buried in the gap caused by the curved shape of the sidewall of the gate sidewall inner spacer 608, remain. This step can then proceed... Figure 9I The etching removal processes of the second SiGe sacrificial layer 602A and the Si sacrificial layer 603A shown are performed continuously within the same apparatus chamber. That is, the etching removal processes from the second SiGe sacrificial layer 602A and the third Si sacrificial layer 603A can be performed continuously within the same apparatus chamber. Figure 9C The isotropic etching shown for the low-dielectric-constant film used to form the inner spacer 608 of the gate sidewall is performed until... Figure 9J The isotropic etching of the second protective insulating film 610 and the first protective insulating film 609 shown is continued.

[0144] Subsequently, by implementing Example 1 Figure 1L The GAA-type FET will be completed using the process shown below. The GAA-type FET made in this embodiment can avoid current leakage caused by micropores due to the recessed shape of the internal spacer 608 of the gate sidewall because the recess of the internal spacer 608 of the gate sidewall is filled by the second protective insulating film 610 and the first protective insulating film 609.

[0145] Explanation of reference numerals in the attached figures

[0146] 1. 301, 401, 601: Silicon substrate; 2. 302: Component separation (STI) insulating film; 3: Monocrystalline silicon-germanium layer; 3A, 402A, 602A: Second silicon-germanium sacrificial layer; 3B, 303, 402B, 602B: First silicon-germanium sacrificial layer; 4: Monocrystalline silicon layer; 4A, 403A, 603A: Silicon sacrificial layer; 4B, 304, 403B, 603B: Silicon channel layer; 5. 305, 404, 604: Dummy gate insulating film; 6. 306, 405, 605: Polycrystalline silicon dummy gate; 7. 307, 406, 606: Hard mask; 8. 308, 407, 607: Gate sidewall spacers; 9. 309, 408, 609: First protective insulating film; 0, 310, 409, 610: Second protective insulating film; 11, 311, 410: Gate-substrate separation insulating film; 12, 608: Internal spacer of gate sidewall; 13: Gate insulating film; 14: Gate metal; 15: Source / drain; 16: Second interlayer insulating film; 17: Contact barrier metal; 18: Contact metal; 101, 501: Vertical etching process of gate sidewall spacer; 102, 502: Vertical etching process of silicon / silicon-germanium stacked film; 503: Isotropic etching of first SiGe sacrificial film; 103, 504: First protective insulating film deposition process; 104, 505: Vertical etching process of first protective insulating film; 105, 506: Second protective insulating film deposition process; 10 6, 507: Vertical etching process of the second protective insulating film; 107: Anisotropic etching process of the second silicon-germanium sacrificial film; 108: Isotropic etching process of the second silicon-germanium sacrificial film; 109: Isotropic etching process of the silicon sacrificial film; 508: Anisotropic etching of the silicon sacrificial film / second silicon-germanium sacrificial film; 509: Isotropic etching of the silicon sacrificial film / second silicon-germanium sacrificial film; 110, 510: Isotropic etching process of the first / second protective insulating film; 201: Processing chamber; 201A: Upper region of the processing chamber; 201B: Lower region of the processing chamber; 202: Vacuum exhaust port; 203: Window; 204: Perforated plate; 205: Gas source; 206: Gas supply device; 207: Gas inlet; 208 209: High-frequency power supply for plasma generation; 210: Waveguide; 211: Magnetic field generating coil; 212: Semiconductor substrate; 213: Sample stage; 220: High-frequency bias power supply; 221: Control unit; 222: Control signal; t1: Horizontal thickness of the first protective insulating film; t2: Vertical thickness of the first protective insulating film at the bottom of the tank; t3: Horizontal thickness of the second protective insulating film; t4: Horizontal thickness of the second protective insulating film at the bottom of the tank; t5: Vertical thickness of the second protective insulating film at the bottom of the tank; θ1: Angle between the sidewall of the silicon / silicon-germanium laminate and the upper surface of the second silicon-germanium sacrificial layer 3A; θ2: Angle between the sidewall of the silicon / silicon-germanium laminate and the lower surface of the etched first protective insulating film.a1: The flow path of the raw material gas during the formation of the second protective insulating film; a2: The ion irradiation path during the etching of the second protective insulating film.

Claims

1. A method for manufacturing a semiconductor device, wherein a gate forming region has a stacked channel in which fine wire-like or sheet-like channels are stacked in a direction perpendicular to the substrate, and the gate and the semiconductor substrate are insulated and separated by an insulating film, characterized in that, The semiconductor device has the following structure: a multilayer film formed by alternating layers of a first semiconductor layer and a second semiconductor layer is formed on the semiconductor substrate; the gate and a gate sidewall spacer film are further formed on the multilayer film; a portion of the multilayer film is etched away along the gate sidewall spacer film; and a portion or all of the bottommost first semiconductor layer, or a portion or all of the bottommost second semiconductor layer formed on the bottommost first semiconductor layer, is left unetched and remains. The method for manufacturing the semiconductor device includes: In the first step, a protective insulating film is deposited on the sidewall of the laminated film formed by the etching process, which consists of the first semiconductor layer and the second semiconductor layer. In the second step, the protective insulating film is anisotropically etched in the vertical direction to expose the surface of the bottommost first semiconductor layer or the bottommost second semiconductor layer. In the third step, the first and second steps are repeated multiple times using an insulating film material different from the protective insulating film to form a laminated film on the sidewall consisting of the protective insulating film and multiple protective insulating films different from the protective insulating film. as well as In the fourth step, the bottommost first semiconductor layer, or the bottommost first semiconductor layer and the bottommost second semiconductor layer, are etched away.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The first to the fourth processes are performed continuously within the same plasma processing apparatus.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, The semiconductor substrate is silicon, the first semiconductor layer is silicon-germanium, and the second semiconductor layer is silicon.

4. The method for manufacturing a semiconductor device according to claim 1, wherein, The film in the laminated protective insulating film that is in contact with the sidewall of the laminated film composed of the first semiconductor layer and the second semiconductor layer is composed of a film containing silicon and nitrogen elements, and the film on the upper side of the laminated protective insulating film is composed of a film containing aluminum and oxygen elements.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, After the second step, the sidewalls of the second and subsequent first semiconductor layers stacked on the bottom first semiconductor layer are exposed, and the sidewalls are covered by the laminated film of the protective insulating film formed in the third step.

6. The method for manufacturing a semiconductor device according to claim 1, wherein, Continuous processing within the same plasma treatment unit: Vertical etching of the gate sidewall spacer film used to form the gate sidewall spacer film; A process of removing a portion of the laminated film composed of the first semiconductor layer and the second semiconductor layer by vertical etching; The first to the fourth processes; and The process of removing the laminated protective insulating film by isotropic etching.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, Continuous processing within the same plasma treatment unit: Vertical etching of the gate sidewall spacer film used to form the gate sidewall spacer film; A process of removing a portion of the laminated film composed of the first semiconductor layer and the second semiconductor layer by vertical etching; as well as The first to the fourth processes, A first insulating film is deposited to insulate the gate and the semiconductor substrate in subsequent processes and then vertically etched.

8. The method for manufacturing a semiconductor device according to claim 1, wherein, After removing a portion of the laminated film composed of the first semiconductor layer and the second semiconductor layer by vertical etching, isotropic etching is performed on the sidewalls of the first semiconductor layer other than the bottom layer. Then, the first to fourth processes and the process of removing the laminated film of the protective insulating film by isotropic etching are performed continuously in the same plasma processing apparatus.

9. The method for manufacturing a semiconductor device according to claim 1, wherein, The method for manufacturing the semiconductor device includes the following steps: after removing a portion of the laminated film composed of the first semiconductor layer and the second semiconductor layer by vertical etching, isotropically etching the sidewalls of the first semiconductor layer other than the bottom layer, and depositing a low-dielectric-constant film in the trench formed by the isotropic etching. Continuous processing within the same plasma treatment unit: The process of removing a portion of the low dielectric constant film by isotropic etching and forming an internal spacer for the gate sidewall made of the low dielectric constant film in the trench. The first to the fourth processes; as well as The process of removing a portion of the laminated protective insulating film by isotropic etching. After a series of processes, the laminated protective insulating film will be formed in the gaps of the sidewalls of the internal spacers of the gate sidewall.

10. A plasma processing method for plasma processing a structure having a multilayer film formed by alternating layers of a first semiconductor layer and a second semiconductor layer on a semiconductor substrate, further forming a gate and a gate sidewall spacer film on the multilayer film, etching away a portion of the multilayer film along the gate sidewall spacer film, and leaving a portion or all of the bottommost first semiconductor layer, or a portion or all of the bottommost second semiconductor layer formed on the bottommost first semiconductor layer, unetched. The plasma treatment method is performed continuously: In the first step, a protective insulating film is deposited on the sidewall of the laminated film formed by the etching process, which consists of the first semiconductor layer and the second semiconductor layer. In the second step, the protective insulating film is anisotropically etched in the vertical direction to expose the surface of the bottommost first semiconductor layer or the bottommost second semiconductor layer. In the third step, steps 1 and 2 are repeated multiple times using an insulating film material different from the protective insulating film to form a laminated protective insulating film on the sidewall; and In the fourth step, the bottommost first semiconductor layer, or the bottommost first semiconductor layer and the bottommost second semiconductor layer, are removed by isotropic etching.

11. The plasma treatment method according to claim 10, wherein, Continuous execution within a single plasma processing unit: Vertical etching of the gate sidewall spacer film used to form the gate sidewall spacer film; A process of removing a portion of the laminated film composed of the first semiconductor layer and the second semiconductor layer by vertical etching; The first to the fourth processes; and The process of removing the laminated protective insulating film by isotropic etching.

12. The plasma treatment method according to claim 10, wherein, Continuous execution within a single plasma processing unit: Vertical etching of the gate sidewall spacer film used to form the gate sidewall spacer film; The process of removing a portion of the laminated film composed of the first semiconductor layer and the second semiconductor layer by vertical etching; and The first to the fourth processes.

13. The plasma treatment method according to claim 10, wherein, After removing a portion of the laminated film composed of the first semiconductor layer and the second semiconductor layer by vertical etching, isotropic etching is performed on the sidewalls of the first semiconductor layer other than the bottommost first semiconductor layer. Then, the first to fourth steps and the step of removing the laminated film of the protective insulating film by isotropic etching are performed continuously in a plasma processing apparatus.

14. The plasma treatment method according to claim 10, wherein, The plasma processing method includes the following steps: after removing a portion of the stacked film composed of the first semiconductor layer and the second semiconductor layer by vertical etching, isotropic etching is performed on the sidewalls of the first semiconductor layer other than the bottommost first semiconductor layer, and a low dielectric constant film is deposited in the trench formed by the isotropic etching. Continuous execution within a single plasma processing unit: The process of removing a portion of the low dielectric constant film by isotropic etching and forming an internal spacer for the gate sidewall made of the low dielectric constant film in the trench. The first to the fourth processes; and The process of removing a portion of the laminated film of the protective insulating film by isotropic etching.

15. The plasma treatment method according to any one of claims 10 to 14, wherein, In the first and third steps, the protective insulating film is deposited using the ALD method.

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