An electronic synaptic circuit and neural network circuit based on ferroelectric tunnel junction

Abstract

The present application relates to a neural network circuit, comprising a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synapse circuit comprises at least: a first transistor, a weight unit, a second transistor, a third transistor, and a fourth transistor; the present application also relates to an electronic device comprising the aforementioned neural network circuit.

Description

Technical Field

[0001] The present application relates to the field of neural network circuit design, and in particular to an electronic synapse circuit and a neural network circuit based on a ferroelectric tunnel junction. Background Art

[0002] Currently, the mainstream computer architecture is the von Neumann architecture, which separates memory and computation. Each computation requires frequent data exchange between the processing unit and the memory unit. This significantly limits the computer's computational speed, as the access speed of the memory unit is much lower than the computation speed of the processing unit. Furthermore, this exchange of data between the processing unit and the memory unit consumes a significant amount of energy, significantly reducing computational efficiency.

[0003] Neuromorphic computing is an emerging computing paradigm that simulates the neuronal behavior and synaptic plasticity of the human brain at the hardware level to achieve efficient data processing similar to that of the human brain. Synapses are the basic units for transmitting signals between neurons. The connection strength between neurons changes over time, and the connection strength of neurons can be affected by adjusting the weight of the synapse. In spike timing-dependent plasticity (STDP), the synaptic weight changes with the time difference between the pulse fired by the preceding neuron and the pulse fired by the following neuron. The LIF model is used to simulate the electrical activity of biological neurons, describing how the membrane potential of neurons changes with the accumulation of input signals, and ultimately produces action. Summary of the Invention

[0004] In response to the technical problems existing in the prior art, the present application proposes a neural network circuit, comprising: a plurality of neuron circuits, and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synapse circuit at least comprises: a first transistor (101), a control electrode of which is configured to receive a reset signal, and a first electrode of which is configured to receive a first voltage; a weight unit (103), a first end of which is coupled to a first power supply, a second end of which is coupled to a second electrode of the first transistor (101), and is configured to receive the first voltage when the first transistor (101) is turned on, and the weight unit (103) at least comprises a ferroelectric tunnel junction; a second transistor (105) , its control electrode is configured to receive a control signal from the presynaptic neuron circuit, and its first electrode is coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103); a third transistor (107), its control electrode is coupled to the second electrode of the second transistor (105), its first electrode is coupled to the postsynaptic neuron circuit, and its second electrode is coupled to ground, and is configured to control the connection state between the electronic synaptic circuit and the postsynaptic neuron circuit under the action of a second voltage; a fourth transistor (109), its first electrode is configured to receive an input signal from the presynaptic neuron circuit, its control electrode is configured to receive a feedback signal from the postsynaptic neuron circuit, and its second electrode is coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103).

[0005] In particular, the neural network circuit, wherein the post-synaptic neuron circuit at least comprises: a comparator (301), a negative input terminal of which is coupled to the first electrode of the third transistor (107) of the electronic synaptic circuit, a positive input terminal of the comparator configured to receive a post-synaptic neuron threshold voltage, and an output terminal of the comparator (301) configured to output a start signal; a resistor (303), which is coupled between the negative input terminal of the comparator (301) and a second power supply, wherein the second power supply voltage is higher than the first power supply voltage; a capacitor (307), which is coupled between the negative input terminal of the comparator (301) and ground; and a fifth transistor (305) and an inverter (306), wherein the input terminal of the inverter (306) is coupled to the output terminal of the comparator (301), the control electrode of the fifth transistor (305) is coupled to the output terminal of the inverter (306), the first electrode of the fifth transistor (305) is coupled to the negative input terminal of the comparator (301), and the second electrode of the fifth transistor (305) is coupled to the second power supply.

[0006] In particular, the neural network circuit, wherein the post-synaptic neuron circuit further comprises a delay unit (309), the delay unit being coupled between the output terminal of the comparator (301) and the control electrode of the fourth transistor (109) of the electronic synaptic circuit, and being configured to receive the start signal output by the comparator (301), delay the start signal by a fixed time interval, and then output a feedback signal, wherein the fixed time interval of the delay unit is equal to the duration of the first half cycle of the input signal, and the second transistor (105) and the fourth transistor (109) are not turned on at the same time.

[0007] In particular, the neural network circuit further includes, when the first transistor (101) is turned off and the feedback signal is at a high level, the fourth transistor (109) is turned on, and the second end of the ferroelectric tunnel junction receives the input signal.

[0008] In particular, the neural network circuit, wherein the input signal, in the first half of the cycle, its amplitude gradually increases from the first preset value to the second preset value and directly jumps down to the third preset value; and, in the second half of the cycle, gradually increases from the third preset value to a fourth preset value lower than the first preset value, and the third preset value is lower than the first voltage; wherein the first preset value is higher than the voltage of the first power supply, and the third and fourth preset values ​​are lower than the voltage of the first power supply.

[0009] In particular, in the neural network circuit, the control signal and the input signal are sent simultaneously by the presynaptic neuron circuit.

[0010] The present application also provides an electronic synaptic circuit configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synaptic circuit at least comprises: a first transistor (101), a control electrode of which is configured to receive a reset signal and a first electrode of which is configured to receive a first voltage; a weight unit (103), a first end of which is coupled to a first power supply and a second end of which is coupled to a second electrode of the first transistor (101), and configured to receive the first voltage when the first transistor (101) is turned on, the weight unit (103) at least comprising a ferroelectric tunnel junction; a second transistor (105), a control electrode of which is configured to receive a control signal from the presynaptic neuron circuit , a first electrode of which is coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103); a third transistor (107), a control electrode of which is coupled to the second electrode of the second transistor (105), a first electrode of which is coupled to the post-synaptic neuron circuit, and a second electrode of which is coupled to ground, and is configured to control the connection state of the electronic synaptic circuit and the post-synaptic neuron circuit under the action of a second voltage; a fourth transistor (109), a first electrode of which is configured to receive an input signal from the pre-synaptic neuron circuit, a control electrode of which is configured to receive a feedback signal from the post-synaptic neuron circuit, and a second electrode of which is coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103).

[0011] In particular, the electronic synapse circuit further comprises: when the first transistor (101) is turned off and the feedback signal is at a high level, the fourth transistor (109) is turned on, and the second end of the ferroelectric tunnel junction receives the input signal.

[0012] The present application also provides an electronic device comprising a neural network circuit as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0014] Figure 1 is a schematic diagram of a neural network circuit model according to an embodiment of the present application;

[0015] Figure 2 FIG2 is a schematic diagram of an electronic synaptic circuit and a portion of a postsynaptic neuron circuit according to one embodiment of the present application;

[0016] Figure 3 Shown Figure 2 a timing diagram of part of the operation of the circuit shown; and

[0017] Figure 4Shown is a curve showing the change in conductivity of a ferroelectric tunnel junction over time in an electronic synapse circuit according to one embodiment of the present application. DETAILED DESCRIPTION

[0018] In the detailed description of the following embodiments, reference will be made to the accompanying drawings that form a part of this application. The accompanying drawings illustrate specific embodiments that can implement this application by way of example. The illustrative embodiments are not intended to be exhaustive of all embodiments according to this application. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of this application. Therefore, the following detailed description is not restrictive, and the scope of this application is defined by the appended claims.

[0019] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the communication between unconnected elements. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of output terminals provided, and is not intended to limit the communication between the two elements to only the signals shown in the figure.

[0020] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0021] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low-temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carriers are electrons or holes, it can be divided into N-type transistors and P-type transistors. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or collector of the bipolar transistor.

[0022] In the following detailed description, the effective level can be a high level or a low level depending on the circuit. In the following embodiments, for ease of understanding, the high level is described as the effective level and the low level is described as the ineffective level.

[0023] In the following detailed description, for ease of understanding, a level with a potential of 0 is described as a low level. Hereinafter, the ground potential and the low level are the same.

[0024] Neuromorphic computing architectures show much lower power consumption than traditional processors due to the integration of non-volatile memory and analog / digital processing circuits, as well as the ability to dynamically learn under complex data environments.

[0025] With the advancement of semiconductor device technology, novel devices with adjustable resistance and non-volatile properties have been proposed, such as the ferroelectric tunnel junction (FTJ). The FTJ is characterized by a ferroelectric layer sandwiched between two electrodes. Since the polarization direction of the ferroelectric layer is affected by the voltage difference across the electrodes, applying different voltage amplitudes and durations to the electrodes influences the charge distribution across the ferroelectric layer, thereby changing the tunneling resistance and enabling information storage. As a structure consisting of two conductors and a dielectric layer, the FTJ inevitably has parasitic capacitance. Tunnel junctions made with different processes and materials have varying tunneling resistance and parasitic capacitance, and the FTJ's charge and discharge speeds and power consumption also vary. In practical applications, the FTJ can function as a parallel structure of a resistor and capacitor, and the impact of the FTJ's parasitic capacitance cannot be ignored.

[0026] The proposed FTJ-based electronic synaptic circuit and neural network circuit integrates the LIF function of neurons and the STDP function of synapses, which has positive significance for promoting the development of neuromorphic circuits. In particular, the application utilizes the FTJ parasitic capacitance to achieve control of the synaptic circuit, making the circuit design more concise.

[0027] Figure 1 This is a schematic diagram of a neural network circuit model according to one embodiment of the present application. A neural network includes multiple nodes, also known as neurons, and two neurons can be connected through electronic synapses. Synapses transmit electrical signals from a presynaptic neuron to a postsynaptic neuron. The transmission path depends on the weights of the electronic synapses between neurons. A higher weight indicates a closer connection between the two neurons.

[0028] like Figure 1As shown, according to one embodiment of the present application, a neuron in a neural network can be connected to multiple neurons, and two neurons are connected and transmit signals through electronic synapses. The calculations that need to be completed can be converted into multiple loop calculations in the neural network, and a single calculation process can be converted into a process of transmitting signals in the neural network starting from the initial neuron set by the user, passing through multiple neurons and electronic synapses, and finally transmitting to the target neuron set by the user. The neural network automatically adjusts the weights between neurons based on a preset learning mechanism, thereby realizing the calculation process of different problems.

[0029] Each electronic synapse can receive signals from at least one neuron (referred to as a presynaptic neuron with respect to the synapse), and / or can send signals to at least one neuron (referred to as a postsynaptic neuron with respect to the synapse).

[0030] Figure 2 Shown is a schematic diagram of an electronic synaptic circuit and a portion of a postsynaptic neuron circuit according to one embodiment of the present application.

[0031] According to one embodiment, a neural network circuit includes an electronic synaptic circuit 10 and a postsynaptic neuron circuit 30. The electronic synaptic circuit 10 is coupled to its postsynaptic neuron circuit 30, and the electronic synaptic circuit 10 is also coupled to a presynaptic neuron circuit (not shown). In one embodiment, the presynaptic neuron circuit can have a circuit structure similar to that of the postsynaptic neuron circuit 30.

[0032] According to one embodiment, a postsynaptic neuron circuit 30 can be coupled to at least one presynaptic neuron circuit using the electronic synapse circuit 10. The electronic synapse circuit 10 can transmit electrical signals between the presynaptic neuron circuit and the postsynaptic neuron circuit 30. One postsynaptic neuron circuit 30 can be coupled to at least one electronic synapse circuit 10.

[0033] According to one embodiment, the electronic synapse circuit 10 receives a control signal LIF WL and an input signal STDP WL from a pre-synaptic neuron circuit, and receives a feedback signal STDP BL from a post-synaptic neuron circuit 30 .

[0034] According to one embodiment, the input signal STDP WL is a signal whose amplitude varies over time. In the first half of the cycle, the amplitude of the input signal STDP WL gradually increases from a first preset value to a second preset value and then directly drops to a third preset value. In the second half of the cycle, the amplitude gradually increases from the third preset value to a fourth preset value. The first preset value is higher than both the third and fourth preset values. The first and second half of the cycle of the input signal STDP WL have equal durations.

[0035] According to one embodiment, the control signal LIF WL is a pulse signal, and the presynaptic neuron circuit sends the control signal LIF WL and the input signal STDP WL simultaneously.

[0036] According to one embodiment of the present application, the input signal STDP WL transmitted by each presynaptic neuron circuit has the same period and waveform, but is transmitted at different times. The postsynaptic neuron circuit 30 simultaneously transmits the feedback signal STDP BL to each of its coupled electronic synaptic circuits. At this time, the input signal STDP WL received by each electronic synaptic circuit has a different value. Therefore, the feedback signal STDP BL determines the timing of the electronic synaptic circuit's weight update.

[0037] According to one embodiment, the electronic synapse circuit 10 includes an N-type transistor 101 and a weight unit 103 connected in series. A first terminal of the weight unit 103 receives a voltage V_PL, and a second terminal of the weight unit 103 is coupled to a second terminal of the transistor 101. A first terminal of the transistor 101 is configured to receive a voltage V_RST, and a control terminal of the transistor 101 is configured to receive a reset signal EN_RST.

[0038] According to one embodiment, the reset signal EN_RST is a pulse signal. When the reset signal EN_RST reaches a high level, the transistor 101 is turned on, so that the potential of the second electrode (point X) of the transistor 101 reaches the level of V_RST.

[0039] According to one embodiment, the voltage V_PL is higher than the voltage V_RST. The first preset value of the amplitude of the input signal STDP WL is higher than the voltage V_PL, the third preset value is lower than the voltage V_RST, and the fourth preset value of the amplitude of the input signal STDP WL is lower than the voltage V_PL and close to the voltage V_RST.

[0040] According to one embodiment, weight unit 103 includes at least a ferroelectric tunnel junction FTJ01. A first terminal of FTJ01 receives a voltage V_PL, and a second terminal is coupled to the second electrode of transistor 101. In one embodiment, the voltage at the first terminal of FTJ01 is higher than the voltage at the second terminal, and the voltage difference across FTJ01 is positive. Under positive voltage, the tunneling resistance of FTJ01 decreases, while its conductance increases. In another embodiment, the voltage at the first terminal of FTJ01 is lower than the voltage at the second terminal, and the voltage difference across FTJ01 is negative. Under negative voltage, the tunneling resistance of FTJ01 increases, while its conductance decreases. The weight of electronic synapse circuit 10 is altered by changing the tunneling resistance of the ferroelectric tunnel junction.

[0041] According to one embodiment, when the reset signal EN_RST is at a low level, transistor 101 is turned off. Under the influence of the voltage difference, the parasitic capacitance of FTJ01 is charged through the tunneling resistance within the ferroelectric tunneling junction FTJ01, causing the potential at point X to gradually rise and approach the voltage level of voltage V_PL. The different tunneling resistances of the ferroelectric tunneling junction FTJ01 result in different charging and discharging rates of the parasitic capacitance. After the same charging time, the charging state of the parasitic capacitance within the ferroelectric tunneling junction FTJ01 also varies.

[0042] According to one embodiment, the electronic synapse circuit 10 may further include a transistor 105 and a transistor 107. A first electrode of transistor 105 is coupled between the second electrode of transistor 101 and the second end of the weight unit 103 (point X). Its control electrode is configured to receive the control signal LIF WL, and its second electrode is coupled to the control electrode of transistor 107. A first electrode of transistor 107 is coupled to the postsynaptic neuron circuit 30, and a second electrode is coupled to ground. In one embodiment, when the control signal LIF WL reaches a high level, transistor 105 turns on, causing the potential at the control electrode of transistor 107 to reach the potential at point X, thereby driving transistor 107 to turn on. The postsynaptic neuron circuit 30 discharges through transistor 107.

[0043] According to one embodiment, the electronic synapse circuit 10 further includes a transistor 109. A first electrode of the transistor 109 is configured to receive an input signal STDP WL, a second electrode of the transistor 109 is coupled between the second electrode of the transistor 101 and the second terminal of the weight unit 103, and a control electrode of the transistor 109 is configured to receive a feedback signal STDP BL from the post-synaptic neuron circuit 30. The transistor 109 is configured to pass the value of the input signal STDP WL under the control of the feedback signal STDP BL.

[0044] In one embodiment, when transistor 109 is turned on, the potential at point X reaches the potential level of input signal STDP WL at the time of turn-on. Each presynaptic neuron circuit transmits input signal STDP WL at different times. When transistor 109 is turned on, the input signal STDP WL received by each electronic synapse circuit is at a different value. This results in different voltages across the ferroelectric tunnel junction FTJ01, thereby changing the tunneling resistance of the ferroelectric tunnel junction FTJ01 and updating the weights of the electronic synapse circuit, thus implementing the STDP function of the synapse. The speed of the change in the FTJ tunneling resistance is affected by the voltage across the junction.

[0045] In one embodiment, when the input signal STDP WL is in the first half of its cycle, the potential level at the second end of the ferroelectric tunnel junction FTJ01 is higher than the potential level of the voltage V_PL. The ferroelectric tunnel junction FTJ01 is subjected to a negative voltage, and the input signal STDP WL values ​​received by each electronic synapse circuit are different, resulting in different voltage values ​​across the ferroelectric tunnel junction FTJ01. The larger the value of the input signal STDP WL, the higher the voltage value at the second end of the ferroelectric tunnel junction FTJ01, and the smaller the change in the conductance of the ferroelectric tunnel junction FTJ01 as the conductance decreases.

[0046] In one embodiment, when the input signal STDP WL is in the second half of its cycle, the potential at the second end of the ferroelectric tunnel junction FTJ01 is lower than the potential of the voltage V_PL. The ferroelectric tunnel junction FTJ01 is subjected to a positive voltage, and the different electronic synapse circuits receive the input signal STDP WL at different times, resulting in different voltage values ​​across the ferroelectric tunnel junction FTJ01. The smaller the input signal STDP WL, the lower the voltage value at the second end of the ferroelectric tunnel junction FTJ01, and the greater the change in the conductance of the ferroelectric tunnel junction FTJ01 as the conductance increases.

[0047] According to one embodiment, the post-synaptic neuron circuit 30 includes a comparator 301. The comparator 301 has a positive input terminal receiving a post-synaptic neuron threshold voltage Vth, and a negative input terminal coupled to the electronic synapse circuit 10 (eg, coupled to the transistor 107).

[0048] According to one embodiment, the postsynaptic neuron circuit 30 further includes a capacitor 307 coupled between the negative input terminal of the comparator 301 and ground. Capacitor 307 is configured to simulate the membrane potential of a neuron. When the control signal LIFWL in the electronic synapse circuit 10 reaches a high level, transistor 105 turns on and transistor 101 turns off. Simultaneously, the voltage at the gate of transistor 107 reaches the voltage level at point X, driving transistor 107 to conduct. Capacitor 307 in the postsynaptic neuron circuit 30 discharges charge through the path formed by transistor 107, causing the potential Vmem to fall below the voltage level Vth. Comparator 301 then outputs a high-level start signal Fire, implementing the LIF function of the postsynaptic neuron circuit. In the electronic synapse circuit 10, the tunneling resistance of the ferroelectric tunnel junction FTJ01 varies, and the potential level at point X also varies. This results in different currents flowing through transistor 107 and different rates of charge discharge from capacitor 307.

[0049] According to one embodiment, the postsynaptic neuron circuit 30 further includes a transistor 305 and an inverter 306. The input of the inverter 306 is coupled to the output of the comparator 301. The control electrode of the transistor 305 is coupled to the output of the inverter 306, the first electrode of the transistor 305 is coupled to the negative input of the comparator 301, and the second electrode of the transistor 305 is configured to be coupled to the power supply VDD. The transistor 305 can be a P-type transistor. When the electronic synapse circuit 10 discharges the postsynaptic neuron circuit 30, and after the discharge, Vmem falls below the voltage Vth, the start signal Fire output by the comparator 301 is at a high level, turning on the transistor 305, charging the capacitor 307 through the transistor 305, and resetting the potential Vmem at the negative input of the comparator to the power supply VDD level.

[0050] According to one embodiment, the postsynaptic neuron circuit 30 may further include a resistor 303 coupled between the power supply VDD and the negative input terminal of the comparator 301. When the electronic synaptic circuit 10 discharges the postsynaptic neuron circuit 30 and the discharge fails to reduce Vmem to a voltage lower than Vth, the power supply VDD slowly charges the capacitor 307 through the resistor 303, thereby extending the time it takes for the membrane potential to return to the VDD level and preventing the postsynaptic neuron circuit from being unable to generate the start signal Fire.

[0051] According to one embodiment, the post-synaptic neuron circuit 30 may further include a delay unit 309 configured to ensure a certain time interval t between the high-level pulse of the feedback signal STDP BL and the high-level pulse of the control signal LIF WL output by the pre-synaptic neuron circuit. This ensures that the input signal STDP WL sent by the pre-synaptic neuron circuit, which triggers the post-synaptic neuron circuit 30 to send the start signal Fire, can jump to a third preset value, and prevents transistors 105 and 109 in the electronic synapse circuit from being turned on simultaneously. In one embodiment, the time interval t is equal to the first half cycle of the input signal STDP WL.

[0052] According to one embodiment, when the potential Vmem at the negative input terminal of the comparator 301 is higher than the voltage Vth, the start signal Fire output by the comparator 301 is at a low level, the feedback signal STDP BL output by the delay 309 is also at a low level, and the transistor 109 in the electronic synapse circuit 10 is turned off. When the potential Vmem at the negative input terminal of the comparator is lower than the voltage Vth, the start signal Fire output by the comparator 301 is at a high level. After a waiting time interval t, the signal STDP BL output by the delay 309 is also at a high level. Under the control of the signal STDP BL, the transistor 109 in the electronic synapse circuit 10 is turned on.

[0053] According to one embodiment, a postsynaptic neuron circuit is coupled to multiple electronic synaptic circuits. When any of these electronic synaptic circuits is able to reduce the potential Vmem to a level below the voltage Vth, the postsynaptic neuron circuit will send a high-level start signal Fire, and all electronic synaptic circuits coupled to it will receive a feedback signal STDP BL. At this time, the weights of all electronic synaptic circuits coupled to it will change. Because different presynaptic neuron circuits send control signals and input signals at different times, when the postsynaptic neuron circuit sends the feedback signal STDP BL, the value of the input signal STDP WL received by the electronic synaptic circuit is also different, resulting in different resistance values ​​of the tunneling resistance of the FTJ in each electronic synaptic circuit, thereby changing the weights written into the electronic synaptic circuit.

[0054] According to an embodiment of the present application, device parameters such as gate length, doping concentration and gate insulation layer thickness of transistors 101 , 105 , 107 , 109 and 305 are not restricted and can be adjusted according to actual needs.

[0055] In one embodiment, the power source VDD is higher than the voltage V_PL.

[0056] In one embodiment of the present application, the material and thickness of the ferroelectric layer of the ferroelectric tunnel junction FTJ01 can be adjusted according to actual needs.

[0057] In one embodiment of the present application, the pulse shapes and sizes of the control signal LIF WL, the input signal STDP WL, and the feedback signal can be adjusted according to actual needs.

[0058] Figure 3 Shown Figure 2 Part of the working timing diagram of the circuit shown. The whole process is divided into four stages.

[0059] (1) Reset phase (not shown).

[0060] In the reset phase, the reset signal EN_RST is a high-level pulse signal, the transistor 101 is turned on, and the potential of the second electrode of the transistor 101 (point X) reaches the V_RST level. In this phase, the voltage across the weight circuit 103 is reset.

[0061] (2) Charging stage (not shown).

[0062] During this phase, transistors 101, 105, 107, and 109 in electronic synapse circuit 10 are all turned off, leaving point X floating. Voltage V_PL is higher than the potential level at point X. The parasitic capacitance within the ferroelectric tunnel junction is charged via the tunneling resistance, causing the potential at point X to gradually rise and approach the V_PL level. In one embodiment, the charging time for each electronic synapse circuit is the same. However, the charging speed of the ferroelectric tunnel junctions in the electronic synapse circuits varies due to the different tunneling resistance values, ultimately resulting in different potential levels at point X in each electronic synapse circuit.

[0063] (3)LIF stage.

[0064] In the LIF stage, each electronic synapse circuit receives the control signal LIF WL and the input signal STDP WL sent by the presynaptic neuron circuit coupled to it. Each electronic synapse circuit discharges the capacitor 307 in the postsynaptic neuron circuit 30 until the potential level of Vmem is lower than the potential level of the voltage Vth, triggering the postsynaptic neuron circuit 30 to send the start signal Fire.

[0065] like Figure 3 As shown, at time t1, a presynaptic neuron circuit sends a control signal LIFWL1 and an input signal STDP WL1 to the electronic synapse circuit, triggering the discharge function of the electronic synapse circuit. However, the discharge does not reduce the potential of the Vmem point to a level lower than the voltage Vth. Therefore, the electronic synapse circuit does not receive the feedback signal STDP BL sent by the postsynaptic neuron.

[0066] At time t2, the other presynaptic neuron sends a control signal (LIF WL2) and an input signal (STDP WL2) to the electronic synaptic circuit, causing the potential at point Vmem to drop below voltage Vth. This triggers the postsynaptic neuron to send a start signal (Fire). After waiting for a time interval (t), at time t3, the postsynaptic neuron sends a feedback signal (STDP BL).

[0067] (4) STDP stage.

[0068] During this phase, each electronic synapse circuit coupled to the post-synaptic neuron circuit 30 receives the feedback signal STDP BL. When the electronic synapse circuit that triggers the post-synaptic neuron circuit 30 to send the start signal Fire receives the feedback signal STDP BL from the post-synaptic neuron circuit 30, the received input signal STDP WL jumps to a third preset value. Compared to other electronic synapse circuits, the voltage applied to the FTJ across this electronic synapse circuit is the largest, the change in the FTJ's conductance as it increases is the largest, and the change in the weight of this electronic synapse circuit as it increases is also the largest.

[0069] like Figure 3As shown, V0 is the first preset value of the input signal STDP WL, V1 is the second preset value of the input signal STDP WL, V2 is the third preset value of the input signal STDP WL, and V3 is the fourth preset value of the input signal STDP WL.

[0070] When the duration of the voltage applied to the FTJ is equal, the conductance increases faster when a positive voltage is applied to the FTJ and the voltage value is larger, and the conductance decreases faster when a negative voltage is applied to the FTJ and the voltage value is larger. In one embodiment of the present application, an electronic synapse circuit that triggers the postsynaptic neuron circuit to send a start signal Fire waits for a fixed time interval t and then receives a feedback signal STDP BL sent by the postsynaptic neuron circuit. At this time, the value of the input signal STDP WL sent by the presynaptic neuron circuit received by the electronic synapse circuit jumps to a third preset value. The voltage across the FTJ in the electronic synapse circuit is positive. Compared with other electronic synapse circuits coupled to the postsynaptic neuron circuit, the positive voltage across the FTJ of the electronic synapse circuit is the largest. Therefore, the change in conductance when it increases is also the largest, and the change in the weight of the electronic synapse circuit when it increases is also the largest.

[0071] Figure 4 FIG. 1 is a curve showing the change in conductivity of a ferroelectric tunnel junction in an electronic synaptic circuit according to an embodiment of the present application over time. Figure 4 As shown, the origin is preset to the moment when the pulse peak of the postsynaptic neuron's start signal Fire coincides with the pulse peak of the presynaptic neuron's control signal LIF WL. The horizontal axis represents the time difference between the moment the postsynaptic neuron sends the start signal Fire and the moment the presynaptic neuron sends the control signal LIF WL, and the vertical axis represents the conductivity change rate of the ferroelectric tunnel junction FTJ01 in the electronic synaptic circuit. To make the curve more intuitive, the conductivity change rate curve is normalized based on the time difference.

[0072] According to one embodiment, Figure 4In the example, when the control signal LIF WL from the presynaptic neuron arrives before the start signal Fire from the postsynaptic neuron, the time difference is positive. During this period, the feedback signal STDP BL received by the electronic synaptic circuit is in the second half of the cycle, and FTJ01 is subjected to a positive voltage. The rate of change of FTJ01's conductance and the corresponding weight of the electronic synaptic circuit decrease as the time difference increases. When the control signal LIF WL from the presynaptic neuron arrives after the start signal Fire from the postsynaptic neuron, the time difference is negative. During this period, the input signal STDP WL received by the electronic synaptic circuit is in the first half of the cycle, and FTJ01 is subjected to a negative voltage. The rate of change of FTJ01's conductance and the corresponding weight of the electronic synaptic circuit decrease as the time difference increases. Of course, different input and control signals can also be used based on the STDP mechanism curve of different electronic synapses.

[0073] This application utilizes the non-volatile properties of FTJs and applies them to electronic synapses. By adjusting the magnitude and direction of the voltage difference applied across the FTJ, the FTJ tunneling resistance is set, thereby setting the specific weight of the synapse. This simplifies circuit design while enabling neuromorphic circuits to combine LIF functionality with STDP mechanisms. Furthermore, by taking into account the parasitic capacitance of the FTJ itself, this approach offers the advantages of low power consumption and improved operational efficiency. By applying this approach to neuromorphic computing network design, it is possible to achieve neuromorphic computing with low power consumption and high computing performance.

[0074] During the calculation and optimization process, the circuit does not need to store the calculated weights and intermediate values ​​of other input signals, nor does it need to call the intermediate values ​​again before the next calculation, which reduces the number of times the circuit is used, improves the calculation speed, and reduces circuit power consumption.

[0075] The electronic synaptic circuit provided in this application uses fewer transistors and can greatly reduce chip area when applied to neural networks.

[0076] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A neural network circuit comprising: a plurality of neuron circuits, and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive feedback signals from a postsynaptic neuron circuit; Wherein, the electronic synapse circuit at least includes: A first transistor (101), a control electrode of which is configured to receive a reset signal, and a first electrode of which is configured to receive a first voltage; A weight unit (103), a first end of which is coupled to a first power source, a second end of which is coupled to the second electrode of the first transistor (101), and configured to receive the first voltage when the first transistor (101) is turned on, the weight unit (103) comprising at least a ferroelectric tunnel junction; A second transistor (105), whose control electrode is configured to receive a control signal from the presynaptic neuron circuit, and whose first electrode is coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103); a third transistor (107), a control electrode of which is coupled to the second electrode of the second transistor (105), a first electrode of which is coupled to the post-synaptic neuron circuit, and a second electrode of which is coupled to ground, and is configured to control the connection state between the electronic synapse circuit and the post-synaptic neuron circuit under the action of a second voltage; a fourth transistor (109), a first electrode of which is configured to receive an input signal from the presynaptic neuron circuit, a control electrode of which is configured to receive a feedback signal from the postsynaptic neuron circuit, and a second electrode of which is coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103); The postsynaptic neuron circuit comprises, a comparator (301), wherein a negative input terminal of the comparator is coupled to a first electrode of a third transistor (107) of the electronic synapse circuit, a positive input terminal of the comparator is configured to receive a post-synaptic neuron threshold voltage, and an output terminal of the comparator (301) is configured to output a start signal; and A fifth transistor (305) and an inverter (306), wherein the input terminal of the inverter (306) is coupled to the output terminal of the comparator (301), the control terminal of the fifth transistor (305) is coupled to the output terminal of the inverter (306), the first terminal of the fifth transistor (305) is coupled to the negative input terminal of the comparator (301), and the second terminal of the fifth transistor (305) is coupled to a second power supply.

2. The neural network circuit according to claim 1, wherein: The postsynaptic neuron circuit further comprises at least: a resistor (303) coupled between the negative input terminal of the comparator (301) and a second power supply, wherein the second power supply voltage is higher than the first power supply voltage; A capacitor (307) is coupled between the negative input terminal of the comparator (301) and ground.

3. The neural network circuit according to claim 2, wherein the post-synaptic neuron circuit further comprises a delay unit (309), the delay unit (309) being coupled between the output terminal of the comparator (301) and the control electrode of the fourth transistor (109) of the electronic synaptic circuit, and configured to receive the start signal output by the comparator (301), delay the start signal by a fixed time interval, and then output a feedback signal, wherein the fixed time interval of the delay unit (309) is equal to the duration of the first half cycle of the input signal, and the delay unit (309) is configured to prevent the second transistor (105) and the fourth transistor (109) from being turned on at the same time.

4. The neural network circuit as claimed in claim 3 further includes, when the first transistor (101) is turned off and the feedback signal is at a high level, the fourth transistor (109) is turned on, and the second end of the ferroelectric tunnel junction receives the input signal.

5. The neural network circuit according to claim 4, wherein: The input signal, in the first half cycle, has an amplitude that gradually increases from a first preset value to a second preset value and then directly jumps down to a third preset value; and, in the second half cycle, gradually increases from the third preset value to a fourth preset value that is lower than the first preset value, and the third preset value is lower than the first voltage; wherein, The first preset value is higher than the voltage of the first power source, and the third and fourth preset values ​​are lower than the voltage of the first power source.

6. The neural network circuit according to claim 5, wherein: The control signal and the input signal are sent simultaneously by the presynaptic neuron circuit.

7. An electronic synaptic circuit configured to receive input and control signals from a presynaptic neuron circuit and receive feedback signals from a postsynaptic neuron circuit; in, The electronic synapse circuit comprises at least: A first transistor (101), a control electrode of which is configured to receive a reset signal, and a first electrode of which is configured to receive a first voltage; A weight unit (103), a first end of which is coupled to a first power source, a second end of which is coupled to the second electrode of the first transistor (101), and configured to receive the first voltage when the first transistor (101) is turned on, the weight unit (103) comprising at least a ferroelectric tunnel junction; A second transistor (105), whose control electrode is configured to receive a control signal from the presynaptic neuron circuit, and whose first electrode is coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103); a third transistor (107), a control electrode of which is coupled to the second electrode of the second transistor (105), a first electrode of which is coupled to the post-synaptic neuron circuit, and a second electrode of which is coupled to ground, and is configured to control the connection state between the electronic synapse circuit and the post-synaptic neuron circuit under the action of a second voltage; A fourth transistor (109) has a first electrode configured to receive an input signal from the presynaptic neuron circuit, a control electrode configured to receive a feedback signal from the postsynaptic neuron circuit, and a second electrode coupled to the second electrode of the first transistor (101) and the second end of the weight unit (103).

8. The electronic synapse circuit according to claim 7, further comprising: when the first transistor (101) is turned off and the feedback signal is at a high level, the fourth transistor (109) is turned on, and the second end of the ferroelectric tunnel junction receives the input signal.

9. An electronic device comprising the neural network circuit according to any one of claims 1 to 6.

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