Method, electronic device and storage medium for designing simulation logic system

Abstract

The present application provides a method for simulating a logic system design on a hardware simulation tool, including: compiling the logic system design to respectively generate a first configuration file and a second configuration file; configuring first hardware resources of the hardware simulation tool according to the first configuration file to simulate the logic system design; obtaining a first snapshot of the simulation of the logic system design in a first clock cycle; configuring second hardware resources of the hardware simulation tool according to the second configuration file to debug the logic system design; and restoring the logic system design to the first clock cycle on the second hardware resources according to the first snapshot.

Description

Technical Field

[0001] This application relates to the field of chip verification technologies, and in particular, to a method for designing a simulation logic system, an electronic device, and a storage medium. Background Art

[0002] Hardware simulation tools (e.g., prototype verification boards or hardware emulators) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, a design for an Application-Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a specific application. Therefore, the logic system design being tested in the simulation tool can also be referred to as the Design Under Test (DUT). The simulation tool can simulate the DUT through one or more configurable components (e.g., Field Programmable Gate Arrays (FPGAs)), including performing various operations of the DUT, thereby testing and verifying the functions of each module of the DUT before manufacturing. By externally connecting various peripheral daughter cards to the simulation tool, the operation effect of the DUT running with various peripherals as a complete system can also be tested.

[0003] Hardware simulation tools can include, for example, prototype verification boards and hardware emulators. Generally, prototype verification boards focus on the overall operation of the electronic system, emphasizing the running speed and usually not having debugging capabilities. While hardware emulators focus on the simulation of the chip design itself, emphasizing debugging capabilities, but with a slow running speed. Summary of the Invention

[0004] A first aspect of this application provides a method for simulating a logic system design on a hardware simulation tool, including: compiling the logic system design to generate a first configuration file and a second configuration file respectively; configuring a first hardware resource of the hardware simulation tool according to the first configuration file to simulate the logic system design; obtaining a first snapshot of the simulation of the logic system design in a first clock cycle; configuring a second hardware resource of the hardware simulation tool according to the second configuration file to debug the logic system design; and restoring the logic system design to the first clock cycle on the second hardware resource according to the first snapshot.

[0005] A second aspect of this application provides an electronic device, including: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method as described in the first aspect.

[0006] A third aspect of the present application provides a non-transitory computer-readable storage medium storing a set of instructions for a computer, which when executed cause the computer to perform the method as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following description are only embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0008] Figure 1 FIG. shows a schematic structural diagram of an exemplary host according to an embodiment of the present application.

[0009] Figure 2 FIG. shows a schematic diagram of a simulation system according to an embodiment of the present application.

[0010] Figure 3 FIG. shows a schematic diagram of the process of generating a configuration file according to an embodiment of the present application.

[0011] Figure 4 FIG. shows a schematic diagram of configuring hardware simulation resources according to an embodiment of the present application.

[0012] Figure 5 FIG. shows a schematic diagram of the process of debugging a logic system design according to an embodiment of the present application.

[0013] Figure 6 FIG. shows a schematic diagram of another process of debugging a logic system design according to an embodiment of the present application.

[0014] Figure 7 FIG. shows a flowchart of a method for simulating a logic system design on a hardware simulation tool according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] In order to make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the present application in detail with reference to specific embodiments and the accompanying drawings.

[0016] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0017] As mentioned above, prototype verification boards and hardware emulators are both hardware simulation tools. They are similar at the hardware level. However, in actual use, prototype verification boards can continuously provide prototype simulation at a high running speed, but errors that occur during the prototype simulation process cannot be recorded and restored, let alone debugged. Hardware emulators can use triggers and other means to record and restore simulation errors, but the running speed is very slow, and the hardware emulator itself is very expensive.

[0018] In view of the above problems, the inventor of the present application attempts to provide a hardware simulation tool with both prototype verification capability and debugging capability. Usually, prototype verification and debugging cannot be performed simultaneously on a hardware device. At the same time, the hardware resources required for the prototype verification function are relatively few, while the hardware resources required for the debugging function are relatively many. If the hardware simulation tool provided by the present application uses the same hardware resources in two modes, it will cause a waste of hardware resources and greatly reduce the efficiency of the prototype verification mode. Therefore, how to ensure the overall operating speed of the hardware simulation tool as much as possible while supporting the prototype verification capability and the hardware simulation capability is a technical problem to be solved urgently.

[0019] In view of this, an embodiment of the present application provides a method for simulating a logic system design on a hardware simulation tool, which effectively improves the overall efficiency of the hardware simulation tool by providing different hardware resources to different operating modes of the hardware simulation tool.

[0020] Figure 1 FIG. 1 shows a schematic diagram of the structure of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other through the bus 110 in communication with each other inside the electronic device.

[0021] The processor 102 can be a Central Processing Unit (CPU), an image processor, a Neural Network Processor (NPU), a microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits. The processor 102 can be used to execute functions related to the technologies described in this application. In some embodiments, the processor 102 can also include multiple processors integrated as a single logic component. As Figure 1 shown, the processor 102 can include multiple processors 102a, 102b, and 102c.

[0022] The memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design can be a computer program stored in the memory 104. As Figure 1 shown, the data stored in the memory can include program instructions (e.g., program instructions for implementing the method of positioning errors in this application) and data to be processed (e.g., the memory can store temporary code generated during the compilation process). The processor 102 can also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 can include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 can include a Random Access Memory (RAM), a Read Only Memory (ROM), an optical disc, a magnetic disk, a hard disk, a Solid State Drive (SSD), a flash memory, a memory stick, etc.

[0023] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0024] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as keyboards, mice, touch pads, touch screens, microphones, various sensors, etc. and output devices such as displays, speakers, vibrators, indicator lights, etc.

[0025] The bus 110 can be configured to transfer information among various components of the host 100, such as the processor 102, the memory 104, the network interface 106, and the peripheral interface 108, such as internal buses (e.g., processor-memory bus), external buses (USB ports, PCI-E bus), etc.

[0026] It should be noted that although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, the electronic device architecture may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above electronic device architecture may also only include the components necessary to implement the solution of the embodiments of the present application, and do not necessarily include all the components shown in the figure.

[0027] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0028] As Figure 2 shown, the simulation system 200 may include a simulation tool 202 and a host 100 connected to the simulation tool 202.

[0029] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 may be a prototype verification board or a hardware emulator. A design under test may include multiple modules. The design under test may be a combinational logic circuit, a sequential logic circuit, or a combination of the two. The simulation tool 202 may include one or more configurable circuits (e.g., FPGA) for simulating the design under test. It can be understood that although in Figure 2 the simulation tool 202 is only shown as a single circuit board, in fact, the simulation tool 202 may include multiple circuit boards (e.g., multiple prototype verification boards or dual-mode verification boards).

[0030] The simulation tool 202 may include an interface unit 2022 for communicatively coupling with the host 100 to enable communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 may include one or more interfaces with electrical connection capabilities. For example, the interface unit 2022 may include an RS232 interface, a USB interface, a LAN port, an optical fiber interface, an IEEE1394 (FireWire interface), etc. In some embodiments, the interface unit 2022 may be a wireless network interface. For example, the interface unit 2022 may be a WIFI interface, a Bluetooth interface, etc.

[0031] The host 100 can transmit the compiled DUT, debugging instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 can also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0032] The simulation tool 202 may further include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values generated by the design under test during the simulation process can be directly read by the host 100. It can be understood that the memory 2024 can also be independent of the simulation tool 202, for example, using an external memory.

[0033] The simulation tool 202 may further include an FPGA 2026 for hardware-implementing the logic system design onto the FPGA. It can be understood that the simulation tool 202 may include multiple FPGAs, which is only an example in the figure.

[0034] In addition to being connected to the host 100, the simulation tool 202 can also be connected to one or more daughter cards 204 via the interface unit 2022.

[0035] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that, before the chip is taped out, tries to restore the real usage scenario of the chip as much as possible to verify whether the chip functions accurately and completely. The daughter card 204 may include a memory daughter card (e.g., providing a DDR memory interface), a communication daughter card (e.g., providing multiple network interfaces or a wireless network card interface), etc.

[0036] The host 100 can be used to configure the simulation tool 202 to simulate a design under test. The design under test can be a complete logical system design or one or more modules of a complete logical system design. In some embodiments, the host 100 can be a virtual host in a cloud computing system. The logical system design (e.g., ASIC or System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). Configuring the simulation tool 202 by the host 100 may include configuring the simulation environment (e.g., the connection relationship between multiple simulation tools 202 or the connection relationship between the simulation tool and the daughter card), etc.

[0037] The host 100 can compile the logical system design in source code form into an executable file. From a design perspective, the logical system design can include the design under test and a test bench corresponding to the design under test. At this time, the compilation can cover the entire process from the source code to the executable file (e.g., a bit file).

[0038] From a comprehensive perspective, the logical system design can include synthesizable parts and non-synthesizable parts. The synthesizable parts usually correspond to the actual physical design (e.g., a chip), while the non-synthesizable parts usually include initialization modules, test benches, etc. The executable file formed after compiling the non-synthesizable parts can usually be run by the host 100. The synthesizable parts still need to be synthesized after compilation to form a bit file. The bit file can be used to configure the FPGA 2026 to operate according to the design requirements of the synthesizable parts.

[0039] The host 100 can also receive a request from the user to debug the design under test. As described above, the design under test can include one or more modules. The description of the design under test can be completed in a hardware description language. The host 100 can synthesize based on the description of the design under test to generate, for example, a gate-level circuit netlist (not shown) of the design under test. The gate-level circuit netlist of the design under test can be loaded into the simulation tool 202 for operation, and then a circuit structure corresponding to the design under test can be formed in the simulation tool 202. Therefore, the circuit structure of the design under test can be obtained according to the description, and correspondingly, the circuit structure of each block in the design under test can also be obtained similarly.

[0040] Figure 3 A schematic diagram showing the process of generating a configuration file according to an embodiment of the present application is shown.

[0041] As Figure 3 described, the host 100 can compile the logical system design 302 (hereinafter also simply referred to as the design 302) into a configuration file to configure the hardware simulation resources on the simulation tool 202. The simulation tool 202 can be the HuaPro P2E simulation tool produced by Xinhuazhang Co., Ltd. It can be understood that in some embodiments, the hardware simulation resources of the simulation tool 202 can include one or more FPGAs, and each FPGA can only simulate at least a part (e.g., one or more modules) of the logical system design. The simulation tool 202 can implement the prototype verification function and the debugging function.

[0042] For the same logical system design 302, due to different environment variables and whether there is a debugging function, the configuration file can include the configuration file 304 and the configuration file 306 generated by separate compilations. In some embodiments, the configuration files 304 and 306 can be binary files of the bit file type. Usually, one FPGA can correspond to one bit file, that is to say, the configuration file 304 or 306 can include one or more bit files.

[0043] The configuration file 304 corresponds to the prototype verification function, and the configuration file 306 corresponds to the debugging function.

[0044] The prototype verification function generally can refer to a simulation function without debugging capabilities. For example, a user can implement a logic system design (e.g., a chip design) onto a programmable logic device (e.g., FPGA 2026) of a hardware simulation tool 202, and connect one or more daughter cards (providing different peripheral functions) to the hardware simulation tool 202, thereby realizing a prototype of an entire electronic system. On this basis, by continuously providing test cases (e.g., providing stimuli) to the prototype of the electronic system, the simulation of various functions of the logic system design under the prototype of the electronic system is completed. During the simulation process, the values of the logic system design over multiple clock cycles can be saved. For example, the values of the key signals of the logic system design over multiple clock cycles can be saved. The key signals of the logic system design refer to a part of the signals that can be sufficient to restore the logic system design at the target clock cycle. Key signals generally can include at least part of the main inputs of the logic system design and the outputs of the registers. According to the values of the key signals and the description of the logic system design, the value of each signal of the logic system design can be calculated, and thus the logic system design can be restored to a given target clock cycle accordingly. For example, for a logic system design of C = A and B, A and B are key signals. Once the values of A and B are obtained, the value of C can be directly calculated according to the description of the logic system design (i.e., C = A and B).

[0045] However, the prototype verification function generally cannot stop or roll back to a given clock cycle according to the user's will at a specific clock cycle, nor can it view the waveform of a given signal within a given clock cycle range, etc.

[0046] In contrast to the prototype verification function, the debugging function can stop the simulation of the logic system design at a specific clock cycle or roll back to a given clock cycle according to the user's will, and can also view the waveform of a given signal within a given clock cycle range, etc., thereby allowing the user to find the root cause of the error in the logic system design.

[0047] The implementation of the debugging function often depends on simulation data. That is to say, the user needs to first perform a simulation on the logic system design and obtain simulation data (e.g., the values of the key signals of the logic system design over multiple given clock cycles), so as to rely on these simulation data to perform the debugging function during the debugging process.

[0048] The user can embody a specific function (prototype verification function or debugging function) in the configuration file by selecting the prototype verification function or the debugging function when compiling and synthesizing the logic system design.

[0049] Corresponding to the prototype verification function, the configuration file 304 generally only needs to configure the generation of the logic system design on the FPGA 2026 and configure the connection relationship of the physical pins.

[0050] In contrast, the configuration file 306 may further include information for configuring the debugging function. In some embodiments, during the process of the simulation tool 202 implementing the debugging function, the user needs to observe and record the values of one or more key signals during the simulation of the logic system design. The values of these key signals can be led out to the interface 2022 via one or more pins specified in the configuration file 306 and transmitted to the host 100. Therefore, compared with the configuration file 304, the configuration file 306 needs to additionally configure these pins for reading the values of the key signals and the connections of these pins to the interface 2022 on the FPGA 2026. In addition, in some embodiments, the configuration file 306 also needs to configure the generation of a small CPU on the FPGA 2026 for processing debugging functions such as triggering.

[0051] It can be understood that the configuration file 306 may include more debugging functions and is not limited to the above examples.

[0052] Thus, compared with the configuration file 304, the configuration file 306 needs to configure more functions and modules on the FPGA 2026, which will cause the running speed of the hardware simulation tool configured via the configuration file 306 to be significantly lower than that of the hardware simulation tool configured via the configuration file 304.

[0053] For a general hardware emulator focusing on the debugging function, due to the drag of the debugging function, its running speed for the logic system design is relatively slow (for example, about several hundred kHz or 1 MHz). Although the prototype verification board focusing on the prototype verification function can run at a relatively fast speed (for example, up to 10 MHz), the prototype verification board does not support the debugging function.

[0054] How to support both the prototype verification function and the debugging function on a hardware simulation tool and increase the running frequency of the simulation logic system design is a technical problem to be solved urgently.

[0055] Figure 4 The figure shows a schematic diagram of configuring hardware simulation resources according to an embodiment of the present application.

[0056] The simulation tool 202 typically has sufficient hardware resources to complete the prototype verification function or the debugging function. The hardware resources typically may include at least one of one or more programmable logic devices (e.g., FPGAs), configurable interfaces, or one or more daughter cards. The amount of resources of the hardware resources can be measured by the number of programmable logic devices (e.g., the number of equivalent gate circuits), the number of configurable interfaces, and the number of daughter cards.

[0057] When the simulation tool 202 performs prototype verification on the design 302, the host 100 can call the configuration file 304 to configure the hardware simulation resources 410. As Figure 4 shown, the hardware simulation resources 410 may include one or more programmable logic devices (e.g., FPGAs 401 - 404). When the simulation tool debugs the design 302, the host 100 can call the configuration file 306 to configure the hardware simulation resources 420. As Figure 4 shown, the hardware simulation resources 420 may include one or more programmable logic devices (e.g., FPGAs 401 - 408).

[0058] In some embodiments, the hardware simulation resources may further include hardware devices connected to the simulation tool 202, such as peripheral daughter cards.

[0059] Generally, since the debugging function needs to process and save more signals, the amount of resources of the hardware simulation resources 420 is greater than or equal to the amount of resources of the hardware simulation resources 410.

[0060] Figure 5 FIG. shows a schematic diagram of a process 500 for debugging the logic system design 302 according to an embodiment of the present application.

[0061] When prototyping the logic system design 302, the host 100 can set a restore point at a specific clock cycle. The restore point can include a given clock cycle or the clock cycle at which an error occurs. In some embodiments, the user can set certain clock cycles as restore points. In other embodiments, the host 100 can save the clock cycle in which an error message appears during the prototype verification process as the restore point. The restore point includes the simulation clock cycles that require the simulation tool 202 for subsequent debugging. Examples of restore points are not shown in the present application. The following description assumes the same restore point a, i.e., clock cycle a.

[0062] As Figure 5 shown, the design 302 may include multiple modules, such as module A. Among them, the signal 502 at the output port of module A may be a key signal of the logic system design 302.

[0063] As Figure 5As shown, when the simulation tool 202 performs prototype verification on the logic system design 302, the host 100 can call the configuration file 302 to configure the hardware simulation resources 410. In clock cycle a, the simulation tool 202 and the host 100 can obtain the signal value of the first physical signal (e.g., physical signal 501) corresponding to the critical signal on the hardware simulation resources 410 in clock cycle a. According to the configuration file 304 and the logic system design 302, the host 100 can determine the first mapping 510 from the design 302 to the hardware simulation resources 410. The first mapping 510 at least includes the mapping relationship between the critical signal 502 of the design 302 and the physical signal 501 of the FPGA 401. The host 100 can save the value of the physical signal 501 in clock cycle a to a snapshot (not shown). A snapshot is usually a kind of database (e.g., waveform database). In the embodiments of the present application, the snapshot can include the signal values of the physical signals corresponding to the critical signals in the hardware simulation resources 410 at the restoration point (i.e., the clock cycle). In some other embodiments, the snapshot can also include the signal values of the critical signals of the logic system design at the restoration point (i.e., the clock cycle).

[0064] According to the signal value of the first physical signal and the description of the logic system design (e.g., configuration file or netlist, etc.), the host 100 can determine the signal value of the critical signal of the logic system design. For example, the host 100 can determine the first mapping 510 between the critical signal 502 and the physical signal 501 of the logic system design according to the logic system design 302 and the configuration file 304; and determine the value of the critical signal 502 of the logic system design corresponding to the physical signal 501 of the hardware resources 410 in clock cycle a according to the snapshot (not shown) and the first mapping 510.

[0065] In some embodiments, as Figure 5 shown, the first mapping 510 can include the mapping relationship between the critical signal 502 and the physical signal 501. The simulation tool 202 and the host 100 save the signal value of the physical signal 501 at the restoration point a (i.e., the given clock cycle a) to a snapshot (not shown). According to the first mapping 510 and the snapshot (not shown), the host 100 can determine the signal value of the critical signal 502 in the design 302 corresponding to the physical signal 501 at the restoration point a (i.e., the clock cycle a). It can be understood that the snapshot (not shown) can also include the signal value of the critical signal 502 at the restoration point a (i.e., the clock cycle a).

[0066] When the simulation tool 202 starts to debug the logic system design 302, the host 100 can call the configuration file 306 to reconfigure the hardware simulation resources 420. According to the configuration file 306 and the logic system design 302, the host 100 can determine a second mapping 520 from the design 302 to the hardware simulation resources 420. The second mapping 520 at least includes the mapping relationship between the key signals 502 of the design 302 and the physical signals 503 of the FPGA 403.

[0067] In the above embodiment, as Figure 5 shown, according to the value of the key signal 502 in clock cycle a and the second mapping 520, the host 100 can determine the signal value of the physical signal 503 of the hardware simulation resources 420 in clock cycle a. More specifically, according to the second mapping 520, the host 100 can obtain the signal value of the physical signal 503 of the FPGA 403 on the hardware simulation tool 420 in clock cycle a through the signal value of the key signal 502 of the design 302 in clock cycle a. In this way, the host 100 can initialize the physical signal 503 with the signal value of the physical signal 503 in clock cycle a, so that the logic system design 302 on the hardware simulation resources 420 is restored to clock cycle a.

[0068] In summary, the embodiments of the present application provide different configuration files for the prototype verification function and the debugging function of the hardware simulation tool to configure different hardware resources, which speeds up the prototype verification of the hardware simulation tool and retains the debugging ability of the hardware simulation tool, thereby improving the operating efficiency of the hardware simulation tool for simulating the logic system design.

[0069] Figure 6 FIG. shows a schematic diagram of another process 600 for debugging the logic system design 302 according to an embodiment of the present application.

[0070] In some embodiments, as Figure 6 shown, the simulation tool 202 can perform prototype verification on the logic system design 302 on the hardware simulation resources 410. The configuration file of the hardware simulation resources 410 is Figure 6 not shown. The mapping 612 from the logic system design 302 to the hardware simulation resources 410 may include the mapping relationship between the key signal 603 and the physical signal 601 of the FPGA 401 and the mapping relationship between the key signal 604 and the physical signal 602 of the FPGA 404. According to the mapping 612 and the signal values of the physical signal 601 and the physical signal 602 in clock cycle a, the host 100 can determine the signal values of the key signal 603 and the key signal 604 in clock cycle a.

[0071] In some embodiments, the amount of resources of the original simulation tool 202 for the prototype verification logic system design 302 is insufficient to implement the logic system design 302 with debugging functions. At this time, the host 100 can divide the logic system design 302 into multiple parts, select the debugging function, and compile a part of the logic system design 302 to generate a new configuration file, so as to complete the debugging of this part on the simulation tool 202. The host 100 can determine that the amount of resources of the simulation tool 202 does not meet the requirements of the debugging function, and as Figure 6 shown, divide the logic system design 302 into sub-design 312 and sub-design 322. The output signal of module B of sub-design 312 is, for example, a key signal 602, and the output signal of module C of sub-design 322 is, for example, a key signal 604. The host 100 can implement sub-design 312 on the hardware simulation resource 620 and perform debugging, and implement sub-design 322 on the hardware simulation resource 630 and perform debugging. In this way, a mapping 622 from sub-design 312 to the actual circuit on the hardware simulation resource 620 and a mapping 632 from sub-design 322 to the actual circuit on the hardware simulation resource 630 are generated. In some embodiments, the mapping 622 may include the mapping relationship between the key signal 603 and the physical signal 605 of the FPGA 641; the mapping 632 may include the mapping relationship between the key signal 604 and the physical signal 606 of the FPGA 651.

[0072] According to the mapping 622 and the signal value of the key signal 603 in clock cycle a, the host 100 can obtain the signal value of the physical signal 605 in clock cycle a to initialize the physical signal 605, and finally initialize a part of the logic system design 302 (i.e., sub-design 312) to clock cycle a. Similarly, according to the mapping 632 and the signal value of the key signal 604 in clock cycle a, the host 100 can obtain the signal value of the physical signal 606 in clock cycle a to initialize the physical signal 606, and finally initialize another part of the logic system design 302 (i.e., sub-design 322) to clock cycle a.

[0073] In this way, by dividing the logic system design during the debugging phase, not only the problem of insufficient hardware resources of the simulation tool is solved, but also the verification task of the complex logic system design can be divided into multiple subtasks and debugged on hardware tools with lower specifications. At the same time, since the cost of hardware simulation tools with a large number of FPGAs is relatively high, the embodiments of the present application reduce the demand for high-performance hardware tools by debugging on hardware tools with lower specifications, thereby reducing the cost for users.

[0074] In summary, in the present application, different configuration files are provided for the prototype verification function and the debugging function of the hardware simulation tool to configure different hardware resources, which speeds up the prototype verification of the hardware simulation tool and retains the debugging ability of the hardware simulation tool, thereby improving the operating efficiency of the hardware simulation tool for simulating the logic system design. The present application also divides the logic system design and then verifies or debugs it, solves the problem of insufficient hardware resources that may exist in the simulation tool, simplifies the complex and numerous verification tasks, reduces the simulation tasks of the simulation tool, and speeds up the efficiency of the simulation system. At the same time, since the development cost of the hardware simulation tool with a large number of FPGAs is relatively high, dividing the logic system design and then using the hardware simulation tools with smaller resource amounts for simulation also greatly solves the simulation cost.

[0075] An embodiment of the present application also provides a method for simulating a logic system design on a hardware simulation tool.

[0076] Figure 7 FIG. 7 shows a flowchart of a method 700 for simulating a logic system design on a hardware simulation tool according to an embodiment of the present application. Among them, the method 700 can be executed by a host 100 as shown in Figure 2 The method 700 may include the following steps.

[0077] In step 701, the host 100 may compile the logic system design (e.g., Figure 3 the logic system design 302 in Figure 3 to generate a first configuration file (e.g., Figure 3 the configuration file 304 in

[0078] The first configuration file corresponds to the prototype verification function of the logic system design, and the second configuration file corresponds to the debugging function of the logic system design.

[0079] In some embodiments, in response to selecting the prototype verification function, the host 100 may compile the logic system design in combination with the prototype verification function to generate the first configuration file; in response to selecting the debugging function, the host 100 may compile the logic system design in combination with the debugging function to generate the second configuration.

[0080] In step 702, the host 100 may configure the first hardware resources ( Figure 3 the hardware simulation resources 410 in Figure 2 of the hardware simulation tool (e.g., Figure 4 the hardware simulation tool 202 in Figure 3in the logical system design 302).

[0081] In step 703, the host 100 obtains a first snapshot (not shown) of the simulation of the logical system design (e.g., the logical system design 302 in Figure 3 ) in the first clock cycle (e.g., the above-mentioned clock cycle a).

[0082] In some embodiments, the first snapshot includes the value of a first physical signal (e.g., the physical signal 501 in Figure 5 ) on the first hardware resource (e.g., the hardware simulation resource 410 of Figure 5 ) in the first clock cycle.

[0083] In other embodiments, in addition to the value of the above physical signal in the first clock cycle, the first snapshot further includes the value of a key signal (e.g., the key signal 502 in Figure 5 ) of the logical system design in the first clock cycle.

[0084] The first snapshot can be directly output by the hardware simulation tool 202 or the host 100 generates the value of the key signal after obtaining the value of the physical signal and stores it. For example, method 700 may further include: determining a first mapping (e.g., the mapping 510 of Figure 5 ) between the key signal of the logical system design and the first physical signal according to the logical system design and the first configuration file; determining the value of the key signal of the logical system design corresponding to the first physical signal of the first hardware resource in the first clock cycle according to the first snapshot and the first mapping.

[0085] In step 704, the host 100 may configure a second hardware resource (e.g., the hardware simulation resource 420 of Figure 3 ) of the hardware simulation tool according to the second configuration file (e.g., the configuration file 304 in Figure 5 ) to debug the logical system design.

[0086] It can be understood that since the debugging function occupies more hardware resources, the resource amount of the second hardware resource is greater than or equal to the resource amount of the first hardware resource. The resource amount of the hardware resource mentioned here can refer to the capacity of the programmable logic device, the number of hardware resources such as daughter cards, etc. For example, the first hardware resource includes a programmable logic device.

[0087] In step 705, the host 100 may restore the logical system design to the first time period on the second hardware resource (e.g., the hardware simulation resource 420 of Figure 5 ) according to the first snapshot.

[0088] In some embodiments, the host 100 may: design and configure the second configuration file according to the logic system (for example, Figure 3 The configuration file 304 in the second hardware resource determines the key signal (for example, Figure 5 The second physical signal (eg, Figure 5 physical signal 503) and a second mapping between the key signal and the second physical signal (eg, Figure 5 mapping 520); and determining a value of the second physical signal in the first clock cycle according to the value of the key signal in the first clock cycle and the second mapping.

[0089] In some embodiments, when the hardware simulation tool is not sufficient to support the logic system design with debugging function, the second configuration file may correspond to only a part of the logic system design.

[0090] Through the embodiments of the present application, the user can separate the prototype verification function and the debugging function, and use different configuration files in the prototype verification stage and the debugging stage, so that the hardware simulation tool can have a higher operating frequency in the prototype verification stage, while having the required debugging function in the debugging stage.

[0091] The present application also provides an electronic device. The electronic device may be Figure 1 The host 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device executes the method 700.

[0092] The embodiment of the present application further provides a non-transitory computer-readable storage medium, which stores a set of computer instructions, and the set of instructions is used to make the computer perform method 700 when executed.

[0093] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0094] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; within the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above, which are not provided in detail for the sake of brevity.

[0095] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can be used with the embodiments discussed.

[0096] The present application is intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the protection scope of the present application.

Claims

1. A method for simulating a logic system design on a hardware simulation tool, comprising: Compiling the logic system design to generate a first configuration file and a second configuration file respectively, wherein the first configuration file corresponds to a prototype verification function of the logic system design, and the second configuration file corresponds to a debugging function of the logic system design; configuring a first hardware resource of the hardware simulation tool according to the first configuration file to simulate the logic system design; Obtain a first snapshot of the simulation of the logic system design in a first clock cycle, wherein the first snapshot further includes a value of a key signal of the logic system design in the first clock cycle; configuring a second hardware resource of the hardware simulation tool according to the second configuration file to debug the logic system design; as well as Restoring the logic system design to the first clock cycle on the second hardware resource according to the first snapshot; Wherein, compiling the logic system design to generate a first configuration file and a second configuration file respectively further comprises: In response to selecting the prototype verification function, compiling the logic system design in conjunction with the prototype verification function to generate the first configuration file; and In response to selecting the debug function, the logic system design is compiled in combination with the debug function to generate the second configuration file, the second configuration file includes information for configuring the debug function, and the second configuration file is used to configure the pin for reading the value of the key signal and the connection of the pin to the interface on the second hardware resource.

2. The method of claim 1, wherein: The resource amount of the second hardware resource is greater than or equal to the resource amount of the first hardware resource, and the first hardware resource includes a programmable logic device.

3. The method of claim 1, wherein: The first snapshot includes a value of a first physical signal on the first hardware resource in the first clock cycle.

4. The method of claim 3, wherein: The method further comprises: Determine a first mapping between a key signal of the logic system design and the first physical signal according to the logic system design and the first configuration file; A value of a key signal of the logic system design corresponding to a first physical signal of the first hardware resource in the first clock cycle is determined according to the first snapshot and the first mapping.

5. The method of claim 4, wherein: Restoring the logic system design to the first clock cycle on the second hardware resource according to the first snapshot further includes: Determining, on the second hardware resource according to the logical system design and the second configuration file, a second physical signal corresponding to the critical signal and a second mapping between the critical signal and the second physical signal; and The value of the second physical signal in the first clock cycle is determined according to the value of the key signal in the first clock cycle and the second mapping.

6. The method according to any one of claims 1 to 4, wherein: The second configuration file corresponds to a portion of the logical system design.

7. An electronic device for simulating a logic system design, comprising: a memory for storing a set of instructions; as well as At least one processor is configured to execute the set of instructions to perform the method according to any one of claims 1 to 6.

8. A non-transitory computer-readable storage medium storing a set of instructions for a computing device, the set of instructions being used to cause the computing device to execute the method according to any one of claims 1 to 6.

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