Power electronic components with embedded power electronic devices

Abstract

This disclosure relates to a power electronic assembly having embedded power electronic devices. The power electronic assembly includes a circuit board assembly comprising a first electrically insulating layer, an electrically insulating substrate, a laminate disposed between the first electrically insulating layer and the electrically insulating substrate, and one or more conductive layers disposed within the electrically insulating substrate. The laminate includes a power electronic device assembly comprising an S-cell and power electronic devices. The S-cell includes a graphite layer and a metal layer covering the graphite layer. A groove is formed in the outer surface of the metal layer, and the power electronic devices are disposed within the groove on the outer surface of the S-cell.

Description

Technical Field

[0001] This specification generally relates to power electronic components, and more specifically, to apparatus and methods for power electronic components that have low overall thermal resistance while achieving a compact package size. Background Technology

[0002] With the increasing use of electronic components in vehicles, there is a need for more compact electronic systems. One component of these systems is the power electronic equipment used as a switch in the inverter. Power electronic equipment has significant cooling requirements due to the heat it generates.

[0003] Furthermore, power electronic devices, conventionally made of silicon, are now trending towards using silicon carbide. The use of silicon carbide results in greater heat flux because it limits the device footprint. For these and other reasons, there is a need to improve the cooling of power electronic devices while maintaining a compact package size. Summary of the Invention

[0004] In one embodiment, a power electronic component includes: a circuit board assembly comprising: a first electrically insulating layer; an electrically insulating substrate; a laminate disposed between the first electrically insulating layer and the electrically insulating substrate, the laminate comprising: a power electronic device assembly comprising: an S-cell comprising: a graphite layer; a metal layer covering the graphite layer, wherein a groove is formed in the outer surface of the metal layer; a power electronic device disposed in the groove on the outer surface of the S-cell; and one or more conductive layers disposed within the electrically insulating substrate.

[0005] In another embodiment, a power electronic assembly includes: a circuit board assembly comprising: a first electrically insulating layer; an electrically insulating substrate; a laminate disposed between the first electrically insulating layer and the electrically insulating substrate, the laminate comprising: a plurality of power electronic device assemblies, each power electronic device assembly comprising: an S-unit comprising: a graphite layer; and a metal layer covering the graphite layer, wherein a groove is formed in the outer surface of the metal layer; and a power electronic device disposed within the groove on the outer surface of the S-unit; and one or more conductive layers disposed within the electrically insulating substrate, wherein each power electronic device is thermally coupled to a plurality of thermally perforated vias in the one or more conductive layers; and a cold plate, wherein the metal layer of each S-unit of the circuit board assembly is bonded to a first surface of the cold plate via the first electrically insulating layer.

[0006] In yet another embodiment, a method includes: forming a first electrically insulating layer on a first surface of a cold plate; forming a laminate opposite to the cold plate on the first electrically insulating layer, the laminate including: a power electronic device assembly including: an S-unit including: a graphite layer; and a metal layer covering the graphite layer, a groove being formed in the outer surface of the metal layer; and a power electronic device disposed within the groove on the outer surface of the S-unit; laminating a first double-layer circuit pair opposite to the first electrically insulating layer on the laminate; laser-drilling through-holes through the first double-layer circuit pair; and filling the through-holes with a conductive material to thermally couple the first double-layer circuit pair to the power electronic device.

[0007] These and additional features provided by the embodiments described herein will be more fully understood from the following detailed description and in conjunction with the accompanying drawings. Attached Figure Description

[0008] The embodiments illustrated in the accompanying drawings are illustrative and exemplary in nature and are not intended to limit the subject matter defined by the claims. The following detailed description of the illustrative embodiments will be understood when read in conjunction with the following drawings, wherein like structures are indicated by like reference numerals, and wherein:

[0009] Figure 1 An assembly perspective view of a power electronic assembly including a cold plate and a circuit board assembly, according to one or more embodiments described and illustrated herein, is depicted schematically.

[0010] Figure 2 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 An exploded perspective view of the power electronic components;

[0011] Figure 3 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A partial perspective view of the cold plate of the power electronic components;

[0012] Figure 4 An exploded perspective view of a power electronic device assembly including an S-cell and power electronic devices according to one or more embodiments described and illustrated herein is schematically depicted.

[0013] Figure 5 One or more embodiments described and illustrated herein are illustrated schematically. Figure 4 Cross-sectional view of a power electronic device component;

[0014] Figure 6 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1A partial perspective view of a power electronic assembly, which includes a cold plate and a laminated layer comprising multiple power electronic device components;

[0015] Figure 7 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 An exploded cross-sectional view of the power electronic components, illustrating the first double-layer circuit pair of the circuit board assembly.

[0016] Figure 8 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating the first double-layer circuit pair of the circuit board assembly;

[0017] Figure 9 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating the through-hole formed through the first double-layer circuit pair of the circuit board assembly.

[0018] Figure 10 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating... Figure 9 The through hole was filled;

[0019] Figure 11 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating the etching of the first double-layer circuit pair of the circuit board assembly.

[0020] Figure 12 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 An exploded cross-sectional view of the power electronic components, illustrating the second double-layer circuit pair of the circuit board assembly.

[0021] Figure 13 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating the second double-layer circuit pair of the circuit board assembly;

[0022] Figure 14 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating the through-hole formed through the second double-layer circuit pair of the circuit board assembly;

[0023] Figure 15One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating... Figure 14 The through hole was filled;

[0024] Figure 16 One or more embodiments described and illustrated herein are illustrated schematically. Figure 1 A cross-sectional view of the assembled power electronic components, illustrating the etching of the second double-layer circuit pair of the circuit board assembly; and

[0025] Figure 17 The illustration schematically depicts a plurality of surface-mount electronics according to one or more embodiments described and shown herein. Figure 1 A cross-sectional view of the assembled power electronic components. Detailed Implementation

[0026] The embodiments described herein generally relate to power electronic assemblies having a circuit board assembly coupled to a cold plate, the circuit board assembly including a power electronic device assembly that includes an S-cell. Power electronic devices may be embedded within the S-cell.

[0027] The power electronic device assembly disclosed herein includes power electronic devices attached to a mounting substrate, referred to herein as an S-cell. As described in more detail below, the S-cell includes a graphite layer providing enhanced thermal diffusion capabilities. Furthermore, embodiments of this disclosure include one or more electrically insulating layers that electrically isolate the power electronic device(s) from a cold plate. For example, the electrically insulating layer of the S-cell makes it possible to remove the electrically insulating layer between the printed circuit board and the cold plate, since the electrical isolation is provided by the S-cell itself.

[0028] As described in more detail below, the S-cell of this disclosure provides enhanced thermal properties by facilitating heat flux flow to the graphite layer of the cold plate. The S-cell described herein comprises stacked metal, graphite, and one or more electrically insulating layers in a compact package. The bonding materials described herein for bonding the S-cell are particularly suitable for increased thermal conductivity relative to other bonding techniques while maintaining the ability to electrically insulate the S-cell. The devices, systems, and apparatuses described herein improve heat flux from the S-cell to the cold plate, thereby increasing thermal diffusion and cooling performance of the circuit board assembly.

[0029] The cold plates, power electronic equipment components, circuit board assemblies, and power electronic components described herein can be used in electrified vehicles, such as, but not limited to, electric vehicles, hybrid electric vehicles, any electric motor, generator, industrial tools, household appliances, etc. The various components described herein can be electrically coupled to an electric motor and / or battery and can be configured as inverter circuits operable to convert direct current (DC) power to alternating current (AC) power.

[0030] As used herein, "power electronic device" means any electrical component used to convert DC power to AC power and vice versa. Examples can also be used in AC-AC converters and DC-DC converter applications. Non-limiting examples of power electronic devices include power metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), thyristors, and power transistors.

[0031] As used herein, the phrase “fully embedded” means that every surface of a component is surrounded by a substrate. For example, when a power electronic device assembly is fully embedded in a circuit board substrate, it means that the material of the circuit board substrate covers every surface of the circuit board substrate. When one or more surfaces of a component are exposed, the component is “partially embedded.”

[0032] As used herein, an “S-cell” is an operable mounting substrate for attachment to a power electronic device and includes one or more of a metal layer, a graphite layer, and an electrical insulating layer.

[0033] Various embodiments of power electronic components, power electronic device assemblies, and cold plates are described in detail below. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0034] Now for reference Figure 1 and Figure 2 Example power electronic assembly 100 is shown in both assembly and exploded views. Figure 1 and Figure 2 The power electronic assembly 100 shown includes a cold plate 102 and a circuit board assembly 106. The cold plate 102 may be a power electronic device 140 (see [link to power electronic device 140]) capable of coupling from a substrate material to the circuit board assembly 106. Figure 4 Any device that removes heat flux. Non-limiting examples of the cold plate 102 include radiators, single-phase liquid cooling, two-phase liquid cooling, and steam chambers. Figure 1 and Figure 2 The illustration shows that the cold plate 102 has been configured as a single-phase liquid cooling device. The cold plate 102 includes a fluid chamber 115 within the cold plate 102, into which fluid is coupled. Figure 7 The fluid inlet 132 and fluid outlet 134 are shown. Although Figure 1 and Figure 2 The fluid inlet 132 and fluid outlet 134 are depicted as being located on the same side of the cold plate 102, but this disclosure is not limited to such an embodiment. That is, in other embodiments, the fluid inlet 132 and fluid outlet 134 may be located on other surfaces.

[0035] Refer again Figure 1 and Figure 2The circuit board assembly 106 is coupled (e.g., fixed) to the first surface 107 of the cold plate 102. Figure 1 and Figure 2 The illustration shows that the circuit board assembly 106 is secured to the first surface 107 of the cold plate 102 by fasteners 101 (e.g., bolts and nuts) extending through a through-hole 105 and a through-hole 109 of the circuit board assembly 106. It should be appreciated that in other embodiments, the through-holes 105, 109 and the fasteners 101 may be omitted, as described below.

[0036] In an embodiment, the circuit board assembly 106 may be a 3D printed layer. It should be recognized that, in such an embodiment, the 3D printed layer of the circuit board assembly 106 reduces the overall thermal resistance. In an embodiment, the circuit board assembly 106 may be laminated to the cold plate 102. However, other additive manufacturing processes for attaching the circuit board assembly 106 to the cold plate 102 are also contemplated and included within the scope of this disclosure. Additionally, as described in more detail herein, laser drilling can be used in the various components of the circuit board assembly 106 and the power electronics device 140 (…). Figure 4 Through-holes are formed between the components. That is, the through-holes are drilled through the circuit board assembly 106 to the top surface of each conductive layer and power electronics device 140. As described in more detail herein, the through-holes are then filled with copper via an electroplating method to establish electrical connections between the components. Although the circuit board assembly 106 is in Figure 1 and Figure 2 A general description is provided, but the individual layers and assembly steps are described in detail below. Figures 6-17 Described in the text.

[0037] Now for reference Figures 3-17 This describes the various steps involved in manufacturing the power electronic component 100. For example... Figure 3 As shown, a first electrical insulating layer 180 is deposited on the first surface 107 of the cold plate 102 to reduce the electrical insulation of the circuit board assembly 106 and the cold plate 102. Figure 1 The first electrical insulating layer 180 can typically be any layer providing electrical insulation, such as ceramic. In one embodiment, the first electrical insulating layer 180 comprises an insulating metal substrate (IMS) dielectric film. The IMS dielectric film can be a solid film layer. In other embodiments, the first electrical insulating layer 180 can be a thermal grease layer. Note that the first electrical insulating layer 180 may not have dedicated through-holes.

[0038] Now for reference Figure 4 and Figure 5 The exploded top perspective view and assembled cross-sectional view of example S-cell 121 are shown, respectively. S-cell 121 comprises multiple stacked layers. In particular, Figure 4 and Figure 5The S-unit 121 shown includes a metal layer 122 and a graphite layer 124 embedded within the metal layer 122. The metal layer 122 includes an inner surface 125 and an outer surface 128 opposite to the inner surface 125. In an embodiment, the metal layer 122 includes a first metal layer and a second metal layer, wherein the graphite layer 124 is positioned between the first and second metal layers. The metal layer 122 includes a recess 127 disposed in the outer surface 128 of the metal layer 122. The dimensions of the recess 127 are designed to accommodate a power electronic device 140. As described in more detail below, the metal layer 122 provides a conductive surface to which electrodes on the bottom surface of the power electronic device 140 are connected (e.g., via direct connections and / or via electrical connection through-holes). It should be appreciated that... Figure 4 and Figure 5 The layers of S-unit 121 depicted are merely illustrative. That is, for example, in some embodiments, S-unit 121 may include multiple graphite layers and / or other layers deployed between metal layers.

[0039] Note that, Figure 4 and Figure 5 In the embodiments, S unit 121 includes a graphite layer 124 embedded within a metal layer 122 to provide along... Figure 4 and Figure 5 The S-cell 121 is symmetrical about the z-axis of the coordinate system plotted in the figure. The symmetry of the S-cell 121 balances the forces on the S-cell 121 during the high-temperature bonding process. Because the metal layer 122 and the graphite layer 124 have different coefficients of thermal expansion, it may be desirable to have a symmetrical substrate stack to balance the thermal stresses during the bonding process.

[0040] The metal layer 122 can be made of any suitable metal or alloy. As a non-limiting example, copper and aluminum can be used as the metal layer. The metal layer 122 of the S unit 121 has a groove 127 formed in its outer surface 128. The groove 127 can be formed, for example, by chemical etching. The groove 127 has the size and shape to receive the power electronic device 140. The outer surface 128 can generally be a second main surface or surface of the metal layer 122 opposite to the inner surface 125 (which is configured as a first main surface or surface of the metal layer 122). That is, the metal layer 122 can be a planar layer, whereby the inner surface 125 faces the graphite layer 124 and the opposing outer surface 128 faces the power electronic device 140 and the circuit board assembly 106. Figure 7 ).

[0041] Figure 5 In the embodiments depicted, the graphite layer 124 is configured to facilitate heat diffusion through the S-unit 121 and toward the cold plate 102 (see, for example...). Figure 7The crystal structure of graphite provides it with high thermal conductivity, making it suitable for conducting heat flux to the cold plate 102. However, graphite does not possess an isothermal curve. Instead, it exhibits a non-isothermal curve, with high thermal conductivity along two axes and low thermal conductivity along a third axis. To account for the non-isothermal curve of graphite, the S-unit 121 is designed in a rectangular shape, such that its length dimension is greater than its width dimension. (Reference) Figure 5 Graphite layer 124 along Figure 5 The x-axis and z-axis of the coordinate system plotted in the figure have high thermal conductivity. Therefore, the S-unit 121 is designed such that its dimension along the x-axis is greater than its dimension along the y-axis. Heat flux will propagate along both the x-axis and z-axis. As described in more detail below, the heat flux moves from the S-unit 121 along the x-axis toward the cold plate 102. The heat flux will also propagate along the z-axis toward the cold plate 102.

[0042] Refer again Figure 4 An exploded view of a power electronic device assembly 146, including an S-unit 121 and a power electronic device 140, is depicted. Figure 4 A power electronic device 140 and a bonding layer 143 relative to a recess 127 of an S-cell 121 are depicted. The bonding layer 143 may be, for example, a solder layer. As another example, the bonding layer 143 may be a transient liquid bonding layer 143. The power electronic device 140 includes a plurality of large electrodes 141 and a plurality of small electrodes 142 on its top surface. The large electrodes 141 may be power electrodes, while the small electrodes 142 may be signal electrodes. Note that although in Figure 4 While not visible, the power electronic device 140 also includes one or more electrodes on its bottom surface. By placing the power electronic device 140 into the recess 127, one or more electrodes on the bottom surface of the power electronic device 140 are electrically connected to the metal layer 122. Therefore, electrical connections to the bottom electrodes of the power electronic device 140 can be made through the metal layer 122.

[0043] As described above, S-cell 121 is a substrate to which the power electronic device 140 is bonded. S-cell 121 provides a conductive surface area for connection to electrodes on the bottom surface of the power electronic device 140. S-cell 121 also provides thermal diffusion and electrical isolation.

[0044] Now for reference Figure 6A laminate 200, comprising one or more power electronic device assemblies 146 surrounded by a laminated material 202, is disposed opposite a cold plate 102 on a first electrical insulation layer 180. In an embodiment, the laminated material 202 comprises FR-4; however, alternative materials are also within the scope of this disclosure. As shown, a total of six power electronic device assemblies 146 are arranged in two rows of three and bonded to the cold plate 102 via the first electrical insulation layer 180 and the laminated material 202. However, it should be understood that any number of power electronic device assemblies 146 can be used depending on the application.

[0045] Now for reference Figure 7 The figure illustrates a cross-sectional view of the power electronic assembly 100. Cooling fluid (depicted as moving arrow 135) from a storage unit (not shown) flows into a fluid chamber 115 through a fluid inlet 132 and exits the fluid chamber 115 as warm cooling fluid through a fluid outlet 134, where it returns to the storage unit, such as after flowing through a heat exchanger (not shown) to remove heat from the cooling fluid 135. Although not shown, an array of fins may be provided in the fluid chamber 115 to provide additional surface area for heat transfer to the cooling fluid 135.

[0046] As shown in the figure, a laminate 200 is disposed between a first electrical insulating layer 180 and a second electrical insulating layer 204. It should be understood that the second electrical insulating layer 204 may comprise the same material as the first electrical insulating layer 180.

[0047] Still referencing Figure 7 The diagram shows a first double-layer circuit pair 206 positioned above a second electrically insulating layer 204 forming a circuit board assembly 106. The first double-layer circuit pair 206 includes a first conductive layer 208 and a second conductive layer 210 laminated therebetween through a third electrically insulating layer 212. In an embodiment, the first conductive layer 208 and the second conductive layer 210 are copper layers. The first conductive layer 208 is etched into a specified pattern to conduct current, while the second conductive layer 210 remains unetched.

[0048] Now for reference Figure 8 The first double-layer circuit pair 206 is positioned on the second electrical insulating layer 204. The first double-layer circuit pair 206 is laminated to the second electrical insulating layer 204 in a high-temperature, high-pressure chamber. During this lamination step, material from the second electrical insulating layer 204 and the third electrical insulating layer 212 fills the gaps defined by the etching of the first conductive layer 208.

[0049] Now for reference Figure 9Through-holes 112 are formed to extend between any combination of the power electronics device 140, the first conductive layer 208, and the second conductive layer 210 of the power electronics device assembly 146. For example, through-holes 112 are shown extending between the power electronics device 140 and the second conductive layer 210 in each power electronics device assembly 146 and through the first conductive layer 208. Additionally, through-holes 112 (conductive through-holes and thermally conductive through-holes) are shown extending between the first conductive layer 208 and the second conductive layer 210 without intersecting with the power electronics device 140. Through-holes 112 can be formed in any suitable manner, such as, for example, laser drilling. It should be understood that the scope of this disclosure is not limited to... Figure 9 The specific configuration of the through hole 112 is shown in the figure, and other configurations can be envisioned based on the specific needs of the circuit board assembly 106.

[0050] Through-hole 112 can provide a drive signal to power electronic device 140 and provide a current path for switching current. Note that in some embodiments, some through-holes 112 can be configured as thermally conductive through-holes that do not conduct drive signals or switching current. Additionally, the S-cell arrangement allows flux to move from power electronic device 140 to cold plate 102 via S-cell 121, as described herein. In this way, heat flux is optimally directed away from power electronic device 140 and towards cold plate 102 via S-cell 121.

[0051] Now for reference Figure 10 Through-holes 112 are filled with copper by electroplating to form an electrical connection between each power electronic device assembly 146, the first conductive layer 208, and the second conductive layer 210. However, it should be recognized that through-holes 112 can be filled in any other suitable manner besides electroplating.

[0052] Now for reference Figure 11 After the first double-layer circuit pair 206 is laminated to the laminate 200 via the second electrically insulating layer 204, the second conductive layer 210 can be etched into a desired configuration based on the specifications of the circuit board assembly 106. It should be understood that the circuit board assembly 106 may include any number of conductive layers. For example, the circuit board assembly 106 may include only the first conductive layer 208 and the second conductive layer 210. In such embodiments, one or more surface-mount electronic devices (such as…) Figure 17 Surface-mount electronics (214) illustrated herein, such as transistors, resistors, capacitors, etc., can be mounted onto the second conductive layer 210. However, in other embodiments, the circuit board assembly 106 may include multiple double-layer circuit pairs, with the surface-mount electronics mounted on the uppermost conductive layer. In doing so, the process described herein can be repeated for each additional double-layer circuit pair to be laminated onto the previous double-layer circuit pair. Figure 7-11 The steps described.

[0053] For example, now refer to Figure 12 A fourth electrical insulating layer 216 is disposed on the second conductive layer of the first double-layer circuit pair 206, and a second double-layer circuit pair 218 is shown positioned above the first double-layer circuit pair 206. The second double-layer circuit pair 218 includes a third conductive layer 220 and a fourth conductive layer 222 laminated therebetween by a fifth electrical insulating layer 224. In an embodiment, the third conductive layer 220 and the fourth conductive layer 222 are copper layers. The third conductive layer 220 is etched into a specified pattern to conduct current, while the fourth conductive layer 222 remains unetched.

[0054] Now for reference Figure 13 A second double-layer circuit pair 218 is positioned on top of a first double-layer circuit pair 206. The second double-layer circuit pair 218 is laminated to the first double-layer circuit pair 206 in a high-temperature, high-pressure chamber. During this lamination step, material from the second electrical insulating layer 204 and the third electrical insulating layer 212 fills the gaps defined by the etching of the second conductive layer 210. Additionally, material from the fourth electrical insulating layer 216 and the fifth electrical insulating layer 224 fills the gaps defined by the etching of the third conductive layer 220. It should be understood that, in this embodiment, the electrical insulating layers 204, 212, 216, and 224 form a one-piece, monolithic electrical insulating substrate, such that the laminate 200, and specifically the power electronic device assembly 146, is disposed within the electrical insulating substrate.

[0055] Now for reference Figure 14 An additional through-hole 112 is formed to extend between any combination of the first conductive layer 208, the second conductive layer 210, the third conductive layer 220, and the fourth conductive layer 222. For example, the through-hole 112 is shown extending through the third conductive layer 220 between the second conductive layer 210 and the fourth conductive layer 222. Alternatively, the through-hole 112 is shown extending between the third conductive layer 220 and the fourth conductive layer 222 without intersecting with the power electronic device 140, the first conductive layer 208, or the second conductive layer 210. As described herein, it should be understood that the scope of this disclosure is not limited to... Figure 14 The specific configuration of the through hole 112 depicted is shown in the figure, and other configurations can be envisioned based on the specific needs of the circuit board assembly 106.

[0056] Now for reference Figure 15 As described herein, through-holes 112 are filled with electroplated copper to form electrical connections directly or indirectly between each power electronic device assembly 146, the first conductive layer 208, the second conductive layer 210, the third conductive layer 220, and the fourth conductive layer 222.

[0057] Finally, as Figure 16As shown, after the second double-layer circuit pair 218 is laminated to the first double-layer circuit pair 206 via the fourth electrical insulating layer 216, the fourth conductive layer 222 can be etched into the desired configuration based on the specifications of the circuit board assembly 106.

[0058] Now for reference Figure 17 One or more surface mount electronics 214 may be mounted to the fourth conductive layer 222. As described herein, surface mount electronics 214 may include, for example, transistors, resistors, capacitors, etc. Therefore, it should be appreciated that the circuit board assembly 106 includes at least a laminate 200, which includes a plurality of power electronic device assemblies 146, a first double-layer circuit pair 206, a second double-layer circuit pair 218, and surface mount electronics 214.

[0059] As should be understood from the above, this document defines power electronic components and methods for manufacturing the same. Specifically, the power electronic components disclosed herein include circuit board assemblies comprising a first electrically insulating layer, an electrically insulating substrate, a laminate disposed between the first electrically insulating layer and the electrically insulating substrate, and one or more conductive layers disposed within the electrically insulating substrate. The laminate includes a power electronic device assembly comprising an S-cell and power electronic devices. The S-cell comprises a graphite layer and a metal layer covering the graphite layer. A groove is formed in the outer surface of the metal layer, and the power electronic devices are disposed within the groove in the outer surface of the S-cell.

[0060] It should now be understood that embodiments of this disclosure relate to power electronic assemblies having a circuit board assembly coupled to a power electronic device assembly, the power electronic device assembly including a cold plate containing an S-cell. The power electronic device may be embedded within the S-cell and / or within the circuit board assembly. Such a power electronic assembly is compact, provides increased thermal conductivity while maintaining electrical insulation to the S-cell, thereby improving heat flux from the S-cell to the cold plate, thus increasing the thermal diffusion and cooling performance of the circuit board assembly relative to conventional packaging.

[0061] It should be noted that the terms “substantially” and “approximately” are used herein to indicate the degree of uncertainty attributable to any quantitative comparison, value, measurement, or other representation. These terms are also used herein to indicate the extent to which a quantitative representation may differ from the stated reference without altering the fundamental function of the subject matter under discussion.

[0062] While specific embodiments have been illustrated and described herein, it should be understood that various other changes and modifications can be made without departing from the scope of the claimed subject matter. Furthermore, although various aspects of the claimed subject matter have been described herein, they need not be used in combination. Therefore, the appended claims are intended to cover all such changes and modifications within the scope of the claimed subject matter.

[0063] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments described herein without departing from the scope of the claimed subject matter. Therefore, this specification is intended to cover modifications and variations to the various embodiments described herein, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A power electronic component, comprising: Circuit board assembly, including: First electrical insulating layer; Electrically insulating substrate; A laminate is disposed between the first electrically insulating layer and the electrically insulating substrate, the laminate comprising: Multiple power electronic device components, each power electronic device component including: S-unit includes: Graphite layer; and A metal layer covering the graphite layer has grooves formed in its outer surface; and Power electronic equipment, deployed in a groove on the outer surface of the metal layer; Multiple conductive layers are disposed within the electrically insulating substrate; and Multiple through holes extend through the electrically insulating substrate and thermally couple the power electronics of each power electronics component to each conductive layer.

2. The power electronic assembly of claim 1, wherein the laminate comprises: Laminated materials; as well as The plurality of power electronic equipment components are embedded within the laminated material.

3. The power electronic component of claim 2, wherein the laminate material comprises FR-4.

4. The power electronic component of claim 1, wherein the first electrical insulating layer and the electrical insulating substrate each comprise an insulating metal substrate dielectric film.

5. The power electronic assembly of claim 1, wherein the S-unit has a length greater than the width of the S-unit.

6. The power electronic assembly of claim 1, further comprising a cold plate, wherein the circuit board assembly is bonded to the surface of the cold plate through the first electrical insulating layer.

7. A power electronic component, comprising: Circuit board assembly, including: First electrical insulating layer; Electrically insulating substrate; A laminate is disposed between the first electrically insulating layer and the electrically insulating substrate, the laminate comprising: Multiple power electronic device components, each power electronic device component including: S-unit includes: Graphite layer; and A metal layer covering the graphite layer has grooves formed in its outer surface; and Power electronic devices, deployed within grooves on the outer surface of the metal layer; and Multiple conductive layers are disposed within the electrically insulating substrate; Multiple thermal vias thermally couple the power electronics of each power electronics component to each conductive layer; and A cold plate, wherein the metal layer of each S unit of the circuit board assembly is bonded to the first surface of the cold plate via the first electrical insulating layer.

8. The power electronic component as claimed in claim 7, wherein: The laminate includes a laminate material; and The plurality of power electronic equipment components are embedded within the laminated material.

9. The power electronic component of claim 8, wherein the laminate material comprises FR-4.

10. The power electronic component of claim 7, wherein the first electrical insulating layer and the electrical insulating substrate each comprise an insulating metal substrate dielectric film.

11. The power electronic assembly of claim 7, wherein the S-unit has a length greater than the width of the S-unit.

12. A method comprising: A first electrical insulation layer is formed on the first surface of the cold plate; A laminate is disposed on the first electrical insulating layer opposite to the cold plate, the laminate comprising: Multiple power electronic device components, each power electronic device component including: S-unit includes: Graphite layer; and A metal layer covering the graphite layer has grooves formed in its outer surface; and Power electronic equipment, deployed in a groove on the outer surface of the metal layer; A first double-layer circuit pair opposite to the first electrical insulating layer is laminated on the laminate; Through the first double-layer circuit, a laser drilled through hole was formed; and The through-hole is filled with a conductive material to thermally couple the first double-layer circuit to the power electronic device of each power electronic device assembly.

13. The method of claim 12, further comprising laminating a second double-layer circuit pair opposite to the laminate on the first double-layer circuit pair.

14. The method of claim 13, further comprising drilling a through hole through the second double-layer circuit.

15. The method of claim 14, further comprising filling the through-hole extending through the second double-layer circuit pair with the conductive material to thermally couple the second double-layer circuit pair to the first double-layer circuit pair.

16. The method of claim 15, further comprising mounting surface-mount electronics onto the second double-layer circuit pair.

17. The method of claim 13, wherein the first double-layer circuit pair and the second double-layer circuit pair each comprise a pair of conductive layers and an electrically insulating layer therebetween.

18. The method of claim 17, wherein the pair of conductive layers of the first dual-layer circuit pair and the pair of conductive layers of the second dual-layer circuit pair are etched.

19. The method of claim 12, wherein the laminate comprises: Laminated materials; as well as The plurality of power electronic equipment components embedded within the laminated material.

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