Method and apparatus for confirming access path, and SoC chip
By performing spatial address translation on the access information of the SoC chip and adding a flag bit, the complexity of confirming the address space access path between SoC chips is solved, enabling fast confirmation of access paths and logical consistency, reducing the design complexity of the central processing unit and eliminating the risk of deadlock.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN YUXIAN MICROELECTRONICS CO LTD
- Filing Date
- 2024-01-19
- Publication Date
- 2026-05-01
AI Technical Summary
In a central processing unit (CPU), how can the access path be quickly determined when accessing the address space between SoC chips, especially when the processors have different address spaces and there is an issue of cross-access in address spaces?
By performing spatial address translation on the preset access information, a flag bit representing the target SoC chip is added. The flag bit and spatial information bit are used to distinguish the SoC chip from external SoC chips, confirm the logical consistency of the access path, reduce the complexity of the central processing unit architecture design, and eliminate the risk of deadlock.
It enables rapid confirmation of access paths between SoC chips, reduces the complexity of address mapping design, avoids the problem of inconsistent address widths, and eliminates the risk of bus loops and deadlocks.
Smart Images
Figure CN117951076B_ABST
Abstract
Description
Access path verification method and device, SoC chip Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a method and apparatus for confirming access paths, and a SoC chip. Background Technology
[0002] With the continuous development of computer technology, the number of SoC chips in central processing units and the number of processors in SoC chips are gradually increasing. When the address spaces of the processors are different, address space conversion is required when the processors access each other's address spaces. Usually, the first preset access is that there is also cross access between the address spaces of different SoC chips. How to quickly identify the access space corresponding to any access has become an urgent problem to be solved. Summary of the Invention
[0003] Therefore, it is necessary to provide a method and device for confirming access paths, as well as a SoC chip.
[0004] An access path verification method is applied to a SoC chip, the SoC chip including a plurality of main processor cores and a plurality of slave processor cores, the verification method comprising:
[0005] The preset access information issued by the preset main processor core is subjected to spatial address translation processing to obtain the first transition preset access information. The first transition preset access information includes target information bits representing the target SoC chip address and spatial information bits representing the target access address.
[0006] Based on the target information bits, a flag bit for characterizing the target SoC chip is added to the first transition preset access information to obtain the second transition preset access information;
[0007] When the flag bit in the second transition preset access information indicates that the target SoC chip is the SoC chip, and the target access address indicated by the spatial information bit corresponds to the local spatial address of the SoC chip, it is confirmed that the access path of the preset access points to the local space in the SoC chip.
[0008] In the aforementioned method for confirming access paths, spatial address translation processing of the preset access information avoids the inconsistency in address width between the address space of the preset access information and the address space of the target SoC chip. By adding a flag bit representing the target SoC chip, it is possible to distinguish between a target SoC chip and an external SoC chip. The logic for confirming access paths between the SoC chip and the external SoC chip, which is also a SoC chip, is the same, based on the flag bit and spatial information bits. This achieves consistency in the design of the SoC chip in the central processing unit and the external SoC chip, reducing the complexity of the central processing unit architecture design. When the flag bit represents the target SoC chip as the SoC chip, and the target access address represented by the spatial information bits corresponds to the local space address of the SoC chip, the access path of the preset access is confirmed to point to the local space in the SoC chip. The target information bit is not required during access address mapping, reducing the design complexity of address mapping. By extracting the preset access to the local space corresponding to the SoC chip, bus loops are eliminated, and the risk of deadlock is eliminated.
[0009] In one embodiment, the method for confirming the access path further includes:
[0010] When the flag bit in the second transition preset access information indicates that the target SoC chip is the SoC chip, and the target access address indicated by the spatial information bit is different from the local spatial address of the SoC chip, the second transition preset access information is marked as the third transition preset access information;
[0011] When the target SoC chip address represented by the target information bit in the first transition preset access information corresponding to the third transition preset access information corresponds to the SoC chip address, it is confirmed that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip. By distinguishing preset accesses pointing to the remote space corresponding to the slave processor core in the SoC chip based on the target information bit, the filtering of preset accesses whose access paths are the local space and remote space corresponding to the SoC chip is achieved.
[0012] In one embodiment, after confirming that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, the method further includes: sending the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip, and sending the first transition preset access information with the flag removed to the slave processor core in the SoC chip. This removes the influence of human operation on the preset access, so that the slave processor core can determine the relationship between the access path corresponding to the preset access and the remote space of the slave processor core based on the actual preset access, that is, whether the access path corresponding to the preset access is the local space of the slave processor core or the remote space of the slave processor core.
[0013] In one embodiment, the method for confirming the access path further includes:
[0014] When the flag bit in the second transition preset access information indicates that the target SoC chip is an external SoC chip, it is confirmed that the access path of the preset access points to the external SoC chip. The preset access corresponding to the external SoC chip can be distinguished by the flag bit, which simplifies the determination step of the access path of the preset access.
[0015] In one embodiment, the method for confirming the access path further includes:
[0016] When the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip, the first transition preset access information corresponding to the second transition preset access information is sent to the next SoC chip; wherein, the next SoC chip is any of the external SoC chips corresponding to the address of the target SoC chip indicated by the target information bit in the first transition preset access information. Sending the first transition preset access information corresponding to the preset access of the target SoC chip being an external SoC chip to the external SoC chip of the next SoC chip (the new SoC chip) removes the influence of the flag bit related to the current SoC chip on the preset access, so that the external SoC chip, as the next SoC chip, can determine the access path corresponding to the preset access based on the actual preset access (the first transition preset access information corresponding to the preset access information of the preset access).
[0017] In one embodiment, the step of adding a marker bit characterizing the target SoC chip to the first transition preset access information based on the target information bit to obtain the second transition preset access information includes:
[0018] When the target SoC chip corresponding to the target information bit in the first transition preset access information is the SoC chip, a first flag bit is added to the first transition preset access information to obtain flag preset access information;
[0019] When the target SoC chip corresponding to the target information bit in the first transition preset access information is the external SoC chip, a second flag bit is added to the first transition preset access information to obtain flag preset access information;
[0020] The target information bit in the first transition preset access information is stored in a preset channel as target SoC chip information, and the target information bit in the marked preset access information is set to empty information to obtain the second transition preset access information. The first and second marker bits can be used to distinguish whether the target SoC chip is an SoC chip or an external SoC chip. By setting the target information bit in the marked preset access information to empty information, the influence of the target information bit on the address mapping confirmation of the access path through the second transition preset access information is avoided.
[0021] In one embodiment, when the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip, or the access path of the preset access corresponding to the second transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, the method for confirming the access path further includes:
[0022] Based on the target SoC chip information in the preset channel, the empty space information in the second transition preset access information is set as the target SoC chip information. In this way, the first transition preset access information corresponding to the second transition preset access information can be obtained during the transmission of the second transition preset access information, and the influence of the flag bit on determining whether the access path is the remote space corresponding to the processor core in the SoC chip or the space in the external SoC chip can be removed.
[0023] This disclosure also provides a SoC chip, including:
[0024] Several main processor cores;
[0025] Several from processor cores;
[0026] The address space translation module is connected to the main processor core and is used to perform space address translation processing on the preset access information of the preset access issued by the preset main processor core to obtain the first transition preset access information. The first transition preset access information includes target information bits representing the target SoC chip address and space information bits representing the target access address.
[0027] A chip address translation module, connected to the address space translation module, is used to add a marker bit to the first transition preset access information to characterize the target SoC chip according to the target information bit, so as to obtain the second transition preset access information;
[0028] A bus network interconnect module, connected to the chip address translation module, is used to determine that the access path of the preset access points to the local space of the SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is the SoC chip and the target access address indicated by the spatial information bit corresponds to the local space address of the SoC chip.
[0029] In the aforementioned SoC chip, the address space translation module performs space address translation on the preset access information, avoiding the inconsistency in address bit width between the preset access information's address space and the target SoC chip's address space. The chip address translation module adds a flag bit representing the target SoC chip, which can be used to distinguish between a target SoC chip and an external SoC chip. The SoC chip and the external SoC chip, which is also a SoC chip, confirm that the access path logic is the same based on the flag bit and space information bits, achieving consistency between the SoC chip design in the central processing unit and the external SoC chip design, reducing the complexity of the central processing unit architecture design. When the flag bit represents the target SoC chip as the SoC chip, and the target access address represented by the space information bits corresponds to the SoC chip's local space address, the bus network interconnect module confirms that the preset access path points to the local space in the SoC chip. The target information bit is not required during access address mapping, reducing the design complexity of address mapping. By extracting the preset access to the local space corresponding to the SoC chip, bus loops are eliminated, eliminating the risk of deadlock.
[0030] In one embodiment, the address space translation module includes a register, and the address space translation module configures the high-order address in the preset access information through the register to increase the bus address of the preset access information to obtain the first transitional preset access information.
[0031] In one embodiment, the chip address translation module is used to add a first flag bit to the first transitional preset access information when the target SoC chip corresponding to the target information bit in the first transitional preset access information is the SoC chip itself, and to add a second flag bit to the first transitional preset access information when the target SoC chip corresponding to the target information bit in the first transitional preset access information is an external SoC chip, so as to obtain marked preset access information; the chip address translation module is also used to store the target information bit in the first transitional preset access information to a preset channel as target SoC chip information, and to set the target information bit in the marked preset access information to empty information, so as to obtain the second transitional preset access information. The bus network interconnect module can distinguish whether the target SoC chip is an SoC chip or an external SoC chip according to the first flag bit and the second flag bit in the second transitional preset access information. By setting the target information bit in the marked preset access information to empty information, the influence of the target information bit on the bus network interconnect module's address mapping confirmation of the access path through the second transitional preset access information is avoided.
[0032] In one embodiment, the SoC chip also includes:
[0033] The chip address recovery module is connected to the bus network interconnection module;
[0034] The bus network interconnection module is further configured to mark the second transitional preset access information as third transitional preset access information when the target SoC chip represented by the flag bit in the second transitional preset access information is the SoC chip and the target access address represented by the spatial information bit is different from the local spatial address of the SoC chip; it is also configured to confirm that the access path of the preset access points to the external SoC chip when the flag bit in the second transitional preset access information represents the target SoC chip as an external SoC chip, and mark the second transitional preset access information as third transitional preset access information; the chip address recovery module is configured to receive the third transitional preset access information, and set the empty bit information in the third transitional preset access information to the target SoC chip information according to the target SoC chip information in the preset channel, so as to obtain the first transitional preset access information corresponding to the third transitional preset access information.
[0035] In one embodiment, the chip address recovery module is further configured to, when the target information bit in the first transition preset access information corresponding to the third transition preset access information represents the target SoC chip address corresponding to the SoC chip address of the SoC chip, confirm that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, and send the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip.
[0036] In one embodiment, the chip address recovery module is further configured to send the first transition preset access information corresponding to the third transition preset access information to the next SoC chip when the target SoC chip represented by the target information bit in the first transition preset access information corresponding to the third transition preset access information is the external SoC chip.
[0037] Wherein, the next SoC chip is any of the external SoC chips corresponding to the target SoC chip address represented by the target information bit in the first transition preset access information.
[0038] This disclosure also provides a central processing unit including several SoC chips as described above.
[0039] This disclosure also provides an access path verification device applied to a SoC chip, the SoC chip including a plurality of main processor cores and a plurality of slave processor cores, the verification device comprising:
[0040] The address space translation module is connected to the main processor core and is used to perform space address translation processing on the preset access information of the preset access issued by the preset main processor core to obtain the first transition preset access information. The first transition preset access information includes target information bits representing the target SoC chip address and space information bits representing the target access address.
[0041] A chip address translation module, connected to the address space translation module, is used to add a marker bit to the first transition preset access information to characterize the target SoC chip according to the target information bit, so as to obtain the second transition preset access information;
[0042] The determination module, connected to the chip address translation module, is used to determine that the access path of the preset access points to the local space of the SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is the SoC chip and the target access address indicated by the spatial information bit corresponds to the local space address of the SoC chip.
[0043] In the aforementioned access path confirmation device, the address space translation module performs space address translation processing on the preset access information of the preset access, avoiding the problem of inconsistent address bit widths between the address space of the preset access information and the address space of the target SoC chip. The chip address translation module adds a flag bit representing the target SoC chip, which can be used to distinguish between a target SoC chip and an external SoC chip. The SoC chip and the external SoC chip, which is also a SoC chip, confirm the access path based on the same logic using the flag bit and space information bits, achieving consistency between the SoC chip design in the central processing unit and the external SoC chip design, reducing the complexity of the central processing unit architecture design. When the flag bit indicates that the target SoC chip is the SoC chip, and the target access address represented by the space information bit corresponds to the local space address of the SoC chip, the determination module confirms that the access path of the preset access points to the local space in the SoC chip. The target information bit is not required during access address mapping, reducing the design complexity of address mapping. By extracting the preset access to the local space corresponding to the SoC chip, bus loops are eliminated, eliminating the risk of deadlock.
[0044] In one embodiment, the determination module is further configured to mark the second transitional preset access information as third transitional preset access information when the flag bit in the second transitional preset access information indicates that the target SoC chip is the SoC chip, and the target access address indicated by the spatial information bit is different from the local spatial address of the SoC chip; and when the target SoC chip address indicated by the target information bit in the first transitional preset access information corresponding to the third transitional preset access information corresponds to the SoC chip address of the SoC chip, determine that the access path of the preset access corresponding to the third transitional preset access information points to the remote space corresponding to the slave processor core in the SoC chip.
[0045] In one embodiment, the determination module is further configured to send the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip when the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip.
[0046] In one embodiment, the determination module is further configured to determine that the access path of the preset access points to the external SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is an external SoC chip.
[0047] In one embodiment, the determination module is further configured to send the first transition preset access information corresponding to the second transition preset access information to the next SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip;
[0048] The next SoC chip is any of the external SoC chips corresponding to the target SoC chip address represented by the target information bit in the first transition preset access information.
[0049] This disclosure also provides a computer device, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the verification method as described in any of the preceding claims.
[0050] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the verification method as described in any of the preceding claims. Attached Figure Description
[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0052] Figure 1 is a flowchart illustrating a method for confirming an access path in one embodiment;
[0053] Figure 2 is a schematic block diagram of an access path confirmation device in one embodiment;
[0054] Figure 3 is a schematic block diagram of an access path confirmation device in another embodiment;
[0055] Figure 4 is a schematic diagram of a SoC chip in one embodiment;
[0056] Figure 5 is a schematic diagram of the SoC chip in another embodiment;
[0057] Figure 6 is a schematic diagram of a central processing unit in one embodiment. Detailed Implementation
[0058] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0060] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.
[0061] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0062] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.
[0063] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0064] Figure 1 is a flowchart illustrating an access path confirmation method in one embodiment. As shown in Figure 1, this embodiment provides an access path confirmation method applied to a SoC chip. The SoC chip includes several main processor cores and several slave processor cores. The confirmation method includes:
[0065] S102, perform space address translation processing on the preset access information issued by the preset main processor core to obtain the first transition preset access information.
[0066] Specifically, a SoC chip has multiple processors, such as a master processor and slave processors. Access between processors is bidirectional. The processor that issues the access is the master processor core, and the processor that receives the access or the access path is the slave processor core. Depending on the state of issuing or receiving the access, the master processor core and the slave processor core can be interchanged. That is, for a processor in a SoC chip, it acts as a master processor core when it issues an access and as a slave processor core when it receives an access.
[0067] The preset access information issued by the preset main processor core undergoes spatial address translation processing to obtain first transitional preset access information. This first transitional preset access information includes target information bits representing the address of the target SoC chip and spatial information bits representing the target access address. Here, the preset main processor core in the SoC chip is the main processor core that sent the preset access. By performing spatial address translation processing on the preset access information, the first transitional preset access information with the target address space is obtained. This eliminates the problem of inconsistent address space bit width between the preset access information and the target access address in the target SoC chip. For example, if the preset access information is 48 bits and the target access address's address space is 64 bits, then by performing spatial address translation processing on the 48-bit preset access information, a 64-bit first transitional preset access information is obtained.
[0068] S104, based on the target information bits, add a flag bit to the first transition preset access information to characterize the target SoC chip, and obtain the second transition preset access information.
[0069] Specifically, based on the target SoC chip address represented by the target information bits, it can be determined whether the target SoC chip is the SoC chip containing the main processor core or an external SoC chip. Then, a flag bit is added to the first transitional preset access information to indicate whether the target SoC chip is an SoC chip or an external SoC chip, resulting in the second transitional preset access information. At this point, both the SoC chip and any subsequent external SoC chip can use the flag bit in the second transitional preset access information to determine whether the target system is the current SoC chip or an external SoC chip. Then, based on the spatial information bits, it confirms whether to access the SoC chip's local space. The logic for confirming the preset access path is the same for both the SoC chip and the external SoC chip, achieving consistency in the design of the SoC chip within the central processing unit and the external SoC chip outside the SoC chip, simplifying the SoC chip design and reducing the complexity of the central processing unit architecture design.
[0070] S106, when the target SoC chip corresponding to the second transitional access information is an SoC chip and the target access address corresponds to the local space address, confirm that the access path of the preset access points to the local space in the SoC chip.
[0071] When the flag bit in the second transition preset access information indicates that the target SoC chip is an SoC chip, and the target access address indicated by the spatial information bit corresponds to the local space address of the SoC chip, it is confirmed that the access path of the preset access points to the local space in the SoC chip. Confirming that the access path of the preset access points to the local space in the SoC chip eliminates the need for target information bits during access address mapping, reducing the design complexity of address mapping. By extracting the preset access to the local space corresponding to the SoC chip, bus loops are removed, eliminating the risk of deadlock.
[0072] In the aforementioned method for confirming access paths, spatial address translation processing of the preset access information avoids the inconsistency in address width between the address space of the preset access information and the address space of the target SoC chip. By adding a flag bit representing the target SoC chip, it is possible to distinguish between a target SoC chip and an external SoC chip. The logic for confirming access paths between the SoC chip and the external SoC chip, which is also a SoC chip, is the same, based on the flag bit and spatial information bits. This achieves consistency in the design of the SoC chip in the central processing unit and the external SoC chip, reducing the complexity of the central processing unit architecture design. When the flag bit represents the target SoC chip as the SoC chip, and the target access address represented by the spatial information bits corresponds to the local space address of the SoC chip, the access path of the preset access is confirmed to point to the local space in the SoC chip. The target information bit is not required during access address mapping, reducing the design complexity of address mapping. By extracting the preset access to the local space corresponding to the SoC chip, bus loops are eliminated, and the risk of deadlock is eliminated.
[0073] In one embodiment, the method for confirming the access path further includes steps S202-S204.
[0074] S202, when the flag bit in the second transition preset access information indicates that the target SoC chip is the SoC chip, and the target access address indicated by the spatial information bit is different from the local spatial address of the SoC chip, the second transition preset access information is marked as the third transition preset access information.
[0075] S204, when the target SoC chip address represented by the target information bit in the first transition preset access information corresponding to the third transition preset access information corresponds to the SoC chip address of the SoC chip, it is confirmed that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip.
[0076] In the second transition preset access information, the flag bit indicates that the target SoC chip is the SoC chip where the preset main processor core is located. When the target access address indicated by the spatial information bit does not correspond to the local space address in the SoC chip, the access path of the preset access is confirmed according to the target information bit in the first transition preset access information corresponding to the second transition preset access information (third transition preset access information). When the target SoC chip indicated by the target information bit in the first transition preset access information corresponds to the SoC chip address in the SoC chip, it is determined that the access path of the preset access corresponding to the second transition preset access information (third transition preset access information) points to the remote space corresponding to the processor core in the SoC chip. By distinguishing the preset access pointing to the remote space corresponding to the processor core in the SoC chip according to the target information bit, the filtering of preset accesses whose access paths are the local space and remote space corresponding to the SoC chip is realized.
[0077] In one embodiment, after confirming that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, the access path confirmation method further includes: sending the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip. By sending the first transition preset access information with the flag removed to the slave processor core in the SoC chip, the influence of human operation on the preset access is eliminated, allowing the slave processor core to determine the relationship between the access path corresponding to the preset access and the remote space of the slave processor core based on the actual preset access (the first transition preset access information obtained after spatial address translation processing of the preset access information), that is, whether the access path corresponding to the preset access is in the local space of the slave processor core or in the remote space of the slave processor core.
[0078] In one embodiment, the access path confirmation method further includes: when the flag bit in the second transitional preset access information indicates that the target SoC chip is an external SoC chip, confirming that the access path of the preset access points to the external SoC chip. The preset access corresponding to the external SoC chip can be distinguished by the flag bit, simplifying the determination step of the access path for the preset access. Here, the external SoC chip refers to any SoC chip other than the SoC chip containing the preset main processor core in the central processing unit.
[0079] In one embodiment, the access path confirmation method further includes: when the flag bit in the second transitional preset access information indicates that the target SoC chip is the external SoC chip, sending the first transitional preset access information corresponding to the second transitional preset access information to the next SoC chip; wherein, the next SoC chip is any of the external SoC chips corresponding to the target SoC chip address indicated by the target information bit in the first transitional preset access information. Sending the first transitional preset access information corresponding to the preset access of the target SoC chip being an external SoC chip to the external SoC chip of the next SoC chip (the new SoC chip) removes the influence of the flag bit related to the current SoC chip on the preset access, so that the external SoC chip, as the next SoC chip, can determine the access path corresponding to the preset access based on the actual preset access (the first transitional preset access information corresponding to the preset access information of the preset access), so that the logic and method of the next SoC chip in determining the access path can be the same as that of the current SoC chip.
[0080] In one embodiment, the step of adding a marker bit to the first transition preset access information to characterize the target SoC chip according to the target information bit to obtain the second transition preset access information includes steps S302-S306.
[0081] S302, when the target SoC chip corresponding to the target information bit in the first transition preset access information is the SoC chip, a first flag bit is added to the first transition preset access information to obtain flag preset access information.
[0082] S304, when the target SoC chip corresponding to the target information bit in the first transition preset access information is the external SoC chip, a second flag bit is added to the first transition preset access information to obtain flag preset access information.
[0083] S306, the target information bit in the first transition preset access information is stored in a preset channel as target SoC chip information, and the target information bit in the marker preset access information is set to empty information to obtain the second transition preset access information.
[0084] Specifically, one of the first and second flag bits is set to 0, and the other to 1. These two flag bits distinguish whether the target SoC chip is an SoC chip itself or an external SoC chip. The preset channel can be used to store or retrieve information bits. It can be understood that the address space of the preset channel is greater than or equal to the number of bits in the target information bit. For example, the preset channel is the user channel within the SoC chip. By setting the target information bit in the preset access information to empty bits, the impact of the target information bit on the address mapping confirmation of the access path through the second transition preset access information is avoided. Storing the target information bit in the preset channel facilitates the subsequent recovery of the target information bit in the second transition preset access information.
[0085] In one embodiment, when the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip or the access path of the preset access corresponding to the second transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, the access path confirmation method further includes: setting the empty bit information in the second transition preset access information to the target SoC chip information according to the target SoC chip information (target information bit) in the preset channel. In this way, the first transition preset access information corresponding to the second transition preset access information can be obtained during the transmission of the second transition preset access information, and the influence of the flag bit on determining whether the access path is the remote space corresponding to the slave processor core in the SoC chip or the space in the external SoC chip can be removed.
[0086] It should be understood that although the steps in the flowchart of Figure 1 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.
[0087] Figure 2 is a schematic block diagram of an access path confirmation device in one embodiment. As shown in Figure 2, in this embodiment, an access path confirmation device is provided, which is applied to a SoC chip 100. The SoC chip includes a plurality of main processor cores 102 and a plurality of slave processor cores 104. The access path confirmation device is the same as or corresponds to the parts in the above-described access path confirmation method, and will not be described in detail below.
[0088] The access path confirmation device includes: an address space translation module 200, a chip address translation module 300, and a determination module 400. The address space translation module 200 is connected to the main processor core 102 and is used to perform space address translation processing on the preset access information of the preset access issued by the preset main processor core to obtain first transition preset access information. The first transition preset access information includes target information bits representing the address of the target SoC chip and space information bits representing the target access address. The chip address translation module 300 is connected to the address space translation module 200 and is used to add a flag bit representing the target SoC chip to the first transition preset access information according to the target information bits to obtain second transition preset access information. The determination module 400 is connected to the chip address translation module 300 and is used to determine that the access path of the preset access points to the local space of the SoC chip when the flag bit in the second transition preset access information represents the target SoC chip as the SoC chip and the target access address represented by the space information bits corresponds to the local space address of the SoC chip.
[0089] In the aforementioned access path confirmation device, the address space translation module 200 performs space address translation processing on the preset access information of the preset access, avoiding the problem of inconsistent address bit widths between the address space of the preset access information and the address space of the target SoC chip. The chip address translation module 300 adds a flag bit representing the target SoC chip, which can be used to distinguish whether the target SoC chip is an SoC chip or an external SoC chip. The SoC chip and the external SoC chip, which is also an SoC chip, confirm the access path logic based on the flag bit and space information bit, achieving consistency between the SoC chip design in the central processing unit and the external SoC chip design, and reducing the complexity of the central processing unit architecture design. When the flag bit represents the target SoC chip as the SoC chip, and the target access address represented by the space information bit corresponds to the local space address of the SoC chip, the determination module 400 confirms that the access path of the preset access points to the local space in the SoC chip. The target information bit is not required when mapping the access address, reducing the design complexity of the address mapping. By extracting the preset access corresponding to the local space of the SoC chip, the bus loop is removed, eliminating the risk of deadlock.
[0090] In one embodiment, the determination module 400 is further configured to mark the second transitional preset access information as third transitional preset access information when the flag bit in the second transitional preset access information indicates that the target SoC chip is the SoC chip, and the target access address indicated by the spatial information bit is different from the local space address of the SoC chip; and when the target SoC chip address indicated by the target information bit in the first transitional preset access information corresponding to the third transitional preset access information corresponds to the SoC chip address, determine that the access path of the preset access corresponding to the third transitional preset access information points to the remote space corresponding to the processor core in the SoC chip. The determination module 400 distinguishes preset accesses pointing to the remote space corresponding to the processor core in the SoC chip according to the target information bit, thereby achieving the filtering of preset accesses whose access paths are the local space and remote space corresponding to the SoC chip.
[0091] In one embodiment, the determination module 400 is further configured to send the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip when the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip. By sending the first transition preset access information with the flag removed to the slave processor core in the SoC chip, the influence of human operation on the preset access is eliminated, allowing the slave processor core to determine the relationship between the access path corresponding to the preset access and the remote space of the slave processor core based on the actual preset access (the first transition preset access information obtained after spatial address translation processing of the preset access information), that is, whether the access path corresponding to the preset access is in the local space of the slave processor core or in the remote space of the slave processor core.
[0092] In one embodiment, the determination module 400 is further configured to determine that the access path of the preset access points to the external SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is an external SoC chip. The preset access corresponding to the external SoC chip can be distinguished by the flag bit, simplifying the determination step of the access path of the preset access. Here, the external SoC chip refers to any SoC chip other than the SoC chip containing the preset main processor core in the central processing unit.
[0093] In one embodiment, the determination module 400 is further configured to send the first transition preset access information corresponding to the second transition preset access information to the next SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip; wherein, the next SoC chip is any of the external SoC chips corresponding to the target SoC chip address indicated by the target information bit in the first transition preset access information. The determination module 400 sends the first transition preset access information corresponding to the preset access of the target SoC chip being an external SoC chip to the external SoC chip of the next SoC chip (the new SoC chip), removing the influence of the flag bit related to the current SoC chip on the preset access, so that the external SoC chip, as the next SoC chip, can determine the access path corresponding to the preset access based on the actual preset access (the first transition preset access information corresponding to the preset access information of the preset access), making the logic and method of the next SoC chip determining the access path the same as that of the current SoC chip.
[0094] In one embodiment, the chip address translation module 300 is configured to add a first flag bit to the first transition preset access information when the target SoC chip corresponding to the target information bit in the first transition preset access information is the SoC chip itself, to obtain marked preset access information; it is also configured to add a second flag bit to the first transition preset access information when the target SoC chip corresponding to the target information bit in the first transition preset access information is the external SoC chip, to obtain marked preset access information; the chip address translation module 300 is further configured to store the target information bit in the first transition preset access information to a preset channel as target SoC chip information, and set the target information bit in the marked preset access information to empty information, to obtain the second transition preset access information. By setting the target information bit in the marked preset access information to empty information, the influence of the target information bit on the address mapping confirmation of the access path through the second transition preset access information is avoided; by storing the target information bit in the preset channel, it is convenient to subsequently recover the target information bit in the second transition preset access information.
[0095] Figure 3 is a schematic block diagram of an access path confirmation device in another embodiment. As shown in Figure 3, in one embodiment, the access path confirmation device further includes: a chip address recovery module 500, connected to the determination module 400; wherein, the determination module 400 is further configured to mark the second transitional preset access information as third transitional preset access information when the target SoC chip represented by the marker bit in the second transitional preset access information is the SoC chip, and the target access address represented by the spatial information bit is different from the local spatial address of the SoC chip; the determination module 400 is further configured to confirm that the access path of the preset access points to the external SoC chip when the marker bit in the second transitional preset access information represents the target SoC chip as an external SoC chip, and mark the second transitional preset access information as third transitional preset access information; the chip address recovery module 500 is configured to receive the third transitional preset access information, and set the empty space information in the third transitional preset access information to the target SoC chip information according to the target SoC chip information in the preset channel, so as to obtain the first transitional preset access information corresponding to the third transitional preset access information. This method allows for the acquisition of the first transition preset access information corresponding to the second transition preset access information during the transmission of the second transition preset access information, thereby removing the influence of the flag bit on determining whether the access path is the remote space corresponding to the processor core in the SoC chip or the space in the external SoC chip.
[0096] Specific limitations regarding the access path confirmation device can be found in the limitations of the access path confirmation method described above, and will not be repeated here. Each module in the aforementioned access path confirmation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module. It should be noted that the module division in this embodiment is illustrative and only represents a logical functional division; other division methods may be used in actual implementation.
[0097] Figure 4 is a schematic diagram of a SoC chip in one embodiment. As shown in Figure 4, in this embodiment, a SoC chip is provided, including: a plurality of main processor cores 102, a plurality of slave processor cores 104, an address space translation module 106, a chip address translation module 108, and a bus network interconnection module 110; the address space translation module 106 is connected to the main processor cores 102 and is used to perform space address translation processing on the preset access information of the preset access issued by the preset main processor core to obtain first transition preset access information. The first transition preset access information includes target information bits representing the target SoC chip address and space information bits representing the target access address; chip address The conversion module 108 is connected to the address space conversion module 106 and is used to add a flag bit to the first transition preset access information to characterize the target SoC chip according to the target information bit in the received first transition preset access information, so as to obtain the second transition preset access information; the bus network interconnection module 110 is connected to the chip address conversion module and is used to determine that the access path of the preset access points to the local space in the SoC chip when the flag bit in the second transition preset access information characterizes the target SoC chip as the SoC chip and the target access address characterized by the space information bit corresponds to the local space address of the SoC chip.
[0098] Specifically, a SoC chip has multiple processors, such as a master processor and slave processors. The processor that issues the access is the master processor core, and the processor that receives the access or the access path is the slave processor core. Depending on the state of issuing or receiving the access, the master and slave processor cores can interchange. That is, for a processor in the SoC chip, it acts as the master processor core when issuing an access and as the slave processor core when receiving an access. The preset master processor core is the one that sends the preset access. The address space translation module 106 performs space address translation processing on the preset access information to obtain first transitional preset access information with the target address space. This eliminates the inconsistency in the address space bit width between the preset access information and the target access address in the target SoC chip. For example, if the preset access information is 48 bits and the target access address's address space is 64 bits, the address space translation module 106 receives the 48-bit preset access information, performs space address translation processing on the preset access information, and outputs 64-bit first transitional preset access information. By moving address space translation forward to the address space translation module 106, which precedes the bus network interconnect module 110, the logic complexity of the bus network interconnect module 110 is reduced when multiple processors in a SoC chip are accessing address mappings. This reduces path latency, decreases logic area, and effectively saves chip resources.
[0099] The chip address translation module 108, based on the target information bits in the received first transition preset access information, can determine whether the target SoC chip is the SoC chip containing the main processor core or an external SoC chip. Then, based on the determination result, it adds a flag bit to the first transition preset access information to indicate whether the target SoC chip is an SoC chip or an external SoC chip, obtaining second transition preset access information. At this time, both the SoC chip and the bus network interconnect module 110 in the subsequent external SoC chip can use the flag bits in the second transition preset access information to determine whether the target system is the current SoC chip or an external SoC chip. Then, based on the space information bits, it confirms whether to access the SoC chip's local space. The logic for confirming the preset access path is the same for both the SoC chip and the external SoC chip, achieving consistency in the design of the SoC chip in the central processing unit and the external SoC chip outside the SoC chip, simplifying the SoC chip design and reducing the complexity of the central processing unit architecture design. The bus network interconnect module 110 confirms that the preset access path points to the local space in the SoC chip based on the received second transition preset access information. The target information bits are not required when accessing the address mapping, reducing the design complexity of the address mapping. By extracting the preset access to the local space corresponding to the SoC chip, the bus loop is removed, eliminating the risk of deadlock.
[0100] In the aforementioned SoC chip, the address space translation module 106 performs space address translation processing on the preset access information of the preset access, avoiding the problem of inconsistent address bit widths between the address space of the preset access information and the address space of the target SoC chip. The chip address translation module 108 adds a flag bit representing the target SoC chip, which can be used to distinguish whether the target SoC chip is an SoC chip or an external SoC chip. The SoC chip and the external SoC chip, which is also an SoC chip, confirm that the access path logic is the same based on the flag bit and the space information bit, achieving consistency between the SoC chip design in the central processing unit and the external SoC chip design, and reducing the complexity of the central processing unit architecture design. When the flag bit represents the target SoC chip as the SoC chip, and the target access address represented by the space information bit corresponds to the local space address of the SoC chip, the bus network interconnect module 110 confirms that the access path of the preset access points to the local space in the SoC chip. The target information bit is not required when mapping the access address, reducing the design complexity of the address mapping. By extracting the preset access to the local space corresponding to the SoC chip, the bus loop is removed, eliminating the risk of deadlock.
[0101] In one embodiment, the address space translation module 106 includes a register, and the address space translation module 106 configures the high-order address in the preset access information through the register to increase the bus address of the preset access information to obtain the first transitional preset access information.
[0102] In one embodiment, the chip address translation module 108 is used to add a first flag bit to the first transition preset access information when the target SoC chip corresponding to the target information bit in the first transition preset access information is the SoC chip, and to add a second flag bit to the first transition preset access information when the target SoC chip corresponding to the target information bit in the first transition preset access information is an external SoC chip, so as to obtain marked preset access information; the chip address translation module 108 is also used to store the target information bit in the first transition preset access information to a preset channel as target SoC chip information, and set the target information bit in the marked preset access information to empty information, so as to obtain the second transition preset access information.
[0103] Specifically, one of the first and second flag bits is set to 0, and the other to 1. The bus network interconnect module 110 can distinguish whether the target SoC chip is an SoC chip or an external SoC chip based on the first and second flag bits in the second transition preset access information. The preset channel here can be used to store or retrieve information bits. It can be understood that the address space of the preset channel is greater than or equal to the number of bits of the target information bit. For example, the preset channel is a user channel in the SoC chip. By setting the target information bit in the flag preset access information to empty bits, the impact of the target information bit on the bus network interconnect module 110's address mapping confirmation of the access path through the second transition preset access information is avoided. Storing the target information bit in the preset channel facilitates subsequent recovery of the target information bit in the second transition preset access information. By temporarily storing the target information bit in the preset channel and setting the target information bit in the flag preset access information to empty bits, the second transition preset access information is obtained, reducing the complexity of the address mapping design in the bus network interconnect module 110 and achieving consistency in the design of each SoC chip in the central processing unit.
[0104] Figure 5 is a schematic diagram of a SoC chip in another embodiment. As shown in Figure 5, in one embodiment, the SoC chip further includes a chip address recovery module 112 connected to the bus network interconnect module 110. The bus network interconnect module 110 is further configured to mark the second transitional preset access information as third transitional preset access information when the target SoC chip represented by the flag bit in the second transitional preset access information is the SoC chip, and the target access address represented by the spatial information bit is different from the local spatial address of the SoC chip. The bus network interconnect module 110 is also configured to confirm that the access path of the preset access points to the external SoC chip when the flag bit in the second transitional preset access information represents the target SoC chip as an external SoC chip, and mark the second transitional preset access information as third transitional preset access information. The chip address recovery module 112 is configured to receive the third transitional preset access information, and according to the target SoC chip information in the preset channel, set the empty bit information in the third transitional preset access information to the target SoC chip information, and remove the flag bit to obtain the first transitional preset access information corresponding to the third transitional preset access information. The chip address recovery module 112 can obtain the first transition preset access information corresponding to the second transition preset access information during the transmission of the second transition preset access information, and remove the influence of the flag bit on determining whether the access path is the remote space corresponding to the processor core in the SoC chip or the space in the external SoC chip.
[0105] In one embodiment, the chip address recovery module 112 is further configured to, when the target information bit in the first transition preset access information corresponding to the third transition preset access information represents the target SoC chip address corresponding to the SoC chip address of the SoC chip, confirm that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, and send the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip. The chip address recovery module 112 removes the influence of the flag bit (manual operation) added by the chip address translation module 108 on the preset access, so that the slave processor core can determine the relationship between the access path corresponding to the preset access and the remote space of the slave processor core based on the actual preset access (the first transition preset access information obtained after spatial address translation processing of the preset access information), that is, whether the access path corresponding to the preset access is the local space of the slave processor core or the remote space of the slave processor core.
[0106] In one embodiment, the chip address recovery module 112 is further configured to send the first transition preset access information corresponding to the third transition preset access information to the next SoC chip when the target information bit in the first transition preset access information corresponding to the third transition preset access information corresponds to the external SoC chip; wherein, the next SoC chip is any of the external SoC chips corresponding to the target SoC chip address represented by the target information bit in the first transition preset access information. The chip address recovery module 112 removes the influence of the flag bit (manual operation) related to the current SoC chip added by the chip address translation module 108 on the preset access, so that the external SoC chip, as the next SoC chip, can determine the access path corresponding to the preset access based on the actual preset access (the first transition preset access information corresponding to the preset access information of the preset access), so that the logic and method of the next SoC chip in determining the access path can be the same as that of the current SoC chip.
[0107] As shown in Figure 5, in one embodiment, the SoC chip includes the same number of address space translation modules 106 and chip address translation modules 108. Each address space translation module 106 corresponds one-to-one with a main processor core 102, meaning each main processor core 102 has its own independent address space translation module 106 and chip address translation module 108. No two main processor cores 102 are simultaneously connected to one address space translation module 106, nor is one main processor core 102 simultaneously connected to two address space translation modules 106. The output terminals of the chip address translation modules 108 of different main processor cores 102 are connected to different input terminals of the bus network interconnect module 110. The number of input terminals of the bus network interconnect module 110 is greater than or equal to the number of main processor cores 102. In this case, the preset access sent by the main processor core 102 undergoes address space translation individually, achieving the purpose of simultaneously confirming the access paths of multiple preset accesses. For example, the bus network interconnect module 110 includes a bus interconnect (BUS) for transmitting bus interconnect data information and performing address mapping. It solves the drawback of listing addresses space by space when mapping multiple SoC chips, and at the same time makes the design of all SoC chips consistent, without the need to customize the corresponding bus network interconnect module 110 space mapping method according to the SoC chip address of different SoC chips.
[0108] Figure 6 is a schematic diagram of a central processing unit in one embodiment. As shown in Figure 6, this disclosure also provides a central processing unit 10, which includes a plurality of SoC chips 100 as described above.
[0109] For example, the central processing unit 10 includes multiple SoC chips 100. The following description uses the central processing unit shown in FIG6 as an example to illustrate the confirmation of the access path. The main processor core 102 includes multiple main processors, the slave processor core 104 includes multiple slave processors, the bus network interconnect module 110 is a bus interconnect, the address space of the main processors is 48-bit, the address space of the slave processors is 64-bit, and the local space includes some 48-bit accessible devices. The main processor core 102, several slave processor cores 104, the address space translation module 106, the chip address translation module 108, the bus network interconnect module 110, and the chip address recovery module 112 in the central processing unit 10 are all interconnected via an AXI interface for information transmission. After the preset main processor core in the main processor core 102 issues the preset access information (48-bit bus address, addr[47:0]), the address space translation module 106 performs space address translation processing on the preset access information (48-bit bus address), converting the preset access information (48-bit bus address) into first transition preset access information (64-bit bus address). The high-order address is configured through registers. The address space translation module 106 is implemented using combinational logic, only changing the bus address, changing the 48-bit address to a 64-bit address. The first transition preset access information (64-bit address, addr[63:0]) includes target information bits (die_id) representing the target SoC chip address and space information bits representing the target access address. For example, addr[63:59] is... The target information bits, addr[58:0] are spatial information bits. The chip address translation module 108 adds a flag bit (e.g., the flag bit is 1 bit, represented by addr
[64] ) to the first transition preset access information (64-bit address) based on the target information bits (addr[63:59]) received in the first transition preset access information (64-bit address, addr[63:0]) to represent the target SoC chip, and obtains the flag preset access information (65-bit address, addr[64:0]). For example, when the target SoC chip is the SoC chip where the main processor is located, addr
[64] = 0; when the target SoC chip is another SoC chip in the central processing unit (external SoC chip), addr
[64] = 1; when it is the SoC chip where it is located, addr
[64] = 0.Simultaneously, the chip address translation module 108 stores the target information bits addr[63:59] in the first transition preset access information (64-bit address) in the user channel as the target SoC chip information user[4:0], and sets the target information bits addr[63:59] in the preset access information (65-bit address) to empty bits, for example, addingr[63:59] = 0, to obtain the second transition preset access information (65-bit address, addr[64:0]); the bus network interconnection module 110 (interconnection BUS) uses a 65-bit address input and receives the second transition preset access information (65-bit address, addr[64:0]). After the address (addr[64:0]), the second transitional preset access information (65-bit address, addr[64:0]) that indicates the target SoC chip is a SoC chip and the target access address represented by the space information bit corresponds to the local space address of the SoC chip is mapped to the local space of the SoC chip, that is, the part of the space where addr
[64] =0 is processed is mapped to the local space of the SoC chip; the bus network interconnection module 110 (interconnection BUS) also maps the target SoC chip represented by the flag bit in the second transitional preset access information as the SoC chip (addr
[64] =0) When the target access address represented by the spatial information bit is different from the local spatial address of the SoC chip, or when the target SoC chip represented by the flag bit in the second transition preset access information is an external SoC chip (addr
[64] = 1, cross-SoC chip preset access), the second transition preset access information is sent to the chip address recovery module 112. The chip address recovery module 112 removes the flag bit (addr
[64] ) in the second transition preset access information, that is, removes the flag bit from the received address bus, and sets the second transition preset access information according to the target SoC chip information user[4:0]. The addr[63:59] of the query information is set to the corresponding target SoC chip information to obtain the first transition preset access information, which is then mapped to the Mesh (wireless mesh network) interconnection network and passed to the corresponding target object through the Mesh. That is, when the target SoC chip address represented by the target information bit in the first transition preset access information corresponds to the SoC chip address of the SoC chip, the first transition preset access information is sent to the slave processor core in the SoC chip; when the target SoC chip represented by the target information bit in the first transition preset access information is an external SoC chip, the first transition preset access information is sent to the next SoC chip. This solves the drawback of listing the addresses of multiple SoC chips space by space, while ensuring that the design of all SoC chips remains consistent, eliminating the need to customize the corresponding interconnection BUS space mapping method according to different die_ids.
[0110] This disclosure also provides a computer device, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the verification method as described in any of the preceding claims.
[0111] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the verification method as described in any of the preceding claims.
[0112] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.
[0113] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0114] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0115] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A method for confirming an access path, characterized in that, This method is applied to a System-on-a-Chip (SoC) chip, which includes several main processor cores and several slave processor cores. The confirmation method includes: performing spatial address translation processing on preset access information issued by a preset main processor core to obtain first transitional preset access information. The first transitional preset access information includes target information bits representing the address of the target SoC chip and spatial information bits representing the target access address. Based on the target information bits, a flag bit representing the target SoC chip is added to the first transitional preset access information to obtain second transitional preset access information. When the flag bit in the second transitional preset access information represents the target SoC chip as the SoC chip, and the target access address represented by the spatial information bits corresponds to the local spatial address of the SoC chip... When the address is specified, the access path of the preset access is confirmed to point to the local space in the SoC chip; it also includes: when the flag bit in the second transition preset access information indicates that the target SoC chip is the SoC chip, and the target access address indicated by the space information bit is different from the local space address of the SoC chip, the second transition preset access information is marked as third transition preset access information; when the target SoC chip address indicated by the target information bit in the first transition preset access information corresponding to the third transition preset access information corresponds to the SoC chip address, the access path of the preset access corresponding to the third transition preset access information is confirmed to point to the remote space corresponding to the slave processor core in the SoC chip.
2. The confirmation method according to claim 1, characterized in that, After confirming that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, the method further includes: sending the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip.
3. The confirmation method according to claim 1, characterized in that, The confirmation method further includes: when the flag bit in the second transition preset access information indicates that the target SoC chip is an external SoC chip, confirming that the access path of the preset access points to the external SoC chip.
4. The confirmation method according to claim 3, characterized in that, Also includes: When the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip, the first transition preset access information corresponding to the second transition preset access information is sent to the next SoC chip; wherein, the next SoC chip is any of the external SoC chips corresponding to the address of the target SoC chip indicated by the target information bit in the first transition preset access information.
5. The confirmation method according to claim 1, characterized in that, The step of adding a marker bit to the first transition preset access information to characterize the target SoC chip based on the target information bit to obtain the second transition preset access information includes: when the target SoC chip corresponding to the target information bit in the first transition preset access information is the SoC chip, adding a first marker bit to the first transition preset access information to obtain marker preset access information; when the target SoC chip corresponding to the target information bit in the first transition preset access information is an external SoC chip, adding a second marker bit to the first transition preset access information to obtain marker preset access information; storing the target information bit in the first transition preset access information to a preset channel as target SoC chip information, and setting the target information bit in the marker preset access information to empty information to obtain the second transition preset access information.
6. The confirmation method according to claim 5, characterized in that, When the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip or the access path of the preset access corresponding to the second transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, the confirmation method further includes: setting the empty space information in the second transition preset access information to the target SoC chip information according to the target SoC chip information in the preset channel.
7. A SoC chip, characterized in that, include: Several main processor cores; Several from processor cores; The address space translation module is connected to the main processor core and is used to perform space address translation processing on the preset access information of the preset access issued by the preset main processor core to obtain the first transition preset access information. The first transition preset access information includes target information bits representing the target SoC chip address and space information bits representing the target access address. A chip address translation module, connected to the address space translation module, is used to add a marker bit to the first transition preset access information to characterize the target SoC chip according to the target information bit, so as to obtain the second transition preset access information; A bus network interconnect module, connected to the chip address translation module, is used to determine that the access path of the preset access points to the local space of the SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is the SoC chip and the target access address indicated by the spatial information bit corresponds to the local space address of the SoC chip; the chip address translation module is used to add a first flag bit to the first transition preset access information when the target SoC chip corresponding to the target information bit in the first transition preset access information is the SoC chip, and to add a second flag bit to the first transition preset access information when the target SoC chip corresponding to the target information bit in the first transition preset access information is an external SoC chip, so as to obtain marked preset access information; the chip address translation module is also used to store the target information bit in the first transition preset access information to a preset channel as target SoC chip information, and set the target information bit in the marked preset access information to empty information, so as to obtain the second transition preset access information.
8. The SoC chip according to claim 7, characterized in that, The address space translation module includes a register. The address space translation module configures the high-order address in the preset access information through the register to increase the bus address of the preset access information to obtain the first transitional preset access information.
9. The SoC chip according to claim 7, characterized in that, Also includes: A chip address recovery module is connected to the bus network interconnect module. The bus network interconnect module is further configured to mark the second transitional preset access information as third transitional preset access information when the target SoC chip represented by the flag bit in the second transitional preset access information is the SoC chip, and the target access address represented by the spatial information bit is different from the local spatial address of the SoC chip. It is also configured to confirm that the access path of the preset access points to the external SoC chip when the flag bit in the second transitional preset access information represents an external SoC chip, and to mark the second transitional preset access information as third transitional preset access information when the target SoC chip is an external SoC chip. The chip address recovery module receives the third transitional preset access information and, based on the target SoC chip information in the preset channel, sets the empty bit information in the third transitional preset access information to the target SoC chip information to obtain the first transitional preset access information corresponding to the third transitional preset access information.
10. The SoC chip according to claim 7, characterized in that, The chip address recovery module is further configured to, when the target SoC chip address represented by the target information bit in the first transition preset access information corresponding to the third transition preset access information corresponds to the SoC chip address of the SoC chip, confirm that the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip, and send the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip.
11. The SoC chip according to claim 10, characterized in that, The chip address recovery module is further configured to send the first transition preset access information corresponding to the third transition preset access information to the next SoC chip when the target SoC chip corresponding to the target information bit in the first transition preset access information corresponding to the third transition preset access information is the external SoC chip; wherein, the next SoC chip is any of the external SoC chips corresponding to the address of the target SoC chip represented by the target information bit in the first transition preset access information.
12. A central processing unit, characterized in that, It includes several SoC chips as described in any one of claims 7-11.
13. A device for confirming access paths, characterized in that, This invention relates to a System-on-a-Chip (SoC) chip, which includes several main processor cores and several slave processor cores. The verification device includes: an address space translation module connected to the main processor cores, used to perform address space translation processing on preset access information issued by a preset main processor core to obtain first transitional preset access information, the first transitional preset access information including target information bits representing the address of the target SoC chip and space information bits representing the target access address; a chip address translation module connected to the address space translation module, used to add a flag bit representing the target SoC chip to the first transitional preset access information according to the target information bits to obtain second transitional preset access information; and a determination module connected to the chip address translation module, used to determine whether the flag bit in the second transitional preset access information represents the target SoC chip as the SoC chip, and whether the target SoC chip is indeed the SoC chip. When the target access address represented by the spatial information bit corresponds to the local space address of the SoC chip, the determination module is further configured to mark the second transitional preset access information as third transitional preset access information when the flag bit in the second transitional preset access information represents the target SoC chip as the SoC chip, and the target access address represented by the spatial information bit is different from the local space address of the SoC chip; and when the target SoC chip address represented by the target information bit in the first transitional preset access information corresponding to the third transitional preset access information corresponds to the SoC chip address, the determination module is configured to determine that the access path of the preset access corresponding to the third transitional preset access information points to the remote space corresponding to the slave processor core in the SoC chip.
14. The verification device according to claim 13, characterized in that, The determination module is further configured to send the first transition preset access information corresponding to the third transition preset access information to the slave processor core in the SoC chip when the access path of the preset access corresponding to the third transition preset access information points to the remote space corresponding to the slave processor core in the SoC chip.
15. The verification device according to claim 13, characterized in that, The determination module is further configured to determine that the access path of the preset access points to the external SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is an external SoC chip.
16. The confirmation device according to claim 15, characterized in that, The determination module is further configured to send the first transition preset access information corresponding to the second transition preset access information to the next SoC chip when the flag bit in the second transition preset access information indicates that the target SoC chip is the external SoC chip; wherein, the next SoC chip is any of the external SoC chips corresponding to the address of the target SoC chip indicated by the target information bit in the first transition preset access information.
17. A computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the verification method as described in any one of claims 1-6.
18. A computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the verification method as described in any one of claims 1-6.
Citation Information
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High-density multiprocessor system and node controller
CN101908036A