Display panel

Abstract

The application discloses a display panel; the display panel comprises a display area and a non-display area adjacent to the display area; the display panel further comprises a panel main body; the panel main body comprises a first input signal end, a second input signal end, a first input signal line, a second input signal line arranged in the non-display area and a first gate drive circuit arranged in the non-display area and located at one side of the display area; the first input signal line is connected between the first gate drive circuit and the first input signal end, and the second input signal line is connected between the first gate drive circuit and the second input signal end; wherein the voltage loaded on the first input signal end is the same as the voltage loaded on the second input signal end; the application can improve the stability of the voltage signal of the first input signal line and the second input signal line into the first gate drive circuit, improve the stability of the scanning signal output by the first gate drive circuit, and further improve the display uniformity and display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] In display panels, the Gate Driver On Array (GOA) technology generates scanning signals through the GOA circuit and transmits the scanning signals to the pixel driving circuit in the plane to realize the emission of pixels in the plane.

[0003] The GOA circuit scans line by line to transmit scan signals to the pixel driving circuit of the corresponding line. For example, multiple GOA units in the GOA circuit all input low-potential signals through low-potential scan signal lines. When the pixel driving circuit of the current line is supplied with a low-potential signal, while the pixel driving circuits of other lines are charged with high-potential scan signals, the load on the low-potential scan signal lines will decrease, causing the potential in the low-potential scan signal lines to increase. This will affect the signal stability in the pixel driving circuit, resulting in uneven display on the display panel. Summary of the Invention

[0004] This invention provides a display panel that can improve the stability of signal transmission in the first input signal line and the second input signal line, thereby improving the display uniformity of the display panel.

[0005] This invention provides a display panel, which includes a display area and a non-display area adjacent to the display area;

[0006] The display panel also includes:

[0007] The panel body includes a first input signal terminal, a second input signal terminal, a first input signal line, a second input signal line disposed in the non-display area, and a first gate driving circuit disposed in the non-display area and located on one side of the display area;

[0008] The first input signal line is connected between the first gate driving circuit and the first input signal terminal, and the second input signal line is connected between the first gate driving circuit and the second input signal terminal;

[0009] The voltage applied to the first input signal terminal is the same as the voltage applied to the second input signal terminal.

[0010] In one embodiment of the present invention, the first gate driving circuit is disposed on a first side of the panel body, the first input signal terminal is disposed on a second side of the panel body, the second input signal terminal is disposed on a third side of the panel body, and the second side and the third side are opposite sides of the panel body, with the first side located between the second side and the third side.

[0011] In one embodiment of the present invention, the first gate driving circuit includes a plurality of first gate control units, the first input signal line is connected to a portion of the plurality of first gate control units near the second side, the second input signal line is connected to another portion of the plurality of first gate control units near the third side, and the first input signal line and the second input signal line are connected in the first gate driving circuit.

[0012] In one embodiment of the present invention, the display panel further includes a first flexible circuit board and a second flexible circuit board connected to the panel body, wherein the first flexible circuit board is bound to the first input signal terminal and the second flexible circuit board is bound to the second input signal terminal.

[0013] In one embodiment of the present invention, the display panel further includes a first circuit board connected to the side of the first flexible circuit board away from the panel body, and a first connection trace disposed on the first flexible circuit board and the first circuit board. A first driver chip is disposed on the first circuit board, and the first connection trace is connected between the first driver chip and the first input signal terminal.

[0014] In one embodiment of the present invention, the display panel further includes a third flexible circuit board connected between the first flexible circuit board and the second flexible circuit board, and a second connection trace located on the first circuit board, the second flexible circuit board and the third flexible circuit board, wherein the second connection trace is connected between the first driver chip and the second input signal terminal.

[0015] In one embodiment of the present invention, the display panel further includes a second circuit board connected to the side of the second flexible circuit board away from the panel body, and a third connection trace disposed on the second circuit board and the second flexible circuit board. A second driver chip is disposed on the second circuit board, and the third connection trace is connected between the second input signal terminal and the second driver chip.

[0016] In one embodiment of the present invention, the panel body includes a source / drain layer and a gate layer;

[0017] The first input signal line includes a plurality of first segments, each of which is independently located in the source / drain layer or the gate layer;

[0018] The second input signal line includes a plurality of second segments, each of which is independently located in the source / drain layer or the gate layer.

[0019] In one embodiment of the present invention, the panel body further includes a plurality of pixel driving circuits disposed in the display area, and an output signal line connected between the first gate driving circuit and the pixel driving circuit, wherein the output signal line is used to transmit the signals in the first input signal line and the second input signal line to the pixel driving circuit;

[0020] The pixel driving circuit includes a driving transistor and a compensation transistor. The first terminal of the driving transistor and the first terminal of the compensation transistor are both connected to a first node. The gate of the driving transistor and the second terminal of the compensation transistor are both connected to a second node. The output signal line is connected to the gate of the compensation transistor.

[0021] In one embodiment of the present invention, the compensation transistor is an N-type thin-film transistor, and the voltage applied to the first input signal terminal and the voltage applied to the second input signal terminal are both at a low level.

[0022] The beneficial effects of the present invention are as follows: By adding a second input signal terminal to the panel body, and the voltage applied to the second input signal terminal is the same as the voltage applied to the first input signal terminal, the present invention can improve the stability of the voltage signals of the first input signal line and the second input signal line entering the first gate driving circuit, improve the stability of the scanning signal output by the first gate driving circuit, and thus improve the display uniformity and display effect of the display panel. Attached Figure Description

[0023] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of a planar structure of a display panel in related technologies;

[0025] Figure 2 This is a schematic diagram of signal transmission in a display panel in related technologies;

[0026] Figures 3 to 5 This is a waveform diagram of the display panel in related technologies;

[0027] Figure 6 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0029] Figure 8 This invention provides a signal waveform diagram in a panel body;

[0030] Figure 9 and Figure 10 This is a schematic diagram of a circuit structure of a first gate control unit provided in an embodiment of the present invention;

[0031] Figure 11 A schematic diagram of signal transmission for a panel body provided in an embodiment of the present invention;

[0032] Figure 12 This is a schematic diagram of a signal transmission resistor structure in related technologies;

[0033] Figure 13 This is a schematic diagram of a signal transmission resistor structure provided in an embodiment of the present invention;

[0034] Figure 14 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention;

[0035] Figure 15 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0037] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0038] Please refer to Figures 1 to 5In the related technology display panel, the display panel includes a panel body 1, a flexible circuit board 2 bonded to the panel body 1, and a circuit board 3 connected to the flexible circuit board 2 on the side away from the panel body 1. The signal on the circuit board 3 is transmitted to the bonding terminal 4 through the flexible circuit board 3, and then to the GOA driving circuit 5 through the bonding terminal 4. Then, the driving circuit 5 transmits the signal to the pixel driving circuit 6. For example, when the transmitted signal is a low-level signal VGL, and there can be multiple low-level signals, such as VGL1 / VGL2, the bonding terminal 4 transmits the low-level signal to the GOA driving circuit 5 through traces. The GOA driving circuit 5 includes multiple cascaded units, and each cascaded unit is connected to a row of pixel driving circuits 6. The driving process of the pixel driving circuit 6 includes a data writing period T1 and a hold period T2. During the holding period T2, and within the data writing period T1, the low-level signal VGL needs to switch to a high level to turn on the preset transistor in the preset pixel driving circuit 6. During the holding period T2, the low-level signal VGL needs to remain at a low level to keep the preset transistor off. Therefore, when the pixel driving circuit 6 of this row is at the end of the holding period T2, the pixel driving circuit 6 of other rows will be in the data writing period T1. At this time, the low-level signal VGL of other rows switches to a high level, which reduces the load of the low-level signal VGL. The low-level signal VGL will be pulled up, that is, an upward sharp angle will appear, which will affect the signal transmission stability of the pixel driving circuit 6 of this row. This will cause the brightness of the light-emitting device driven by the pixel driving circuit 6 of this row to change, resulting in uneven display phenomena such as flickering on the display panel.

[0039] Please refer to Figure 6 This invention provides a display panel, which includes a display area 101 and a non-display area 102 adjacent to the display area 101; the display panel also includes a panel body 10.

[0040] The panel body 10 includes a first input signal terminal 121, a second input signal terminal 122, a first input signal line 131, a second input signal line 132, and a first gate driving circuit 11 disposed in the non-display area 102 and located on one side of the display area 101; the first input signal line 131 is connected between the first gate driving circuit 11 and the first input signal terminal 121, and the second input signal line 132 is connected between the first gate driving circuit 11 and the second input signal terminal 122.

[0041] The voltage applied to the first input signal terminal 121 is the same as the voltage applied to the second input signal terminal 122.

[0042] In the implementation process, the embodiments of the present invention add a second input signal terminal 122 to the panel body 10, and the voltage applied to the second input signal terminal 122 is the same as the voltage applied to the first input signal terminal 121. This can improve the stability of the voltage signals of the first input signal line 131 and the second input signal line 132 entering the first gate driving circuit 11, improve the stability of the scanning signal output by the first gate driving circuit 11, and thus improve the display uniformity and display effect of the display panel.

[0043] Specifically, please continue to refer to Figure 6 The display panel includes a display area 101 and a non-display area 102, with the non-display area 102 surrounding the display area 101.

[0044] The display panel also includes a panel body 10, a first flexible circuit board 21, a second flexible circuit board 22, and a first circuit board 31.

[0045] The panel body 10 includes a plurality of pixel driving circuits 15 disposed in the display area 101 and a first gate driving circuit 11 disposed in the non-display area 102.

[0046] Furthermore, the panel body 10 includes a first input signal terminal 121, a second input signal terminal 122, a first input signal line 131, and a second input signal line 132. The first input signal line 131 is connected between the first input signal terminal 121 and the first gate driving circuit 11, and the second input signal line 132 is connected between the second input signal terminal 122 and the second gate driving circuit 14. The first flexible circuit board 21 is bonded to the first input signal terminal 121, and the second flexible circuit board 22 is bonded to the second input signal terminal 122. The voltage applied to the first input signal terminal 121 is the same as the voltage applied to the second input signal terminal 122.

[0047] In one embodiment, a first gate driving circuit 11 is disposed on a first side 1011 of the panel body 10, a first input signal terminal 121 is disposed on a second side 1012 of the panel body 10, and a second input signal terminal 122 is disposed on a third side 1013 of the panel body 10. The second side 1012 and the third side 1013 are opposite sides of the panel body 10, and the first side 1011 is located between the second side 1012 and the third side 1013.

[0048] The first gate driving circuit 11 includes a plurality of first gate control units 111. In one embodiment, the plurality of first gate control units 111 are arranged along a first direction M, where the first direction M is the direction from the second side 1012 to the third side 1013. A first input signal line 131 is connected to a portion of the plurality of first gate control units 111 that is closer to the second side 1012. A second input signal line 132 is connected to another portion of the plurality of first gate control units 111 that is closer to the third side 1013. The first input signal line 131 and the second input signal line 132 are connected in the first gate driving circuit 11, thereby enabling the first input signal line 131 and the second input signal line 132 to jointly input signals to the first gate driving circuit 11.

[0049] The panel body 10 also includes an output signal line 16, which is connected between the first gate driving circuit 11 and the pixel driving circuit 15. The output signal line 16 is used to transmit the signals in the first input signal line 131 and the second input signal line 132 to the pixel driving circuit 15.

[0050] In one embodiment, a plurality of pixel driving circuits 15 are arranged in the display area 101 along a first direction M and a second direction N. A first gate control unit 111 transmits a signal to the plurality of pixel driving circuits 15 arranged along the second direction N through an output signal line 16. The second direction N intersects with the first direction M. Preferably, the first direction M and the second direction N are perpendicular to each other.

[0051] In one embodiment, the panel body 10 further includes a fourth side 1014 disposed opposite to the first side 1011 and a second gate driving circuit 14 disposed on the fourth side 1014 of the panel body 10. The second gate driving circuit 14 includes a plurality of second gate control units 141 arranged along the first direction M. It is understood that the first gate driving circuit 11 and the second gate driving circuit 14 are located on opposite sides of the panel body 10. The circuit structure and signal transmission method of the first gate driving circuit 11 and the second gate driving circuit 14 are the same. Therefore, in this embodiment of the invention, the circuit structure and signal transmission method of the first gate driving circuit 11 are described as an example, and the circuit structure and signal transmission method of the second gate driving circuit 14 can be set with reference to the first gate driving circuit 11. The first gate driving circuit 11 and the second gate driving circuit 14 can be symmetrically arranged with respect to the display area 101.

[0052] In one embodiment, a first gate control unit 111 and a second gate control unit 141 jointly drive a plurality of pixel driving circuits 15 arranged along the second direction N through an output signal line 16.

[0053] In this embodiment of the invention, signals are transmitted to the first input signal terminal 121 and the second input signal terminal 122 via the first flexible circuit board 21 and the second flexible circuit board 22, respectively. The voltage applied to the first input signal terminal 121 is the same as the voltage applied to the second input signal terminal 122. Then, the signals are transmitted to the first gate driving circuit 11 via the first input signal line 131 and the second input signal line 132, respectively. Finally, the signals are transmitted to the pixel driving circuit 15 via the first gate driving circuit 11 to perform scanning driving on the pixel driving circuit 15. That is, this embodiment of the invention uses two flexible circuit boards and two input signal terminals for signal input, relative to... Figure 1 According to the related technologies shown, the stability of signal transmission and the ability to recover after fluctuations can be improved. Even if the load of signal transmission changes, the embodiments of the present invention can reduce the magnitude of voltage fluctuations caused by load changes and improve the uneven display phenomenon of the display panel.

[0054] Specifically, please combine Figure 6 and Figure 7 The pixel driving circuit 15 includes a light-emitting device, a driving transistor T01, a switching transistor T02, a compensation transistor T03, a first reset transistor T04, a first light-emitting control transistor T05, a second light-emitting control transistor T06, a second reset transistor T07, a third reset transistor T08, a first capacitor Cst, and a second capacitor Cboost.

[0055] The first terminal of the driving transistor T01 is connected to the first node B, the gate of the driving transistor T01 is connected to the second node Q, and the second terminal of the driving transistor T01 is connected to the third node A.

[0056] The first terminal of the first switching transistor T02 is connected to the data signal Data, the gate of the first switching transistor T02 is connected to the first scan signal Pscan, and the second terminal of the first switching transistor T02 is connected to the third node A.

[0057] The first terminal of the compensation transistor T03 is connected to the first node B, the gate of the compensation transistor T03 is connected to the second scan signal NscanT3, and the second terminal of the compensation transistor T03 is connected to the second node Q.

[0058] The first terminal of the first reset transistor T04 is connected to the first reset signal Vi_G, the gate of the first reset transistor T04 is connected to the third scan signal NscanT4, and the second terminal of the first reset transistor T04 is connected to the second node Q.

[0059] The first terminal of the first light-emitting control transistor T05 is connected to the first power supply signal VDD, the gate of the first light-emitting control transistor T05 is connected to the light-emitting control signal EM, and the second terminal of the first light-emitting control transistor T05 is connected to the third node A.

[0060] The first terminal of the second light-emitting control transistor T06 is connected to the first node B, the gate of the second light-emitting control transistor T06 is connected to the light-emitting control signal EM, and the second terminal of the second light-emitting control transistor T06 is connected to the fourth node C.

[0061] The first terminal of the second reset transistor T07 is connected to the second reset signal Vi_ANo, the gate of the second reset transistor T07 is connected to the fourth scan signal PScan2, and the second terminal of the second reset transistor T07 is connected to the fourth node C.

[0062] The first terminal of the third reset transistor T08 is connected to the third reset signal Vi_T8, the gate of the third reset transistor T08 is connected to the fourth scan signal PScan2, and the second terminal of the third reset transistor T08 is connected to the third node A.

[0063] The first electrode of the light-emitting device is connected to the fourth node C, and the second electrode of the light-emitting device is connected to the second power supply signal VSS.

[0064] The first capacitor Cst is connected between the second node Q and the third node A, and the second capacitor Cboost is connected between the second node Q and the first scan signal PScan.

[0065] It should be noted that, in this embodiment of the invention, the compensation transistor T03 can be an N-type thin-film transistor, and the voltage applied to the first input signal terminal 121 and the voltage applied to the second input signal terminal 122 are both at low levels; the signals transmitted in the first input signal line 131 and the second input signal line 132 can be transmitted to the gate of the compensation transistor T03 through the first gate control unit 111, which can make the compensation transistor T03 turn off. Since there is a parasitic capacitance between the gate of the compensation transistor T03 and the gate of the driving transistor T01, when the gate potential of the compensation transistor T03 fluctuates, it will affect the gate potential of the driving transistor T01. The coupling effect causes a change in the potential of the driving transistor T01. For example, when the pixel driving circuit 15 of this row is at the end of the holding period, the pixel driving circuits 15 of other rows are in the data writing period. This leads to a decrease in the load on the first input signal line 131 and the second input signal line 132, causing the potential in the first input signal line 131 and the second input signal line 132 to rise and form a sharp angle. This, in turn, causes the potential of the driving transistor T01 to also change due to coupling, resulting in a decrease in the brightness of the pixels in this row. This causes a change in the brightness of the pixels in this row during the holding period, i.e., a decrease in brightness at the end, resulting in a flickering phenomenon on the display panel. However, please combine with... Figure 6 , Figure 7 as well as Figure 8In this embodiment of the invention, by simultaneously inputting low-level signals through the first input signal line 131 and the second input signal line 132, the stability of signal transmission and the recovery capability after fluctuations can be improved. Even if the load of signal transmission changes, this embodiment of the invention can reduce the magnitude of voltage fluctuations caused by load changes. Figure 1 According to the related technology shown, the sharp angle A generated by the voltage NscanT3 on the gate of the compensation transistor T03 can be reduced to a sharp angle a, which effectively reduces the potential fluctuation of the gate of the compensation transistor T03, improves the signal transmission stability and the display uniformity of the display panel.

[0066] Furthermore, such as Figure 9 The first gate control unit 111 provided by the present invention includes a signal control unit 41 and a signal generation unit 42. The signal generation unit 42 can be connected to a high-level signal NVGH_T3 and a low-level signal NVGL_T3, and outputs the high-level signal NVGH_T3 to the signal output terminal NscanT3_out under the control of the high-level transistor TH, or outputs the high-level signal NVGL_T3 to the signal output terminal NscanT3_out under the control of the low-level transistor TL. The signal output terminal NscanT3_out can be connected to the gate of the compensation transistor T03 through the output signal line 16. The signal control unit 41 is connected to the gate of the high-level transistor TH and the gate of the low-level transistor TL, so as to turn on the high-level transistor TH or the low-level transistor TL according to the control of various clock signals.

[0067] In one embodiment, such as Figure 10 As shown in the figure, an embodiment of the present invention provides a first gate control unit 111 with a 16T3C architecture, wherein the first gate control unit 111 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0068] In this configuration, the first terminal of the first transistor T1 is connected to the low-level signal VGL, the gate of the first transistor T1 is connected to the first node N1, and the second terminal of the first transistor T1 is connected to the signal output terminal OUT.

[0069] The first terminal of the second transistor T2 is connected to the high-level signal VGH, the gate of the second transistor T2 is connected to the second node N2, and the second terminal of the second transistor T2 is connected to the signal output terminal OUT.

[0070] The first terminal of the third transistor T3 is connected to the first node N1, the gate of the third transistor T3 is connected to the low-level signal VGL, and the second terminal of the third transistor T3 is connected to the third node N3.

[0071] The first terminal of the fourth transistor T4 is connected to the first node N1, the gate of the fourth transistor T4 is connected to the first capacitor C1, and the second terminal of the fourth transistor T4 is connected to the fourth node N4.

[0072] The first terminal of the fifth transistor T5 is connected to the fourth node N4, the gate of the fifth transistor T5 is connected to the low-level signal VGL, and the second terminal of the fifth transistor T5 is connected to the fifth node N5.

[0073] The first terminal of the sixth transistor T6 is connected to the control signal IN, the gate of the sixth transistor T6 is connected to the first clock signal CK, and the second terminal of the sixth transistor T6 is connected to the fifth node N5.

[0074] The first terminal of the seventh transistor T7 is connected to the control signal IN, the gate of the seventh transistor T7 is connected to the first clock signal CK, and the second terminal of the seventh transistor T7 is connected to the third node N3.

[0075] The first terminal of the eighth transistor T8 is connected to the low-level signal VGL, the gate of the eighth transistor T8 is connected to the first clock signal CK, and the second terminal of the eighth transistor T8 is connected to the sixth node N6.

[0076] The first terminal of the ninth transistor T9 is connected to the second clock signal XCK, the gate of the ninth transistor T9 is connected to the fourth node N4, and the second terminal of the ninth transistor T9 is connected to the seventh node N7.

[0077] The first terminal of the tenth transistor T10 is connected to the first clock signal CK, the gate of the tenth transistor T10 is connected to the third node N3, and the second terminal of the tenth transistor T10 is connected to the sixth node N6; and the tenth transistor T10 can be a dual-gate transistor.

[0078] The first terminal of the eleventh transistor T11 is connected to the high-level signal VGH, the gate of the eleventh transistor T11 is connected to the sixth node N6, and the second terminal of the eleventh transistor T11 is connected to the seventh node N7.

[0079] The first terminal of the twelfth transistor T12 is connected to the high-level signal VGH, the gate of the twelfth transistor T12 is connected to the third node N3, and the second terminal of the twelfth transistor T12 is connected to the second node N2.

[0080] The first terminal of the thirteenth transistor T13 is connected to the high-level signal VGH, the gate of the thirteenth transistor T13 is connected to the control signal RST, and the second terminal of the thirteenth transistor T13 is connected to the third node N3.

[0081] The first terminal of the fourteenth transistor T14 is connected to the sixth node N6, the gate of the fourteenth transistor T14 is connected to the low-level signal VGL, and the second terminal of the fourteenth transistor T14 is connected to the eighth node N8.

[0082] The first terminal of the fifteenth transistor T15 is connected to the ninth node N9, the gate of the fifteenth transistor T15 is connected to the second clock signal XCK, and the second terminal of the fifteenth transistor T15 is connected to the second node N2.

[0083] The first terminal of the sixteenth transistor T16 is connected to the second clock signal XCK, the gate of the sixteenth transistor T16 is connected to the eighth node N8, and the second terminal of the sixteenth transistor T16 is connected to the ninth node N9.

[0084] The first capacitor C1 is connected between the gate of the fourth transistor T4 and the seventh node N7, the second capacitor C2 is connected between the high-level signal VGH and the second node N2, and the third capacitor C3 is connected between the eighth node N8 and the ninth node N9.

[0085] Continuing from the above, under the control of the second node N2, the second transistor T2 transmits the high-level signal transmitted in the first input signal line 131 or the second input signal line 132 to the signal output terminal OUT, and then transmits it to the gate of the compensation transistor T03 in the pixel driving circuit 15 through the output signal line 16.

[0086] In other embodiments of the present invention, the output signal line 16 may also be connected to the gate of the first reset transistor T04 in the pixel driving circuit 15 to apply a voltage signal NscanT4 to it, and the first reset transistor T04 is an N-type thin film transistor, and the voltage signal NscanT4 is at a low level; similarly, there is a coupling capacitance between the gate of the first reset transistor T04 and the gate of the driving transistor T01. Therefore, in the embodiments of the present invention, the uneven display phenomenon of the display panel can be improved by improving the stability of the potential signal NscanT4 on the first reset transistor T04.

[0087] It should be noted that the potential signal NscanT4 is provided by the first gate drive circuit 11, and the circuit structure used to generate the potential signal NscanT4 can be the same as... Figure 8 and Figure 9 The structures shown are identical, and the specific connection methods will not be described in detail here.

[0088] Following on from above, please combine... Figure 6 , Figure 7 , Figure 11 , Figure 12 as well as Figure 13In this embodiment of the invention, a first input signal terminal 121 and a second input signal terminal 122 are provided on opposite sides of a plurality of first gate control units 111 and a plurality of second gate control units 141, so as to jointly input a voltage signal NscanT3 to the plurality of first gate control units 111 and a plurality of second gate control units 141, thereby relative to Figure 12 In the related technologies shown, the resistance of the signal transmission process is the sum of R1 and R2. The embodiments of the present invention can reduce the signal transmission path, so that the resistance of the signal transmission process in the first input signal line 131 is the sum of R1 and R2 / 2, and the resistance of the signal transmission process in the second input signal line 132 is the sum of R3 and R2 / 2, and R3 is less than R2 / 2. This can reduce the resistance of the signal transmission process. That is, the embodiments of the present invention can reduce the resistance of the voltage signal NscanT3 during transmission, improve the signal transmission efficiency and the recovery speed after fluctuations.

[0089] In addition, the third side 1013 of the panel body 10 is provided with at least one third input signal terminal 123, and power signals VDD and / or VSS can be loaded to the at least one third input signal terminal 123 through the second flexible circuit board 22. The panel body 10 also includes a third input signal line 133 connected to the third input signal terminal 123, and the third input signal line 133 is used to transmit power signals VDD and / or VSS to the pixel driving circuit 15 in the display area 101.

[0090] It should be noted that the second side 1012 of the panel body 10 is also provided with input signal terminals for loading power signals VDD and / or VSS (not shown in the figure), and power signals VDD and / or VSS are loaded to it through the first flexible circuit board 21. That is, in this embodiment of the invention, the transmission stability and resistance of power signals VDD and / or VSS can be improved by increasing the number of input terminals of power signals VDD and / or VSS, thereby improving the display effect of the display panel.

[0091] Specifically, in one embodiment of the present invention, please refer to Figure 14 The display panel also includes a first circuit board 31 connected to the side of the first flexible circuit board 21 away from the panel body 10, and a first connection trace 312 disposed on the first flexible circuit board 21 and the first circuit board 31. A first driver chip 311 is disposed on the first circuit board 31, and the first connection trace 312 is connected between the first driver chip 311 and the first input signal terminal 121.

[0092] The display panel also includes a third flexible circuit board 23 connected between the first flexible circuit board 21 and the second flexible circuit board 22, and a second connection trace 221 located on the first circuit board 31, the second flexible circuit board 22 and the third flexible circuit board 23. The second connection trace 221 is connected between the first driver chip 311 and the second input signal terminal 122 (not shown in the figure). It can be understood that the first driver chip 311 transmits signals to the second flexible circuit board 22 through the second connection trace 221 on the third flexible circuit board 23, and the second flexible circuit board 22 is bonded to the second input signal terminal 122 to transmit signals to the second input signal terminal 122.

[0093] The voltage transmitted from the first driving chip 311 to the first connection trace 312 and the second connection trace 221 is the same, and the third flexible circuit board 23 can be disposed on the back side of the panel body 10, that is, the side of the panel body 10 away from the light-emitting surface.

[0094] Furthermore, the third flexible circuit board 23 is also provided with connection traces for transmitting power signals VDD and / or VSS, so as to transmit power signals VDD and / or VSS to the second flexible circuit board 22 through the first driver chip 311 and the third flexible circuit board 23.

[0095] In another embodiment of the present invention, please refer to Figure 15 The display panel also includes a first circuit board 31 connected to the side of the first flexible circuit board 21 away from the panel body 10, and a first connection trace 312 disposed on the first flexible circuit board 21 and the first circuit board 31. A first driver chip 311 is disposed on the first circuit board 31, and the first connection trace 312 is connected between the first driver chip 311 and the first input signal terminal 121.

[0096] The display panel also includes a second circuit board 32 connected to the side of the second flexible circuit board 22 away from the panel body 10, and a third connection trace 322 disposed on the second circuit board 32 and the second flexible circuit board 22. A second driver chip 321 is disposed on the second circuit board 32. The third connection trace 322 is connected between the second input signal terminal 122 and the second driver chip 321. The voltage transmitted by the second driver chip 321 to the second input signal terminal 122 is the same as the voltage transmitted by the first driver chip 311 to the first input signal terminal 121.

[0097] Furthermore, the second flexible circuit board 22 is also provided with connection traces for transmitting power signals VDD and / or VSS, so that the power signals VDD and / or VSS can be transmitted to the third input signal terminal 123 through the second driver chip 321 and the second flexible circuit board 22.

[0098] In one embodiment, the second driver chip 321 can be used to output the reset signal and clock signal required by the first gate drive circuit 11.

[0099] In one embodiment, please continue to refer to Figure 6 The panel body 10 includes a substrate and a source / drain layer and a gate layer disposed on the substrate; the first input signal line 131 includes a plurality of first line segments, each of which is independently located in the source / drain layer or the gate layer; for example, the non-display area 102 includes a fan-out routing area 1021 located on the second side 1012 of the panel body 10. Since there are a large number of wirings in the fan-out routing area 1021, the first line segments located in the fan-out routing area 1021 can be disposed in the gate layer where there is more wiring space, while the first line segments located in other positions can be located in the source / drain layer.

[0100] The second input signal line 132 includes a plurality of second segments, each of which is independently located in the source-drain layer or the gate layer. For example, when the second input signal line 132 overlaps with the third input signal line 133, the second segment in the overlapping part can be located in the gate layer, while the second segments in other positions can be located in the source-drain layer.

[0101] Furthermore, this embodiment of the invention provides an example and a verification of the effect of a ratio of display panels on improving display uniformity, wherein the example adopts the following... Figure 2 The signal output method shown is as follows, while the comparative method uses... Figure 11 The signal input method is shown, and the voltage signal NscanT3 is simulated to obtain the size of the sharp angle generated by the voltage signal NscanT3 in the embodiment and the comparative example. The results are shown in Table 1 below.

[0102] Table 1: Simulation Results of Voltage Signals

[0103] Example Comparative Example Size of the sharp angle in voltage signal NscanT3 10mV 3mV

[0104] As can be seen from the table above, the present invention can effectively reduce the size of the sharp angle generated by the scanning signal output by the first gate driving circuit 11 by adding a signal input terminal, thereby improving the signal transmission stability and the display uniformity of the display panel.

[0105] Continuing from the above, this embodiment of the invention adds a second input signal terminal 122 to the panel body 10, and the voltage applied to the second input signal terminal 122 is the same as the voltage applied to the first input signal terminal 121. This improves the stability of the voltage signals of the first input signal line 131 and the second input signal line 132 entering the first gate driving circuit 11, and improves the stability of the scanning signal output by the first gate driving circuit 11. This, in turn, improves the display uniformity and display effect of the display panel.

[0106] In addition, embodiments of the present invention also provide a display device, which includes the display panel described in the above embodiments.

[0107] It is understood that since the display device includes the display panel described in the above embodiments, the display device has the same beneficial effects as in the above embodiments, and will not be repeated here.

[0108] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0109] The above provides a detailed description of a display panel provided in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area adjacent to the display area; The display panel also includes: The panel body includes a first input signal terminal, a second input signal terminal, a first input signal line, a second input signal line, and a first gate driving circuit disposed in the non-display area and located on one side of the display area. The first input signal terminal is disposed on a second side of the panel body, and the second input signal terminal is disposed on a third side of the panel body. The second side and the third side are opposite sides of the panel body. The first input signal line is connected between the first gate driving circuit and the first input signal terminal, and the second input signal line is connected between the first gate driving circuit and the second input signal terminal; Wherein, the voltage applied to the first input signal terminal is the same as the voltage applied to the second input signal terminal, the first gate driving circuit includes a plurality of first gate control units, the first input signal line is connected to a portion of the plurality of first gate control units near the second side, the second input signal line is connected to another portion of the plurality of first gate control units near the third side, and the first input signal line and the second input signal line are connected in the first gate driving circuit.

2. The display panel according to claim 1, characterized in that, The first gate driving circuit is disposed on a first side of the panel body, and the first side is located between the second side and the third side.

3. The display panel according to any one of claims 1 to 2, characterized in that, The display panel further includes a first flexible circuit board and a second flexible circuit board connected to the panel body, wherein the first flexible circuit board is bound to the first input signal terminal and the second flexible circuit board is bound to the second input signal terminal.

4. The display panel according to claim 3, characterized in that, The display panel further includes a first circuit board connected to the side of the first flexible circuit board away from the panel body, and a first connection trace disposed on the first flexible circuit board and the first circuit board. A first driver chip is disposed on the first circuit board, and the first connection trace is connected between the first driver chip and the first input signal terminal.

5. The display panel according to claim 4, characterized in that, The display panel further includes a third flexible circuit board connected between the first flexible circuit board and the second flexible circuit board, and a second connection trace located on the first circuit board, the second flexible circuit board and the third flexible circuit board, wherein the second connection trace is connected between the first driver chip and the second input signal terminal.

6. The display panel according to claim 3, characterized in that, The display panel further includes a second circuit board connected to the side of the second flexible circuit board away from the panel body, and a third connection trace disposed on the second circuit board and the second flexible circuit board. A second driver chip is disposed on the second circuit board, and the third connection trace is connected between the second input signal terminal and the second driver chip.

7. The display panel according to claim 1, characterized in that, The panel body includes a source / drain layer and a gate layer; The first input signal line includes a plurality of first segments, each of which is independently located in the source / drain layer or the gate layer; The second input signal line includes a plurality of second segments, each of which is independently located in the source / drain layer or the gate layer.

8. The display panel according to claim 1, characterized in that, The panel body also includes a plurality of pixel driving circuits disposed in the display area, and an output signal line connected between the first gate driving circuit and the pixel driving circuit. The output signal line is used to transmit the signals in the first input signal line and the second input signal line to the pixel driving circuit. The pixel driving circuit includes a driving transistor and a compensation transistor. The first terminal of the driving transistor and the first terminal of the compensation transistor are both connected to a first node. The gate of the driving transistor and the second terminal of the compensation transistor are both connected to a second node. The output signal line is connected to the gate of the compensation transistor.

9. The display panel according to claim 8, characterized in that, The compensation transistor is an N-type thin-film transistor, and the voltage applied to the first input signal terminal and the voltage applied to the second input signal terminal are both at a low level.

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