Array substrate, manufacturing method thereof, and liquid crystal panel

Abstract

The application discloses an array substrate and a manufacturing method thereof and a liquid crystal panel, and belongs to the technical field of display. The array substrate comprises a substrate, a pixel electrode, a thin film transistor, a first passivation layer and a second passivation layer located on one side of the substrate. Since the second passivation layer is arranged on the side of the pixel electrode away from the substrate. Therefore, in the process of assembling the array substrate and the cover plate to form the liquid crystal panel, even if foreign matters are introduced between the array substrate and the cover plate, the insulation of the second passivation layer arranged on the side of the pixel electrode away from the substrate can ensure that the foreign matters cannot conduct the pixel electrode in the array substrate and the common electrode layer arranged in the cover plate, and thus the subsequent prepared liquid crystal panel can avoid the adverse phenomenon that the normal display or the handwriting cannot be erased, so that the display effect of the liquid crystal panel is better.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its manufacturing method, and a liquid crystal panel. Background Technology

[0002] With the advancement of technology, more and more products and components are equipped with LCD panels. For example, the LCD panel in a display device can be a liquid crystal display panel. Another example is the LCD panel in a handwriting device, which can be a liquid crystal writing tablet.

[0003] A liquid crystal panel typically includes an array substrate and a cover plate, and a liquid crystal layer located between the two. The array substrate may include a first substrate and pixel electrodes located on one side of the first substrate. The cover plate may include a second substrate and a common electrode layer located on one side of the second substrate.

[0004] However, during the production of LCD panels, foreign objects (such as dust or powder) can easily be introduced between the array substrate and the cover plate. These foreign objects may conduct electricity between the pixel electrodes in the array substrate and the common electrode layer in the cover plate, causing the LCD panel to fail to display properly or the ink to be indelible at the corresponding location, thus resulting in display defects in the LCD panel. Summary of the Invention

[0005] This application provides an array substrate and its manufacturing method, as well as a liquid crystal panel. It can solve the display defects problems found in existing liquid crystal panels. The technical solution is as follows:

[0006] On one hand, an array substrate is provided, the array substrate having a display area and a non-display area located around the display area, the array substrate comprising:

[0007] Substrate;

[0008] A pixel electrode and a thin-film transistor are located on one side of the substrate, both the pixel electrode and the thin-film transistor are located within the display area, and the pixel electrode is located on the side of the thin-film transistor facing away from the substrate;

[0009] A first passivation layer is located between the pixel electrode and the thin-film transistor. The first passivation layer has a plurality of first vias, at least a portion of which are located within the display area. The pixel electrode is electrically connected to the thin-film transistor through the first vias located within the display area.

[0010] In addition, a second passivation layer is located on the side of the pixel electrode facing away from the substrate. The second passivation layer has a plurality of second vias. At least a portion of the plurality of second vias are located within the display area. The second vias located within the display area correspond one-to-one with the first vias located within the display area. The orthographic projection of the second vias located within the display area on the substrate overlaps with the orthographic projection of the corresponding first vias on the substrate.

[0011] Optionally, the central axis of the first via coincides with the central axis of the corresponding second via.

[0012] Optionally, the ratio of the opening size of the first via on the side near the substrate to the opening size on the side away from the substrate is equal to the ratio of the opening size of the corresponding second via on the side near the substrate to the opening size on the side away from the substrate.

[0013] Optionally, the orthographic projection of the second via on the substrate lies within the orthographic projection of the corresponding first via on the substrate.

[0014] Optionally, a portion of the plurality of first vias is located within the display area, and another portion is located within the non-display area; a portion of the plurality of second vias is located within the display area, and another portion is located within the non-display area; the second vias located within the non-display area correspond one-to-one with the first vias located within the non-display area, and the orthographic projection of the second vias located within the non-display area on the substrate overlaps with the orthographic projection of the corresponding first vias on the substrate.

[0015] Optionally, the array substrate further includes: a first electrode, a second electrode, and a first transparent transition electrode located in the non-display area, wherein the first transparent transition electrode is disposed in the same layer as the pixel electrode and is made of the same material;

[0016] The first transparent transition electrode contacts the first electrode through a portion of a first via located within the non-display area, and the first transparent transition electrode also contacts the second electrode through another portion of a first via located within the non-display area.

[0017] Optionally, the width of the second via in any direction parallel to the substrate ranges from 5 micrometers to 12 micrometers.

[0018] Optionally, the array substrate further includes: a plurality of support pillars located on the side of the second passivation layer away from the substrate, and a plurality of auxiliary isolation pillars disposed in the same layer as the plurality of support pillars and made of the same material, wherein the plurality of auxiliary isolation pillars correspond one-to-one with the plurality of second vias and one-to-one with the plurality of first vias, and at least a portion of the auxiliary isolation pillars are located within the corresponding first vias and the corresponding second vias.

[0019] Optionally, the height of the auxiliary isolation post is less than or equal to the sum of the depth of the corresponding first through hole and the depth of the corresponding second through hole.

[0020] Optionally, the first passivation layer further has a first cutout groove located in the non-display area, and the second passivation layer further has a second cutout groove located in the non-display area;

[0021] The second hollowed-out groove has an overlapping area with the first hollowed-out groove on the substrate.

[0022] Optionally, the array substrate further includes: auxiliary signal lines located in the display area, and signal transfer electrodes and a second transparent transfer electrode located in the non-display area;

[0023] The orthographic projection of the auxiliary signal line on the substrate and the orthographic projection of the pixel electrode on the substrate overlap in an area;

[0024] The signal transfer electrode is disposed in the same layer as the auxiliary signal line and is made of the same material, and is electrically connected to the auxiliary signal line. The orthographic projection of the signal transfer electrode on the substrate and the orthographic projection of the first hollow groove on the substrate have an overlapping area.

[0025] The second transparent transition electrode is disposed in the same layer as the pixel electrode and is made of the same material. The second transparent transition electrode is in contact with the signal transition electrode in the first hollow groove.

[0026] Optionally, the first passivation layer includes: at least one first hollow groove, wherein the orthographic projection of the second transparent transfer electrode on the substrate is entirely located within the orthographic projection of the first hollow groove on the substrate;

[0027] And / or, the first passivation layer includes: a plurality of first hollow grooves, wherein a portion of the orthographic projection of the second transparent transition electrode on the substrate is located within the orthographic projection of the first hollow groove on the substrate, and another portion is located outside the orthographic projection of the first hollow groove on the substrate.

[0028] Optionally, the side of the second transparent transition electrode facing away from the substrate is used to contact a common electrode layer in the cover plate via a conductive transition structure, at least a portion of which is located within at least one of the second hollow slots.

[0029] Optionally, the first passivation layer further has a first transition groove located in the non-display area, and the second passivation layer further has a second transition groove located in the non-display area;

[0030] The orthographic projection of the second adapter groove on the substrate overlaps with the orthographic projection of the first adapter groove on the substrate.

[0031] Optionally, the array substrate further includes: multiple signal lines located in the display area, and multiple pads and multiple third transparent transition electrodes located in the non-display area;

[0032] The multiple signal lines are electrically connected to the multiple pads one by one, and the orthographic projection of the pads on the substrate and the orthographic projection of the first adapter groove on the substrate have an overlapping area.

[0033] The third transparent transition electrode is disposed on the same layer as the pixel electrode and is made of the same material. The plurality of third transparent transition electrodes correspond one-to-one with the plurality of pads. The third transition electrode contacts the corresponding pad in the first transition groove.

[0034] Optionally, the first passivation layer includes a first transition groove, and the orthographic projections of the plurality of pads on the substrate are all located within the orthographic projection of the first transition groove on the substrate;

[0035] Alternatively, the first passivation layer includes a plurality of first transition grooves, each of which is strip-shaped, and the plurality of first transition grooves correspond one-to-one with the plurality of pads, wherein at least a portion of the orthographic projection of the pads on the substrate is located within the orthographic projection of the corresponding first transition groove on the substrate.

[0036] On the other hand, a method for manufacturing an array substrate is provided, the method comprising:

[0037] A thin-film transistor, a first passivation layer, a pixel electrode, and a second passivation layer are sequentially formed on one side of the substrate;

[0038] The array substrate has a display area and a non-display area located around the display area. The pixel electrode and the thin-film transistor are both located within the display area, and the pixel electrode is located on the side of the thin-film transistor facing away from the substrate.

[0039] The first passivation layer is located between the pixel electrode and the thin film transistor, and the first passivation layer has a plurality of first vias, at least a portion of which are located within the display area, and the pixel electrode is electrically connected to the thin film transistor through the first vias located within the display area;

[0040] The second passivation layer is located on the side of the pixel electrode away from the substrate, and the second passivation layer has a plurality of second vias. The plurality of second vias are at least partially located in the display area. The second vias located in the display area correspond one-to-one with the first vias located in the display area, and the orthographic projection of the second vias located in the display area on the substrate overlaps with the orthographic projection of the corresponding first vias on the substrate.

[0041] Optionally, the first passivation layer is obtained by patterning an insulating film located on the side of the thin-film transistor away from the substrate using a target mask, and the second passivation layer is obtained by patterning an insulating film located on the side of the pixel electrode away from the substrate using the target mask.

[0042] In another aspect, a liquid crystal panel is provided, comprising: an array substrate and a cover plate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the cover plate, wherein the array substrate is the array substrate described above.

[0043] Optionally, the liquid crystal panel is a liquid crystal writing tablet, the liquid crystal layer includes bistable liquid crystal molecules, and the cover plate includes a flexible substrate and a common electrode layer located on one side of the flexible substrate.

[0044] The beneficial effects of the technical solutions provided in this application include at least the following:

[0045] An array substrate includes a substrate, and pixel electrodes, thin-film transistors, a first passivation layer, and a second passivation layer located on one side of the substrate. Because a second passivation layer is provided on the side of the pixel electrodes facing away from the substrate, during the assembly of this array substrate and a cover plate to form a liquid crystal panel, even if foreign matter is introduced between the array substrate and the cover plate, the insulation provided by the second passivation layer on the side of the pixel electrodes facing away from the substrate ensures that the foreign matter will not conduct electricity between the pixel electrodes in the array substrate and the common electrode layer in the cover plate. This avoids defects such as abnormal display or indelible handwriting in the subsequently fabricated liquid crystal panel, resulting in a better display effect. Furthermore, the portions of the plurality of first vias in the first passivation layer distributed within the display area correspond one-to-one with the portions of the plurality of second vias in the second passivation layer distributed within the display area, and the orthogonal projection of the second vias on the substrate overlaps with the orthogonal projection of the corresponding first vias on the substrate. Therefore, the mask used in fabricating the multiple first vias within the first passivation layer can be the same as the mask used in fabricating the multiple second vias within the second passivation layer. This eliminates the need for developing and manufacturing a separate mask corresponding to the second passivation layer during the fabrication of the array substrate, thereby effectively reducing the manufacturing cost of the array substrate. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a top view of an array substrate provided in an embodiment of this application;

[0048] Figure 2 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A1;

[0049] Figure 3 yes Figure 2 The diagram shows the film structure of the array substrate at B-B'.

[0050] Figure 4 yes Figure 2 A schematic diagram of another film structure of the array substrate at B-B' is shown;

[0051] Figure 5 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A2;

[0052] Figure 6yes Figure 5 The diagram shows the film structure of the array substrate at C-C'.

[0053] Figure 7 yes Figure 5 The diagram shows the film structure of the array substrate at point D-D'.

[0054] Figure 8 yes Figure 1 A partially enlarged view of the antistatic structure is shown.

[0055] Figure 9 yes Figure 8 The diagram shows the film structure of the antistatic structure at E-E'.

[0056] Figure 10 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A3;

[0057] Figure 11 yes Figure 10 The diagram shows the film structure of the array substrate at F-F'.

[0058] Figure 12 This is a schematic diagram of the film layer structure of a liquid crystal panel at F-F' provided in an embodiment of this application;

[0059] Figure 13 yes Figure 1 A partial enlarged view of the array substrate at position A5 is shown;

[0060] Figure 14 yes Figure 13 The diagram shows the film structure of the array substrate at H-H'.

[0061] Figure 15 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A4;

[0062] Figure 16 yes Figure 15 The diagram shows the film structure of the array substrate at G-G'.

[0063] Figure 17 yes Figure 1 Another enlarged view of the array substrate at position A4 is shown;

[0064] Figure 18 yes Figure 17 The diagram shows the film structure of the array substrate at G-G'.

[0065] Figure 19 yes Figure 1 Another enlarged view of the array substrate at position A4 is shown. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0067] Please refer to Figure 1 , Figure 1 This is a top view of an array substrate provided in an embodiment of this application. The array substrate 000 may have a display area 00a and a non-display area 00b located around the display area 00a.

[0068] To see the structure of the array substrate more clearly, please refer to [reference needed]. Figure 2 and Figure 3 , Figure 2 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A1. Figure 3 yes Figure 2 The diagram shows the film structure of the array substrate at B-B'. The array substrate 000 includes: a substrate 100, and a pixel electrode 300, a thin film transistor 200, a first passivation layer 400 and a second passivation layer 500 located on one side of the substrate 100.

[0069] Both the pixel electrode 300 and the thin-film transistor 200 in the array substrate 000 can be located within the display area 00a, and the pixel electrode 300 can be located on the side of the thin-film transistor 200 facing away from the substrate 100. Here, the pixel electrode 300 can be electrically connected to the thin-film transistor 200.

[0070] The first passivation layer 400 in the array substrate 000 may be located between the pixel electrode 300 and the thin-film transistor 200, and the first passivation layer 400 has a plurality of first vias V1, at least a portion of which are located within the display area 00a. In this case, the pixel electrode 300 is electrically connected to the thin-film transistor 200 through the first vias V1 located within the display area 00a.

[0071] The second passivation layer 500 in the array substrate 000 is located on the side of the pixel electrode 300 away from the substrate 100, and the second passivation layer 500 has a plurality of second vias V2, at least a portion of which are located within the display area 00a. The second vias V2 located within the display area 00a can correspond one-to-one with the first vias V1 located within the display area 00a, and the orthographic projection of the second vias V2 located within the display area 00a onto the substrate 100 overlaps with the orthographic projection of the corresponding first vias V1 onto the substrate 100.

[0072] In this embodiment, a second passivation layer 500 is provided on the side of the pixel electrode 300 facing away from the substrate 100. Therefore, during the process of assembling the array substrate 000 and the cover plate to form a liquid crystal panel, even if foreign objects are introduced between the array substrate 000 and the cover plate, the insulation provided by the second passivation layer 500 on the side of the pixel electrode 300 facing away from the substrate 100 ensures that the foreign objects will not conduct electricity between the pixel electrode 300 in the array substrate 000 and the common electrode layer in the cover plate. This avoids the subsequent defects in the prepared liquid crystal panel, such as abnormal display or indelible handwriting, resulting in a better display effect for the liquid crystal panel.

[0073] Furthermore, since the portions of the multiple first vias V1 disposed within the first passivation layer 400 that are distributed within the display area 00a can correspond one-to-one with the portions of the multiple second vias V2 disposed within the second passivation layer 500 that are distributed within the display area 00a, and the orthogonal projection of the second via V2 onto the substrate 100 can overlap with the orthogonal projection of the corresponding first via V1 onto the substrate 100, the mask used in fabricating the multiple first vias V1 within the first passivation layer 400 can be the same as the mask used in fabricating the multiple second vias V2 within the second passivation layer 500. That is, the same mask can be used to fabricate both the multiple first vias V1 within the first passivation layer 400 and the multiple second vias V2 within the second passivation layer 500. Thus, in the fabrication of the array substrate 000, there is no need to develop and produce a separate mask corresponding to the second passivation layer 500, thereby effectively reducing the manufacturing cost of the array substrate 000.

[0074] In summary, the array substrate provided in this application includes: a substrate, and pixel electrodes, thin-film transistors, a first passivation layer, and a second passivation layer located on one side of the substrate. Because a second passivation layer is provided on the side of the pixel electrodes facing away from the substrate, during the process of assembling this array substrate with a cover plate to form a liquid crystal panel, even if foreign matter is introduced between the array substrate and the cover plate, the insulation provided by the second passivation layer on the side of the pixel electrodes facing away from the substrate ensures that the foreign matter will not conduct electricity between the pixel electrodes in the array substrate and the common electrode layer in the cover plate. This avoids defects such as abnormal display or indelible handwriting in the subsequently fabricated liquid crystal panel, resulting in a better display effect. Furthermore, the portions of the multiple first vias provided in the first passivation layer distributed within the display area correspond one-to-one with the portions of the multiple second vias provided in the second passivation layer distributed within the display area, and the orthogonal projection of the second vias on the substrate overlaps with the orthogonal projection of the corresponding first vias on the substrate. Therefore, the mask used in fabricating the multiple first vias within the first passivation layer can be the same as the mask used in fabricating the multiple second vias within the second passivation layer. This eliminates the need for developing and manufacturing a separate mask corresponding to the second passivation layer during the fabrication of the array substrate, thereby effectively reducing the manufacturing cost of the array substrate.

[0075] In this embodiment, a portion of the multiple first vias V1 disposed within the first passivation layer 400 are located within the display area 00a, and another portion of the first vias V1 are located within the non-display area 00b.

[0076] In one possible implementation, the plurality of second vias V2 formed within the second passivation layer 500 can all be located within the display area 00a. In this case, the same mask can also be used to form the plurality of first vias V1 within the first passivation layer 400 and the plurality of second vias V2 within the second passivation layer 500, respectively. However, during the process of forming the plurality of second vias V2 within the second passivation layer 500 using this mask, a shielding plate is needed to shield the portion of the mask corresponding to the non-display area 00b, so that the plurality of second vias V2 subsequently formed within the second passivation layer 500 can all be located within the display area 00a.

[0077] For example, after forming a first passivation layer 400 on the side of the thin-film transistor 200 away from the substrate 100, a target mask can be used to perform a patterning process on the first passivation layer 400 to form a plurality of first vias V1 within the first passivation layer 400; after forming a second passivation layer 500 on the side of the pixel electrode 300 away from the substrate 100, a masking plate can be used to block the portion of the target mask corresponding to the non-display area 00b, and then a patterning process can be performed on the second passivation layer 500 to form a plurality of second vias V2 within the second passivation layer 500.

[0078] In another possible implementation, a portion of the multiple second vias V2 disposed within the second passivation layer 500 are located within the display area 00a, while another portion are located within the non-display area. The second vias V2 located within the non-display area 00b can also correspond one-to-one with the first vias V1 located within the non-display area 00b, and the orthographic projections of the second vias V2 located within the non-display area 00b onto the substrate 100 overlap with the orthographic projections of the corresponding first vias V1 onto the substrate 100.

[0079] In this configuration, the plurality of first vias V1 disposed within the first passivation layer 400 and the plurality of second vias V2 disposed within the second passivation layer 500 are in one-to-one correspondence, and the orthographic projection of each second via V2 onto the substrate 100 overlaps with the orthographic projection of the corresponding first via V1 onto the substrate 100. The same mask can be used to form the plurality of first vias V1 within the first passivation layer 400 and the plurality of second vias V2 within the second passivation layer 500, respectively. Furthermore, during the formation of the plurality of second vias V2 within the second passivation layer 500 using this mask, it is not necessary to use a shielding plate to block the portion of the mask corresponding to the non-display area 00b. This further reduces the manufacturing cost of the array substrate 000.

[0080] For example, after forming a first passivation layer 400 on the side of the thin-film transistor 200 away from the substrate 100, a target mask can be used to perform a patterning process on the first passivation layer 400 to form a plurality of first vias V1 within the first passivation layer 400; after forming a second passivation layer 500 on the side of the pixel electrode 300 away from the substrate 100, the same target mask can be used again to perform a patterning process on the second passivation layer 500 to form a plurality of second vias V2 within the second passivation layer 500.

[0081] It should be noted that the patterning process in this application embodiment refers to: photoresist coating, exposure, development, etching, and photoresist stripping. It should also be noted that the following embodiments are illustrative examples of multiple second vias V2 distributed within the second passivation layer 500 that are located both within the display area 00a and the non-display area 00b.

[0082] In this embodiment, since the first via V1 in the first passivation layer 400 and the second via V2 in the second passivation layer 500 are formed based on the same mask, the central axis of each first via V1 can coincide with the central axis of the corresponding second via V2. However, in practical applications, due to processing errors, the central axis of each first via V1 may not coincide with the central axis of the corresponding second via V2; there may be a certain distance between them, but this distance is usually small. For example, the distance between the central axis of each first via V1 and the central axis of the corresponding second via V2 may be less than or equal to 0.1 micrometers.

[0083] In this application, since the first via V1 is formed by etching the first passivation layer 400, and the second via V2 is formed by etching the second passivation layer 500, the opening size of the first via V1 near the substrate 100 is generally smaller than the opening size away from the substrate 100, and the opening size of the second via V2 near the substrate 100 is also generally smaller than the opening size away from the substrate 100. Furthermore, when the material of the first passivation layer 400 is the same as that of the second passivation layer 500, and the first via V1 in the first passivation layer 400 and the second via V2 in the second passivation layer 500 are formed using the same mask, the etching rate of the first passivation layer 400 is equal to the etching rate of the second passivation layer 500, such that the ratio of the opening size of the first via V1 on the side close to the substrate 100 to the opening size on the side away from the substrate 100 is equal to the ratio of the opening size of the corresponding second via V2 on the side close to the substrate 100 to the opening size on the side away from the substrate 100.

[0084] Furthermore, the via size formed within the passivation layer is related to the thickness of the passivation layer. For example, the greater the thickness of the passivation layer and the longer the etching time, the larger the via size formed within the passivation layer; conversely, the thinner the passivation layer and the shorter the etching time, the smaller the via size formed within the passivation layer. In this application, the thickness of the first passivation layer 300 can range from 300 nanometers to 1000 nanometers, and the thickness of the second passivation layer 400 can range from 150 nanometers to 400 nanometers. Therefore, the thickness of the first passivation layer 300 can be greater than the thickness of the second passivation layer 400, so the size of the first via V1 within the first passivation layer 300 is greater than the size of the second via V2 within the second passivation layer 400. In this case, the orthographic projection of the second via V2 onto the substrate 100 lies within the orthographic projection of the corresponding first via V1 onto the substrate 100.

[0085] The following embodiments will illustrate the function of the first via V1 located in the display area 00a and the function of the first via V1 located in the non-display area 00b from two aspects:

[0086] Firstly, regarding the first via V1 located within display area 00a. For example... Figure 2 and Figure 3 As shown, the pixel electrode 300 in the array substrate 000 can be electrically connected to the thin film transistor 200 through the first via V1.

[0087] For example, the number of pixel electrodes 300 and the number of thin film transistors 200 in the array substrate 000 can both be multiple, and each pixel electrode 300 can be electrically connected to the corresponding thin film transistor 200 through at least one first via V1.

[0088] The thin-film transistor 200 may include a source 201, a drain 202, a gate 203, and an active layer 204. The source 201 and drain 202 may be in contact with the active layer 204, and the gate 203 may be insulated from the active layer 204; for example, a gate insulating layer 205 may be disposed between the gate 203 and the active layer 204. Here, both the source 201 and drain 202 may be located on the side of the active layer 204 away from the substrate 100, and the gate 203 may be located on the side of the active layer 204 closer to the substrate 100. That is, this thin-film transistor 200 is a bottom-gate type thin-film transistor. In other possible implementations, this thin-film transistor may also be a top-gate type thin-film transistor; this embodiment does not limit the specific implementation.

[0089] In this application, each pixel electrode 300 can be electrically connected to one of the source 201 and drain 202 of the corresponding thin-film transistor 200 through at least one first via V1. The array substrate 000 may further include multiple gate lines G and multiple data lines D located within the display area 00a. The multiple gate lines G and multiple data lines D can be arranged in parallel, and the extension direction of the data lines D can be perpendicular to the extension direction of the gate lines G. Thus, any two adjacent data lines D and any two adjacent gate lines G can form a sub-pixel region, and each sub-pixel region can contain a pixel electrode 300 and a corresponding thin-film transistor 200. Therefore, the thin-film transistors 200 within the display area 00a can be arrayed in multiple rows and columns. One data line D can be electrically connected to another of the source 201 and drain 202 of a column of thin-film transistors 200, and one gate line G can be electrically connected to the gate 203 of a row of thin-film transistors 200. Here, the source 201 and drain 202 of the thin-film transistor 200 can be disposed on the same layer as the data line D and made of the same material, and the gate 203 of the thin-film transistor 200 can be disposed on the same layer as the gate line G and made of the same material. It should be noted that in the following embodiments, the metal conductive layer where the gate 203 is located is referred to as the gate metal layer, and the metal conductive layer where the source 201 and drain 202 are located is referred to as the source-drain metal layer.

[0090] In this embodiment, the second passivation layer 500 within the array substrate 000 can be located on the side of the pixel electrode 300 facing away from the substrate 100. The plurality of second vias V2 disposed in the second passivation layer 500 within the display area 00a can correspond one-to-one with the plurality of first vias V1 disposed in the first passivation layer 400 within the display area 00a. The orthographic projection of each second via V2 onto the substrate 100 lies within the orthographic projection of the corresponding first via V1 onto the substrate 100. Since a portion of the pixel electrode 300 needs to be located within the first via V1, the orthographic projection of the second via V2 onto the substrate 100 lies within the orthographic projection of the corresponding pixel electrode 300 onto the substrate 100.

[0091] In this situation, during the cell assembly process between the array substrate 000 and the cover plate, foreign matter introduced between them may pass through the second passivation layer 500 and contact the pixel electrode 300 via V2 provided in the display area 00a. Therefore, to further reduce the probability of foreign matter introduced between the array substrate 000 and the cover plate conducting electricity between the pixel electrode 300 and the common electrode layer during the cell assembly process, the following two possible implementation methods can be adopted.

[0092] One possible implementation is to reduce the size of the second via V2 within the second passivation layer 500. For example, the width of the second via V2 in any direction parallel to the substrate 100 can range from 5 micrometers to 12 micrometers. It should be noted that the width of the second via V2 refers to the width of the opening of the second via V2 away from the substrate 100. Thus, when the width of the opening of the second via V2 away from the substrate 100 in any direction parallel to the substrate 100 is small, even if foreign matter is introduced between the array substrate 000 and the cover plate during the alignment process, the foreign matter will not enter the second via V2 through the opening away from the substrate 100. This ensures that the foreign matter will not contact the pixel electrode 300 disposed on the side of the second passivation layer 500 near the substrate 100, thereby preventing the foreign matter from connecting the pixel electrode 300 to the common electrode layer.

[0093] For the second possible implementation, please refer to [link / reference]. Figure 4 , Figure 4 yes Figure 2 The diagram shows another film structure of the array substrate at point B-B'. The array substrate 000 may further include: a plurality of support pillars 600 located on the side of the second passivation layer facing away from the substrate 100, and a plurality of auxiliary isolation pillars 700 disposed in the same layer as the support pillars and made of the same material. Here, the plurality of auxiliary isolation pillars 700 may correspond one-to-one with a plurality of second vias V2 disposed within the second passivation layer 500, and may also correspond one-to-one with a plurality of first vias V1 disposed within the first passivation layer 400. At least a portion of each auxiliary isolation pillar 700 is located within the corresponding first via V1 and corresponding second via V2. Thus, the auxiliary isolation pillars 700 can protect the portion of the pixel electrode 300 exposed from the second via V2. Thus, even if foreign objects are introduced between the array substrate 000 and the cover plate during the alignment process, the foreign objects can be isolated by the auxiliary isolation pillar 700 to ensure that the foreign objects do not come into contact with the pixel electrode 300 disposed on the side of the second passivation layer 500 near the substrate 100, thereby ensuring that the foreign objects do not make the pixel electrode 300 connected to the common electrode layer.

[0094] It should be noted that, in the embodiments of this application, "structures arranged in the same layer and made of the same material" means that these two structures are formed through the same patterning process. For example, "support pillar 600 and auxiliary isolation pillar 700 arranged in the same layer and made of the same material" means that support pillar 600 and auxiliary isolation pillar 700 are formed using the same patterning process. For instance, in the manufacturing process of the array substrate 000, after the second passivation layer 500 is prepared and multiple second vias V2 are formed within the second passivation layer 500, support pillar 600 and auxiliary isolation pillar 700 can be formed using the same patterning process.

[0095] Here, the support pillar 600 supports the liquid crystal panel formed by the array substrate 000 and the cover plate, preventing damage to the liquid crystal panel when the user presses the cover plate. In this application, when the support pillar 600 and the auxiliary isolation pillar 700 are formed using the same patterning process, it is possible to ensure that there are auxiliary isolation pillars 700 capable of blocking foreign objects in the second via V2 without increasing the manufacturing cost of the array substrate 000.

[0096] Optionally, the height of the auxiliary isolation pillar 700 can be less than or equal to the sum of the depths of the corresponding first via V1 and the corresponding second via V2. For example, when the height of the auxiliary isolation pillar 700 is less than the sum of the depths of the corresponding first via V1 and the corresponding second via V2, a recessed structure exists in the array substrate 000 at the location where the auxiliary isolation pillar 700 is distributed. When the height of the auxiliary isolation pillar 700 is equal to the sum of the depths of the corresponding first via V1 and the corresponding second via V2, the side of the auxiliary isolation pillar 700 facing away from the substrate 100 is flush with the side of the second passivation layer 500 facing away from the substrate 100. In this case, by making the height of the auxiliary isolation pillar 700 less than or equal to the sum of the depths of the corresponding first via V1 and the corresponding second via V2, it can be ensured that after the array substrate 000 and the cover plate are aligned to form a liquid crystal panel, the location of the auxiliary isolation pillar 700 in the array substrate 000 will not affect the normal distribution of liquid crystal molecules in the liquid crystal panel.

[0097] Secondly, regarding the first via V1 located within the non-display area 00a. For example... Figure 5 and Figure 6 As shown, Figure 5 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A2. Figure 6 yes Figure 5 The diagram shows the film layer structure of the array substrate at C-C'. The array substrate 000 may further include: a first electrode S1, a second electrode S2, and a first transparent transition electrode T1 located within the non-display area 00b. The first transparent transition electrode T1 is disposed in the same layer as the pixel electrode 300 and is made of the same material.

[0098] The first transparent transition electrode T1 contacts the first electrode S1 through a portion of the first via V1 located in the non-display area 00b, and the first transparent transition electrode T1 also contacts the second electrode S2 through another portion of the first via V1 located in the non-display area 00b.

[0099] In this application embodiment, the first electrode S1 and the second electrode S2 disposed in the non-display area 00b can be distributed in various ways. This application embodiment will illustrate the following three distribution scenarios as examples:

[0100] The first distribution scenario, such as Figure 5 and Figure 6 As shown, both the first electrode S1 and the second electrode S2 can be disposed in the same layer as the gate 203 of the thin-film transistor 200 and made of the same material. That is, both the first electrode S1 and the second electrode S2 are part of the gate metal layer.

[0101] In this configuration, the first electrode S1 can be electrically connected to the gate lines G distributed within the display area 00a, and the second electrode S2 is used to be electrically connected to the gate signal output terminal G0 located in the non-display area 00b. Since the first electrode S1 and the second electrode S2 can be electrically connected via the first transparent transition electrode T1, the gate signal output from the gate signal output terminal G0 can be sequentially transmitted to the gate lines G through the second electrode S2, the first transparent transition electrode T1, and the first electrode S1.

[0102] It should be noted that the larger the positively transparent area of ​​the gate metal layer on the substrate 100, the easier it is for static electricity to accumulate during the patterning process of forming this gate metal layer in the array substrate 000. This makes the gate insulating layer 205 formed on the gate metal layer more prone to electrostatic breakdown. Therefore, by removing the metal portion located between the first electrode S1 and the second electrode S2, the area of ​​the positive projection of this gate metal layer on the substrate 100 can be reduced, thereby reducing the probability of electrostatic breakdown in the subsequently formed gate insulating layer 205. For this reason, it is necessary to be able to conduct the first electrode S1 and the second electrode S2 separately through the first transparent transition electrode T1, which is disposed in the same layer as the pixel electrode 300 and is made of the same material, to ensure that the gate signal output terminal G0, which is electrically connected to the second electrode S2, can transmit the gate signal to the gate line G, which is electrically connected to the first electrode S1.

[0103] In this embodiment, since the gate metal layer is located on the side of the gate insulating layer 205 closest to the substrate 100, a third via V3 communicating with the first via V1 needs to be formed within the gate insulating layer 205 before the first transparent transition electrode T1 can sequentially contact the first electrode S1 (or the second electrode S2) through the first via V1 and the third via V3. It should be noted that during the fabrication of the array substrate 000, no patterning process is required after forming the gate insulating layer 205; instead, the subsequent film structure is formed directly. Here, after forming the first via V1 within the first passivation layer 200, the gate insulating layer 205 can be etched further to form the third via V3 communicating with the first via V1 within the gate insulating layer 205.

[0104] In this application, a gate drive on array (GOA) circuit can be set in the non-display area 00b, and the signal output terminal of the GOA circuit is the gate signal output terminal G0. For example... Figure 1 As shown, the gate driver chip 004 can also be bonded within the non-display area 00b, and the multiple output pins of the gate driver chip 004 can be electrically connected one-to-one with the multiple gate signal output terminals G0 set within the non-display area 00b. This ensures that the GOA circuit or the gate driver chip 004 outputs gate signals to the gate line G through the multiple gate signal output terminals G0, the first electrode S1, the first transparent transition electrode T1, and the second electrode S2.

[0105] The second distribution scenario, such as Figure 5 and Figure 7 As shown, Figure 7 yes Figure 5 The diagram shows the film structure of the array substrate at point D-D'. The first electrode S1 can be disposed in the same layer and made of the same material as the source 201 and drain 202 of the thin-film transistor 200. That is, the first electrode S1 is part of the source and drain metal layers. The second electrode S2 can be disposed in the same layer and made of the same material as the gate 203 of the thin-film transistor 200. That is, the second electrode S2 is part of the gate metal layer.

[0106] In this configuration, the first electrode S1 can be electrically connected to the data lines D distributed within the display area 00a, and the second electrode S2 is used to be electrically connected to the data signal output terminal D0 located in the non-display area 00b. Since the first electrode S1 and the second electrode S2 can be electrically connected via the first transparent adapter electrode T1, the data signal output from the data signal output terminal D0 can be sequentially transmitted to the data line D via the second electrode S2, the first transparent adapter electrode T1, and the first electrode S1.

[0107] It should be noted that since the data signal output terminal D0, located in the non-display area 00b, is part of the gate metal layer, the first electrode S1, also part of the source / drain metal layer, can be directly electrically connected to the data signal output terminal D0. Furthermore, since the data line D and the second electrode S2 distributed in the display area 00a are both part of the source / drain metal layer, the data line D and the second electrode S2 can be directly electrically connected. Therefore, a separate first transparent transition electrode T1, made of the same material as the pixel electrode 300 and located in the same layer, is needed to conduct the connection between the non-same-layer first electrode S1 and the second electrode S2, ensuring that the data signal output terminal D0, electrically connected to the second electrode S2, can transmit data signals to the data line D, electrically connected to the first electrode S1.

[0108] It should also be noted that, in order to reduce the area of ​​the gate metal layer projected onto the substrate 100, a partition can be provided within the first electrode S1 to separate the first electrode S1 into two disconnected parts. The principle can be referred to the corresponding part in the foregoing embodiments, and will not be repeated here in the embodiments of this application.

[0109] It should also be noted that a third via V3 communicating with the first via V1 is provided within the gate insulating layer 205. The function of the third via V3 can be referred to the corresponding part in the aforementioned embodiments. The embodiments of this application will not be repeated here.

[0110] In this application, as Figure 1 As shown, a source driver chip 005 can be bonded within the non-display area 00b, and multiple output pins of the source driver chip 005 can be electrically connected one-to-one with multiple data signal output terminals D0 set within the non-display area 00b. This ensures that the source driver chip 005 outputs data signals to the data line D through multiple data signal output terminals D0, the first electrode S1, the first transparent transition electrode T1, and the second electrode S2.

[0111] It should be noted that, in Figure 5 In this array, a data signal output terminal D0 is connected to two data lines D, and a gate signal output terminal G0 is connected to two gate lines G. Thus, under the control of the data signal output terminal D0 and the gate signal output terminal G0, pixel voltages can be applied simultaneously to 2×2 pixel electrodes 300. Therefore, this array substrate 000 can be used to fabricate a liquid crystal writing tablet.

[0112] Since the handwriting on the LCD handwriting tablet is typically wide when a user writes with a writing tool, while the width of the sub-pixel area where the pixel electrode 300 is located is typically small, in order to improve the erasure efficiency of the handwriting, the area where every 2×2 pixel electrodes 300 are located can form a minimum erasure area. Subsequently, when the LCD handwriting tablet determines that the handwriting within this minimum erasure area needs to be erased, it can simultaneously apply pixel voltage to the four pixel electrodes 300 within this minimum erasure area, thereby erasing the handwriting within this minimum erasure area.

[0113] In other possible implementations, a data signal output terminal D0 can be connected to one or more data lines D, and a gate signal output terminal G0 can be connected to one or more gate lines G. This application does not limit this implementation.

[0114] The third distribution scenario, such as Figure 1As shown, the array substrate 000 may further include an anti-static structure 800 located within the non-display area 00a. The first electrode S1 and the second electrode S2 may be two electrodes within the anti-static structure 800, respectively.

[0115] In the embodiments of this application, such as Figure 8 As shown, Figure 8 yes Figure 1 The diagram shows a partially enlarged view of the anti-static structure. The anti-static structure 800 may include: a first electrostatic discharge electrode 801 and a second electrostatic discharge electrode 802, and a plurality of series-connected electrostatic discharge (ESD) diodes 803 located between the first and second electrostatic discharge electrodes 801 and 802. The ESD diodes 803 may include: a first electrode, a second electrode, a semiconductor layer, and a third electrode. Specifically, the first and second electrodes of the ESD diode 803 may be disposed in the same layer and made of the same material as the source 201 and drain 202 of the thin-film transistor 200, and the first and second electrodes may be in contact with the semiconductor layer; the third electrode of the ESD diode 803 may be disposed in the same layer and made of the same material as the gate 203 of the thin-film transistor 200, and the third electrode may be insulated from the semiconductor layer; the semiconductor layer of the ESD diode 803 may be disposed in the same layer and made of the same material as the active layer 204 of the thin-film transistor 200. Here, the first terminal of the ESD diode 803 closest to the first electrostatic discharge electrode 801 can be electrically connected to the first electrostatic discharge electrode 801, and the second terminal of the ESD diode 803 closest to the second electrostatic discharge electrode 802 can be electrically connected to the second electrostatic discharge electrode 802.

[0116] In this application, the first electrostatic discharge electrode 801 can be electrically connected to the gate G or data line D in the display area 00a, and the second electrostatic discharge electrode 802 can be electrically connected to the electrostatic discharge signal line 804. Here, the electrostatic discharge signal line 804 can be the signal transfer electrode S3 in a later embodiment. It should be noted that since one end of the gate line G needs to be electrically connected to the gate signal output terminal G0, the antistatic structure 800 electrically connected to the gate line G needs to be connected from the end of the gate line G away from the gate signal output terminal G0. Similarly, since one end of the data line D needs to be electrically connected to the data signal output terminal D0, the antistatic structure 800 electrically connected to the data line D needs to be connected from the end of the data line D away from the data signal output terminal D0. It should be noted that... Figure 8 The following is a schematic illustration using the anti-static structure 800, which is electrically connected to the data cable D.

[0117] When the array substrate 000 generates static electricity during use, the static charge is transferred to the first electrostatic discharge electrode 801 in the anti-static structure 800 through the gate line G or the data line D. This causes a coupling capacitance to be generated between the first and third electrodes of the ESD diode 803, which is electrically connected to the first electrostatic discharge electrode 801. When the charge on the third electrode accumulates to the conduction current value of the ESD diode 803, the third electrode can turn on the active layer in the ESD diode 803, releasing the accumulated static charge to the electrostatic discharge signal line 804 through the second electrode and the second electrostatic discharge electrode 802 of the ESD diode 803, thereby releasing the static electricity generated in the array substrate 000 and protecting the array substrate 000.

[0118] In this embodiment, the first electrode S1 can be disposed in the same layer and made of the same material as the source 201 and drain 202 of the thin-film transistor 200. That is, the first electrode S1 is part of the source-drain metal layer. The second electrode S2 can be disposed in the same layer and made of the same material as the gate 203 of the thin-film transistor 200. That is, the second electrode S2 is part of the gate metal layer. The first electrode S1 and the second electrode S2 can be two electrodes disposed in different layers within the anti-static structure 800 but requiring electrical connection.

[0119] It should be noted that the locations of the two electrodes that need to be electrically connected but are arranged in different layers within the antistatic structure 800 are varied, for example, such as... Figure 9 As shown, Figure 9 yes Figure 8 The schematic diagram of the film structure at E-E' of the antistatic structure is shown. The first electrode S1 and the second electrode S2 are located in the first electrostatic discharge electrode 801 within the antistatic structure 800, or they can be located in the second electrostatic discharge electrode 802 within the antistatic structure 800, or they can be located in the electrodes within the antistatic structure 800 used to connect two adjacent ESD diodes 803 in series.

[0120] In this application, during the cell assembly process between the array substrate 000 and the cover plate, foreign matter introduced between them may pass through the second passivation layer 500 and contact the first transparent transfer electrode T1 via V2 disposed in the non-display area 00b. Therefore, to reduce the probability of foreign matter introduced between the array substrate 000 and the cover plate conducting electricity between the first transparent transfer electrode T1 and the common electrode layer during the cell assembly process, similar implementation methods as described above can be adopted. The embodiments of this application will not be elaborated further here.

[0121] Optional, such as Figure 1 , Figure 10 and Figure 11 As shown, Figure 10 yes Figure 1 The image shown is a partial enlarged view of the array substrate at position A3. Figure 11yes Figure 10 The diagram shows a schematic of the film structure of the array substrate at F-F'. The first passivation layer 400 further has a first cutout groove U1 located within the non-display area 00b, and the second passivation layer 500 further has a second cutout groove U2 located within the non-display area 00b. The orthographic projection of the second cutout groove U2 onto the substrate 100 overlaps with the orthographic projection of the first cutout groove U1 onto the substrate 100. For example, the orthographic projection of the second cutout groove U2 onto the substrate 100 may lie within the orthographic projection of the first cutout groove U1 onto the substrate 100.

[0122] In the embodiments of this application, such as Figure 2 , Figure 10 and Figure 11 As shown, the array substrate 000 may further include: an auxiliary signal line G1 located in the display area 00a, and a signal transfer electrode S3 and a second transparent transfer electrode T2 located in the non-display area 00b.

[0123] The orthographic projection of the auxiliary signal line G1 within the array substrate 000 onto the substrate 100 may overlap with the orthographic projection of the pixel electrode 300 onto the substrate 100. Here, the auxiliary signal line G1 may be disposed in the same layer as the gate line G and made of the same material, and the extension direction of the auxiliary signal line G1 may be parallel to the extension direction of the gate line G. The auxiliary signal line G1 may form a storage capacitor with each pixel electrode 300 in a row of pixel electrodes 300. This storage capacitor can be used to maintain the pixel voltage of the pixel electrode 200.

[0124] The signal transfer electrode S3 in the array substrate 000 can be disposed in the same layer as the auxiliary signal line G1 and made of the same material, and the signal transfer electrode S3 and the auxiliary signal line G1 can be directly electrically connected. The orthographic projection of the signal transfer electrode S3 on the substrate 100 overlaps with the orthographic projection of the first cutout groove U1 on the substrate 100.

[0125] The second transparent transition electrode T2 in the array substrate 000 is disposed on the same layer as the pixel electrode 200 and is made of the same material. The orthographic projection of the second transparent transition electrode T2 on the substrate 100 can also overlap with the orthographic projection of the first cutout groove U1 on the substrate 100. In this way, the second transparent transition electrode T2 can contact the signal transition electrode S3 within the first cutout groove U1.

[0126] In this embodiment, the potential of the auxiliary signal line G1 disposed in the display area 00a needs to be the same as the potential of the common electrode layer disposed in the cover plate of the subsequently manufactured liquid crystal panel. To this end, the auxiliary signal line G1 can contact the common electrode layer disposed in the cover plate through the signal transfer electrode S3 and the second transparent transfer electrode T2 located in the non-display area 00b, thereby ensuring that the potential of the common electrode layer is consistent with the potential of the auxiliary signal line G1.

[0127] For example, the side of the second transparent transfer electrode T2 facing away from the substrate 100 can protrude from the second cutout U2. Thus, the side of the second transparent transfer electrode T2 facing away from the substrate 100 is used to contact the common electrode layer within the cover plate via a conductive transfer structure. At least a portion of this conductive transfer structure can be located within the second cutout U2. Therefore, the auxiliary signal line G1 can sequentially contact the common electrode layer within the cover plate via the signal transfer electrode S3, the second transparent transfer electrode T2, and the conductive transfer structure located within the second cutout U2.

[0128] In one possible implementation, such as Figure 1 As shown, the non-display area 00b has a ring-shaped sealing area 00c. (As indicated...) Figure 12 As shown, Figure 12 This is a schematic diagram of the film layer structure at F-F' of a liquid crystal panel provided in an embodiment of this application. Before the array substrate 000 and the cover plate 001 are aligned, a sealing frame 002 can be coated in this sealing area 00c so that the array substrate 000 and the cover plate 001 can be connected through the sealing frame 002 during subsequent alignment processing. Here, the orthogonal projection of the sealing frame 002 on the substrate 100 can overlap with the orthogonal projection of the first hollow groove U1 on the substrate 100. Thus, metal conductive balls 002a can be filled in the portion of the sealing frame 002 corresponding to the first hollow groove U1, so that after the array substrate 000 and the cover plate 001 are connected through the sealing frame 002, the metal conductive balls 002a can contact the common electrode layer 001a in the cover plate 001, and at least a portion of the metal conductive balls 002a can be located in the second hollow groove U2 and contact the second transparent transition electrode T2. Therefore, the metal conductive ball 002a filled inside the sealing frame 002 is the conductive transition structure.

[0129] It should be noted that the size of the second hollow groove U2 provided in the second passivation layer 500 needs to be large to ensure that at least a portion of the metal conductive balls 002a filled in the sealing frame 002 can be located in the second hollow groove U2.

[0130] In this embodiment, the first passivation layer 400 may include at least one elongated first hollow groove U1, and / or multiple block-shaped first hollow grooves U1. Therefore, this embodiment will be illustrated using the following two implementation methods as examples:

[0131] The first implementation method, such as Figure 10 and Figure 11As shown, when the first passivation layer 400 includes a plurality of block-shaped first hollow grooves U1, a portion of the second transparent transfer electrode T2 is located within the orthographic projection of the first hollow grooves U1 onto the substrate 100, and another portion is located outside the orthographic projection of the first hollow grooves U1 onto the substrate 100. Here, the block-shaped first hollow grooves U1 refer to the shape of the orthographic projection of the first hollow grooves U1 onto the substrate 100 being block-shaped. For example, the shape of the orthographic projection of the first hollow grooves U1 onto the substrate 100 is a rectangle with approximately equal long and short sides.

[0132] In this configuration, the second passivation layer 500 may also include a plurality of block-shaped second hollow grooves U2, each corresponding one-to-one with a plurality of first hollow grooves U1, and the orthographic projection of each second hollow groove U2 onto the substrate 100 lies within the orthographic projection of the corresponding first hollow groove U1 onto the substrate 100. Here, the width of the opening of the second hollow groove U2 facing away from the substrate 100 in any direction parallel to the substrate 100 ranges from 50 micrometers to 1000 micrometers. This ensures that the size of the second hollow groove U2 is relatively large, allowing at least a portion of the conductive transition structure to be located within the second hollow groove U2 and in contact with the second transparent transition electrode T2.

[0133] The second implementation method, such as Figure 13 and Figure 14 As shown, Figure 13 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A5. Figure 14 yes Figure 13 The diagram shows a schematic of the film structure of the array substrate at H-H'. When the first passivation layer 400 includes at least one elongated first perforated groove U1, the orthographic projection of the second transparent switching electrode T2 on the substrate 100 can be entirely located within the orthographic projection of the first perforated groove U1 on the substrate 100. Here, the elongated first perforated groove U1 means that the orthographic projection of the first perforated groove U1 on the substrate 100 is a window-like shape. For example, the orthographic projection of the first perforated groove U1 on the substrate 100 is a long rectangle with a large difference between its long and short sides.

[0134] In one possible scenario, the first passivation layer 400 includes a first cutout groove U1, in which the orthographic projection of the first cutout groove U1 onto the substrate 100 covers at least the upper portion of the encapsulation region 00c and / or covers at least the right portion of the encapsulation region 00c. For example, when the orthographic projection of the first cutout groove U1 onto the substrate 100 covers at least the upper portion of the encapsulation region 00c and can cover at least the right portion of the encapsulation region 00c, the shape of the orthographic projection of the first cutout groove U1 onto the substrate 100 is an L-shape composed of two elongated strips.

[0135] In another possible scenario, the first passivation layer 400 includes two first cutouts U1, wherein the orthographic projection of one first cutout U1 onto the substrate 100 covers at least the upper portion of the encapsulation region 00c, and the orthographic projection of the other first cutout U1 onto the substrate 100 covers at least the right portion of the encapsulation region 00c.

[0136] In this configuration, the second passivation layer 500 may also include at least one elongated second hollow groove U2, the orthographic projection of which onto the substrate 100 lies within the orthographic projection of the first hollow groove U1 onto the substrate 100. This ensures that the second hollow groove U2 is relatively large, guaranteeing that at least a portion of the conductive transition structure is located within it. Furthermore, this configuration also ensures a more uniform distribution of the conductive transition structures within the second hollow groove U2, guaranteeing a stable electrical connection between the auxiliary signal line G1 in the subsequent display area and the common electrode layer on the cover plate.

[0137] In one exemplary implementation, such as Figure 14 As shown, the portion of the signal transfer electrode S3 not covered by the orthographic projection of the first cutout slot U1 can be called the bridging electrode S3'. This bridging electrode S3' is used for electrical connection with the auxiliary signal line G1 disposed within the display area 00a. Thus, the auxiliary signal line G1 can connect to the signal transfer electrode S3, whose orthographic projection is covered by the first cutout slot U1, via the bridging electrode S3'.

[0138] It should be noted that, as Figure 11 and Figure 14 As shown, a transition slot U3 communicating with the first slot U1 is provided in the gate insulating layer 205. Here, the reason for the provision and formation process of the transition slot U3 in the gate insulating layer 205 can be referred to the reason for the provision and formation process of the third via V3 in the gate insulating layer 205 in the above embodiment, and will not be repeated here.

[0139] It should also be noted that each auxiliary signal line G1 set in the display area 00a can be electrically connected to the signal transfer electrode S3, and the orthographic projection of the signal transfer electrode S3 on the substrate 100 can be in the form of a grid to reduce the area of ​​the orthographic projection of the signal transfer electrode S3 on the substrate 100, thereby reducing the probability of electrostatic discharge during the fabrication of the array substrate 000 causing the film layer to break down.

[0140] It should also be noted that the above embodiments are based on Figure 1 Multiple block-shaped first hollow slots U1 are distributed at position A3, and Figure 1The example shown is an illustration of at least one strip-shaped first hollow groove U1 distributed at position A5. In other possible implementations, at least one strip-shaped first hollow groove U1 can be distributed at both positions A3 and A5, or multiple block-shaped first hollow grooves U1 can be distributed at both positions A3 and A5, or at least one strip-shaped first hollow groove U1 can be distributed at position A3 and multiple block-shaped first hollow grooves U1 can be distributed at position A5. This application does not limit the scope of the embodiments in this way.

[0141] Optional, such as Figure 1 , Figure 15 and Figure 16 As shown, Figure 15 yes Figure 1 The diagram shows a partial enlarged view of the array substrate at position A4. Figure 16 yes Figure 15 The diagram shows a schematic of the film structure of the array substrate at G-G'. The first passivation layer 400 also has a first transition groove U4 located within the non-display area 00b, and the second passivation layer 500 also has a second transition groove U5 located within the non-display area 00b. The orthographic projection of the second transition groove U5 onto the substrate 100 overlaps with the orthographic projection of the first transition groove U4 onto the substrate 100. For example, the orthographic projection of the second transition groove U5 onto the substrate 100 may lie within the orthographic projection of the first transition groove U4 onto the substrate 100. In this embodiment, the first transition groove U4 and the first cutout groove U1 may be disposed opposite each other on both sides of the display area 00a. For example, the first cutout groove U1 may be distributed near a set of adjacent sides of the display area 00a, for example, in... Figure 1 In the process, the first hollowed-out groove U1 can be distributed near the right and upper sides of the display area 00a; the first transition groove U4 can be distributed at least near another set of adjacent sides of the display area 00a, for example, in Figure 1 In this configuration, the first adapter slot U4 can be located near the lower or left side of the display area 00a. It should be noted that when a GOA circuit is provided in the non-display area 00b, and the GOA circuit is located near the left side of the display area 00a, the first adapter slot U4 only needs to be located near the lower side of the display area 00a.

[0142] In the embodiments of this application, such as Figure 1 , Figure 15 and Figure 16 As shown, the array substrate 000 also includes: multiple signal lines located in the display area 00a, and multiple pads H and multiple third transparent transition electrodes T3 located in the non-display area 00b.

[0143] Multiple signal lines within the array substrate 000 can be electrically connected to multiple pads H in a one-to-one correspondence. These pads are used to bond with a driver chip, which can be either a gate driver chip 004 or a source driver chip 005. When both the gate driver chip and the source driver chip 005 need to be bonded within the array substrate 000, the signal lines distributed within the display area 00a can be either gate lines G or data lines D. In this way, the gate line G can be electrically connected to the gate driver chip 004 via pad H, allowing the gate driver chip 004 to transmit gate signals to the gate line G via pad H; similarly, the data line D can be electrically connected to the source driver chip 005 via pad H, allowing the source driver chip 005 to transmit data signals to the data line D via pad H. When only the source driver chip 005 needs to be bonded within the array substrate 000, the signal lines distributed within the display area 00a can be data lines D, and the data lines D can be electrically connected to the source driver chip 005 via pad H.

[0144] The orthographic projection of the pad H in the array substrate 000 onto the substrate 100 may overlap with the orthographic projection of the first transition groove U4 onto the substrate 100.

[0145] The third transparent transition electrode T3 within the array substrate 000 is typically disposed and made of the same material as the pixel electrode 300. Multiple third transparent transition electrodes T3 can correspond one-to-one with multiple pads H, and the orthographic projection of each third transparent transition electrode T3 on the substrate 100 can overlap with the orthographic projection of the first transition groove U4 on the substrate 100. Thus, each third transparent transition electrode T3 can contact its corresponding pad H within the first transition groove U4. For example, the boundary of the orthographic projection of each pad H on the substrate 100 can coincide with the boundary of the orthographic projection of the corresponding third transparent transition electrode T3 on the substrate 100.

[0146] Optionally, the pad H may include a first sub-pad H1 and a second sub-pad H2 stacked together. In this application, the third transparent transition electrode T3 contacts the first sub-pad H1 and the second sub-pad H2 respectively. The first sub-pad H1 may be co-layered with the gate line G and made of the same material, while the second sub-pad H2 may be co-layered with the data line D and made of the same material. That is, the first sub-pad H1 in the pad H is part of the gate metal layer, and the second sub-pad H2 in the pad H is part of the source and drain metal layers. Thus, when the pad H is formed using two different metal layers, the overall height of the pad H can be ensured to be relatively high, so that the driver chip can be easily bonded to the array substrate 000 during the subsequent bonding process.

[0147] For example, the second sub-pad H2 has a first auxiliary cutout groove K1, and the orthographic projection of the first auxiliary cutout groove K1 on the substrate 100 lies within the orthographic projection of the first sub-pad H1 on the substrate 100. Furthermore, since there is a gate insulating layer 205 between the gate metal layer and the source / drain metal layers, a second auxiliary cutout groove K2 communicating with the first auxiliary cutout groove K1 needs to be provided on the gate insulating layer 205. In this way, a portion of the third visible transition electrode T3 can sequentially pass through the first auxiliary cutout groove K1 and the second auxiliary cutout groove K2 to contact the first sub-pad H1, and the portion of the third visible transition electrode T3 located outside the first auxiliary cutout groove K1 can contact the second sub-pad H2. Thus, it can be ensured that the third transparent transition electrode T3 contacts both the first sub-pad H1 and the second sub-pad H2.

[0148] In this embodiment, the side of the pad H facing away from the substrate 100 can protrude from the second transition groove U5. Thus, the side of the pad H facing away from the substrate 100 is used to contact the solder pads within the driver chip via anisotropic conductive film (ACF). At least a portion of this ACF can be located within the second transition groove U5. Therefore, the pad H can be electrically connected to the solder pads within the driver chip via the ACF. It should be noted that the size of the second transition groove U5 within the second passivation layer 500 needs to be relatively large to ensure that at least a portion of the ACF can be located within the second transition groove U5 during the bonding of the driver chip onto the array substrate 000.

[0149] In this embodiment, the number of first transition grooves U4 disposed within the first passivation layer 400 can be one or more. Therefore, this embodiment will be illustrated using the following two optional implementation methods as examples:

[0150] The first optional implementation method, such as Figure 15 and Figure 16 As shown, when the first passivation layer 400 includes a first transfer groove U4, the orthographic projections of the multiple pads H distributed in the array substrate 000 onto the substrate 100 can all be located within the orthographic projection of the first transfer groove U3 onto the substrate 100.

[0151] In this case, only the portion of the first passivation layer 400 used to distribute multiple pads H needs to be removed, effectively reducing the process difficulty of patterning the first passivation layer 400. Correspondingly, the number of second transition grooves U5 distributed within the second passivation layer 500 is also one, and the orthographic projections of the multiple pads H on the substrate 100 can all lie within the orthographic projection of this second transition groove U5 on the substrate 100. This ensures that during the bonding of the driver chip on the array substrate 000, the ACF can be located within the second transition groove U5 and contact the pads H.

[0152] The second optional implementation method, such as Figure 17 and Figure 18 As shown, Figure 17 yes Figure 1 Another enlarged view of the array substrate at position A4 is shown. Figure 18 yes Figure 17 The diagram shows the film structure of the array substrate at I-I'. When the first passivation layer 400 includes a plurality of first transition grooves U4, each of the first transition grooves U4 disposed within the first passivation layer 400 can be strip-shaped. The plurality of first transition grooves U4 can correspond one-to-one with a plurality of pads H, and at least a portion of the orthographic projection of each pad H on the substrate 100 lies within the orthographic projection of the corresponding first transition groove U4 on the substrate 100.

[0153] In this configuration, there are multiple second transition grooves U5 within the second passivation layer 500. Each second transition groove U5 corresponds one-to-one with a first transition groove U4, and the orthographic projection of each second transition groove U5 onto the substrate 100 lies within the orthographic projection of the corresponding first transition groove U4 onto the substrate 100. Here, the width of the opening of the second transition groove U5 away from the substrate 100 in any direction parallel to the substrate 100 ranges from 50 micrometers to 120 micrometers. This ensures that the second transition groove U5 has a relatively large size, allowing a portion of the ACF to be located within the second transition groove U5.

[0154] In one possible implementation, such as Figure 17 As shown, the length of each first adapter groove U4 can be greater than the length of the corresponding pad H. In this way, the orthographic projection of each pad H on the substrate 100 can be entirely located within the orthographic projection of the corresponding first adapter groove U4 on the substrate 100.

[0155] In another possible implementation, such as Figure 19 As shown, Figure 19 yes Figure 1The diagram shows another partial enlarged view of the array substrate at position A4, where the length of each first transition groove U4 can be less than the length of the corresponding pad H. Thus, a portion of the orthographic projection of each pad H onto the substrate 100 lies within the orthographic projection of the corresponding first transition groove U4 onto the substrate 100. Here, Figure 19 The schematic diagram of the film structure of the array substrate at J-J' shown can be referenced. Figure 18 .

[0156] In both of the above cases, at least a portion of each pad H can be exposed from the corresponding second adapter groove U5 to ensure that the portion of the pad H exposed from the second adapter groove U5 can contact the solder pins of the driver chip through the ACF.

[0157] In summary, the array substrate provided in this application includes: a substrate, and pixel electrodes, thin-film transistors, a first passivation layer, and a second passivation layer located on one side of the substrate. Because a second passivation layer is provided on the side of the pixel electrodes facing away from the substrate, during the process of assembling this array substrate with a cover plate to form a liquid crystal panel, even if foreign matter is introduced between the array substrate and the cover plate, the insulation provided by the second passivation layer on the side of the pixel electrodes facing away from the substrate ensures that the foreign matter will not conduct electricity between the pixel electrodes in the array substrate and the common electrode layer in the cover plate. This avoids defects such as abnormal display or indelible handwriting in the subsequently fabricated liquid crystal panel, resulting in a better display effect. Furthermore, the portions of the multiple first vias provided in the first passivation layer distributed within the display area correspond one-to-one with the portions of the multiple second vias provided in the second passivation layer distributed within the display area, and the orthogonal projection of the second vias on the substrate overlaps with the orthogonal projection of the corresponding first vias on the substrate. Therefore, the mask used in fabricating the multiple first vias within the first passivation layer can be the same as the mask used in fabricating the multiple second vias within the second passivation layer. This eliminates the need for developing and manufacturing a separate mask corresponding to the second passivation layer during the fabrication of the array substrate, thereby effectively reducing the manufacturing cost of the array substrate.

[0158] This application provides a method for manufacturing an array substrate, which is used to manufacture the array substrate shown in the above embodiments. The method for manufacturing the array substrate may include:

[0159] A thin-film transistor, a first passivation layer, a pixel electrode, and a second passivation layer are sequentially formed on one side of the substrate.

[0160] The array substrate has a display area and a non-display area located around the display area. Pixel electrodes and thin-film transistors are both located within the display area, with the pixel electrodes located on the side of the thin-film transistors facing away from the substrate. A first passivation layer is located between the pixel electrodes and the thin-film transistors, and the first passivation layer has multiple first vias, at least a portion of which are located within the display area. The pixel electrodes are electrically connected to the thin-film transistors through the first vias located within the display area. A second passivation layer is located on the side of the pixel electrodes facing away from the substrate, and the second passivation layer has multiple second vias, at least a portion of which are located within the display area. The second vias located within the display area correspond one-to-one with the first vias located within the display area, and the orthographic projections of the second vias located within the display area onto the substrate overlap with the orthographic projections of the corresponding first vias onto the substrate.

[0161] Optional. The first passivation layer is obtained by patterning the insulating film on the side of the thin-film transistor away from the substrate using a target mask, and the second passivation layer is obtained by patterning the insulating film on the side of the pixel electrode away from the substrate using a target mask.

[0162] It should be noted that the structural principle of the array substrate in the above embodiments can be found in the corresponding content of the array substrate structural embodiments shown in the foregoing embodiments. Further details will not be repeated here.

[0163] This application also provides a liquid crystal panel, which includes: an array substrate and a cover plate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the cover plate. In this application embodiment, the array substrate in the liquid crystal panel can be the array substrate in the above embodiments.

[0164] In one possible implementation, the liquid crystal panel can be a liquid crystal display panel, in which case the cover plate in the liquid crystal panel can be a color filter substrate.

[0165] In another possible implementation, the liquid crystal panel can also be a liquid crystal writing tablet. In this case, the liquid crystal layer in the liquid crystal panel can include bistable liquid crystal molecules, and the cover plate in the liquid crystal panel can include a flexible substrate and a common electrode layer located on one side of the flexible substrate.

[0166] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0167] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0168] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate has a display area and a non-display area located around the display area, and the array substrate includes: Substrate; A pixel electrode and a thin-film transistor are located on one side of the substrate, both the pixel electrode and the thin-film transistor are located within the display area, and the pixel electrode is located on the side of the thin-film transistor facing away from the substrate; A first passivation layer is located between the pixel electrode and the thin-film transistor. The first passivation layer has a plurality of first vias, at least a portion of which are located within the display area. The pixel electrode is electrically connected to the thin-film transistor through the first vias located within the display area. In addition, a second passivation layer is located on the side of the pixel electrode facing away from the substrate. The second passivation layer has a plurality of second vias. At least a portion of the plurality of second vias are located within the display area. The second vias located within the display area correspond one-to-one with the first vias located within the display area. The orthographic projection of the second vias located within the display area on the substrate overlaps with the orthographic projection of the corresponding first vias on the substrate.

2. The array substrate according to claim 1, characterized in that, The central axis of the first via coincides with the central axis of the corresponding second via.

3. The array substrate according to claim 2, characterized in that, The ratio of the opening size of the first via on the side closer to the substrate to the opening size on the side away from the substrate is equal to the ratio of the opening size of the corresponding second via on the side closer to the substrate to the opening size on the side away from the substrate.

4. The array substrate according to claim 3, characterized in that, The orthographic projection of the second via on the substrate lies within the orthographic projection of the corresponding first via on the substrate.

5. The array substrate according to any one of claims 1-4, characterized in that, A portion of the plurality of first vias is located within the display area, and another portion is located within the non-display area; a portion of the plurality of second vias is located within the display area, and another portion is located within the non-display area; the second vias located within the non-display area correspond one-to-one with the first vias located within the non-display area, and the orthographic projection of the second vias located within the non-display area on the substrate overlaps with the orthographic projection of the corresponding first vias on the substrate.

6. The array substrate according to claim 5, characterized in that, The array substrate further includes: a first electrode, a second electrode, and a first transparent transition electrode located in the non-display area, wherein the first transparent transition electrode is disposed in the same layer as the pixel electrode and is made of the same material; The first transparent transition electrode contacts the first electrode through a portion of a first via located within the non-display area, and the first transparent transition electrode also contacts the second electrode through another portion of a first via located within the non-display area.

7. The array substrate according to claim 6, characterized in that, The width of the second via in any direction parallel to the substrate ranges from 5 micrometers to 12 micrometers.

8. The array substrate according to claim 6, characterized in that, The array substrate further includes: a plurality of support pillars located on the side of the second passivation layer away from the substrate, and a plurality of auxiliary isolation pillars disposed in the same layer as the plurality of support pillars and made of the same material. The plurality of auxiliary isolation pillars correspond one-to-one with the plurality of second vias and one-to-one with the plurality of first vias. At least a portion of the auxiliary isolation pillars are located in the corresponding first via and the corresponding second via.

9. The array substrate according to claim 8, characterized in that, The height of the auxiliary isolation column is less than or equal to the sum of the depth of the corresponding first through hole and the depth of the corresponding second through hole.

10. The array substrate according to any one of claims 1-4 and 6-9, characterized in that, The first passivation layer also has a first cutout groove located in the non-display area, and the second passivation layer also has a second cutout groove located in the non-display area; The second hollowed-out groove has an overlapping area with the first hollowed-out groove on the substrate.

11. The array substrate according to claim 10, characterized in that, The array substrate further includes: auxiliary signal lines located in the display area, and signal transfer electrodes and a second transparent transfer electrode located in the non-display area; The orthographic projection of the auxiliary signal line on the substrate and the orthographic projection of the pixel electrode on the substrate overlap in an area; The signal transfer electrode is disposed in the same layer as the auxiliary signal line and is made of the same material, and is electrically connected to the auxiliary signal line. The orthographic projection of the signal transfer electrode on the substrate and the orthographic projection of the first hollow groove on the substrate have an overlapping area. The second transparent transition electrode is disposed in the same layer as the pixel electrode and is made of the same material. The second transparent transition electrode is in contact with the signal transition electrode in the first hollow groove.

12. The array substrate according to claim 11, characterized in that, The first passivation layer includes: at least one first hollow groove, wherein the orthographic projection of the second transparent transfer electrode on the substrate is entirely located within the orthographic projection of the first hollow groove on the substrate; And / or, the first passivation layer includes: a plurality of first hollow grooves, wherein a portion of the orthographic projection of the second transparent transition electrode on the substrate is located within the orthographic projection of the first hollow groove on the substrate, and another portion is located outside the orthographic projection of the first hollow groove on the substrate.

13. The array substrate according to claim 12, characterized in that, The side of the second transparent transition electrode facing away from the substrate is used to contact the common electrode layer in the cover plate through a conductive transition structure, at least a portion of which is located in at least one of the second hollow slots.

14. The array substrate according to any one of claims 1-4, 6-9, and 11-13, characterized in that, The first passivation layer also has a first transition groove located in the non-display area, and the second passivation layer also has a second transition groove located in the non-display area; The orthographic projection of the second adapter groove on the substrate overlaps with the orthographic projection of the first adapter groove on the substrate.

15. The array substrate according to claim 14, characterized in that, The array substrate further includes: multiple signal lines located in the display area, and multiple pads and multiple third transparent transition electrodes located in the non-display area; The multiple signal lines are electrically connected to the multiple pads one by one, and the orthographic projection of the pads on the substrate and the orthographic projection of the first adapter groove on the substrate have an overlapping area. The third transparent transition electrode is disposed on the same layer as the pixel electrode and is made of the same material. The plurality of third transparent transition electrodes correspond one-to-one with the plurality of pads. The third transparent transition electrode contacts the corresponding pad in the first transition groove.

16. The array substrate according to claim 15, characterized in that, The first passivation layer includes a first transition groove, and the orthographic projections of the plurality of pads on the substrate are all located within the orthographic projection of the first transition groove on the substrate; Alternatively, the first passivation layer includes a plurality of first transition grooves, each of which is strip-shaped, and the plurality of first transition grooves correspond one-to-one with the plurality of pads, wherein at least a portion of the orthographic projection of the pads on the substrate is located within the orthographic projection of the corresponding first transition groove on the substrate.

17. The array substrate according to claim 1, characterized in that, The plurality of first vias correspond one-to-one with the plurality of second vias, and the orthographic projection of each second via on the substrate overlaps with the orthographic projection of the corresponding first via on the substrate.

18. A method for manufacturing an array substrate, characterized in that, The method includes: A thin-film transistor, a first passivation layer, a pixel electrode, and a second passivation layer are sequentially formed on one side of the substrate; The array substrate has a display area and a non-display area located around the display area. The pixel electrode and the thin-film transistor are both located within the display area, and the pixel electrode is located on the side of the thin-film transistor facing away from the substrate. The first passivation layer is located between the pixel electrode and the thin film transistor, and the first passivation layer has a plurality of first vias, at least a portion of which are located within the display area, and the pixel electrode is electrically connected to the thin film transistor through the first vias located within the display area; The second passivation layer is located on the side of the pixel electrode away from the substrate, and the second passivation layer has a plurality of second vias. The plurality of second vias are at least partially located in the display area. The second vias located in the display area correspond one-to-one with the first vias located in the display area, and the orthographic projection of the second vias located in the display area on the substrate overlaps with the orthographic projection of the corresponding first vias on the substrate.

19. The method according to claim 18, characterized in that, The first passivation layer is obtained by patterning an insulating film located on the side of the thin-film transistor away from the substrate using a target mask, and the second passivation layer is obtained by patterning an insulating film located on the side of the pixel electrode away from the substrate using the target mask.

20. A liquid crystal panel, characterized in that, include: An array substrate and a cover plate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the cover plate, wherein the array substrate is the array substrate according to any one of claims 1 to 17.

21. The liquid crystal panel according to claim 20, characterized in that, The liquid crystal panel is a liquid crystal handwriting tablet, and the liquid crystal layer includes bistable liquid crystal molecules; The cover plate includes: a flexible substrate, and a common electrode layer located on one side of the flexible substrate.

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