Array substrate and display panel

Abstract

The embodiment of the present application discloses an array substrate and a display panel. The embodiment of the present application integrates shielding lines of a black shading layer into the array substrate to shield data lines, so that the bent display panel avoids vertical misalignment of the black matrix and the data lines, and maintains or improves the aperture ratio of the display panel; in addition, the shielding lines are connected to the common signal, so that during the display process, the shielding lines have a constant voltage signal, reducing the risk of interference signals entering the shielding lines, thereby reducing the influence of the black shading layer on the driving electric field.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the related technology of curved liquid crystal display panels, when the display panel is bent, the array substrate and the color filter substrate are misaligned, resulting in a deviation in the alignment between the black matrix on the color filter substrate side and the data line of the array substrate. In order to compensate for this deviation, the width of the black matrix is ​​usually widened. However, such a design will reduce the aperture ratio.

[0003] In the related art, there is also a method of integrating the black matrix into the array substrate to solve the problems of misalignment and low aperture ratio. However, when the black matrix is ​​a conductive material, the black matrix layer easily absorbs interference signals, thereby affecting the electric field that drives the liquid crystal deflection, resulting in poor display effect. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a display panel, which can avoid vertical misalignment between a black matrix and a data line, and reduce the influence of a black light shielding layer on a driving electric field while maintaining or improving the aperture ratio of the display panel.

[0005] The present application provides an array substrate, which includes:

[0006] substrate;

[0007] A thin film transistor structure layer is disposed on the substrate, and the thin film transistor structure layer includes a data line;

[0008] a black light shielding layer, arranged on a side of the thin film transistor structure layer away from the substrate, the black light shielding layer comprising a shielding line, in a top view of the array substrate, the shielding line is extended along an extension direction of the data line, and the shielding line covers the data line;

[0009] A common electrode is disposed in a different layer from the data line and the black light shielding layer; and

[0010] The pixel electrode is disposed in different layers from the data line and the black light shielding layer respectively;

[0011] Wherein, the shielding line is configured to access a public signal.

[0012] Optionally, in some embodiments of the present application, the common electrode is arranged on a side of the black light shielding layer away from the substrate, the pixel electrode and the common electrode are arranged in a different layer and are located on a side of the common electrode away from the substrate, and the thin film transistor structure layer further includes a common wiring;

[0013] The common wiring is connected to the shielding line; or the black light shielding layer further includes connecting lines connected to a plurality of the shielding lines, and the common wiring is electrically connected to the connecting lines.

[0014] Optionally, in some embodiments of the present application, the common wiring is arranged in the same layer as the data line, and the array substrate further includes a color resist layer, a planar layer, a first insulating layer, and a second insulating layer, the color resist layer is arranged on a side of the data line and the common wiring away from the substrate, the planar layer covers the color resist layer, the black light shielding layer is arranged on a side of the planar layer away from the substrate, the first insulating layer covers the black light shielding layer, the common electrode is arranged on a side of the first insulating layer away from the substrate, the second insulating layer covers the common electrode and the first insulating layer, and the pixel electrode is arranged on a side of the second insulating layer away from the substrate;

[0015] The array substrate is further provided with a first via hole and a second via hole, the first via hole penetrates the first insulating layer and the planar layer and exposes the common wiring, and the second via hole penetrates the first insulating layer and exposes the shielding line or the connecting line;

[0016] The array substrate further includes a transfer line which is arranged in the same layer as and connected to the common electrode, the transfer line is connected to the common wiring through the first via hole, and the transfer line is connected to the shielding line or the connecting line through the second via hole.

[0017] Optionally, in some embodiments of the present application, the common wiring is arranged in the same layer as the data line, and the array substrate further includes a color resist layer, a planar layer, a first insulating layer, and a second insulating layer, the color resist layer is arranged on a side of the data line and the common wiring away from the substrate, the planar layer covers the color resist layer, the black light shielding layer is arranged on a side of the planar layer away from the substrate, the first insulating layer covers the black light shielding layer, the common electrode is arranged on a side of the first insulating layer away from the substrate, the second insulating layer covers the common electrode and the first insulating layer, and the pixel electrode is arranged on a side of the second insulating layer away from the substrate;

[0018] The array substrate is further provided with a first via hole and a second via hole, the first via hole penetrating the second insulating layer, the first insulating layer and the flat layer and exposing the common wiring, and the second via hole penetrating the second insulating layer and the first insulating layer and exposing the shielding line or the connecting line;

[0019] The array substrate further includes a transfer line disposed in the same layer as the pixel electrode, wherein the transfer line is connected to the common wiring through the first via hole, and the transfer line is connected to the shielding line or the connecting line through the second via hole.

[0020] Optionally, in some embodiments of the present application, the array substrate is further provided with a third via hole, the third via hole penetrates the second insulating layer and exposes the common electrode, and the adapter is connected to the common electrode through the third via hole.

[0021] Optionally, in some embodiments of the present application, the array substrate further includes a first isolation layer and a second isolation layer, the first isolation layer is arranged between the thin film transistor structure layer and the color resistance layer, the first isolation layer covers the data line and the common wiring, the second isolation layer is arranged between the black light shielding layer and the flat layer, and the second isolation layer covers the flat layer;

[0022] The thin film transistor structure layer includes a thin film transistor, and the array substrate is also provided with a contact hole, which passes through the second insulating layer, the first insulating layer, the second isolation layer, the planar layer and the first isolation layer, and the pixel electrode is connected to the output electrode of the thin film transistor through the contact hole.

[0023] Optionally, in some embodiments of the present application, the common wiring is arranged on the same layer as the data line, the array substrate further comprises a color resist layer, a first insulating layer, a planar layer, and a second insulating layer, the color resist layer is arranged on a side of the data line and the common wiring away from the substrate, the first insulating layer covers the color resist layer, the black light shielding layer is arranged on a side of the first insulating layer away from the substrate, the planar layer covers the black light shielding layer and the first insulating layer, the common electrode is arranged on a side of the planar layer away from the substrate, the second insulating layer covers the common electrode and the planar layer, and the pixel electrode is arranged on a side of the second insulating layer away from the substrate;

[0024] The array substrate is further provided with a first via hole and a second via hole, the first via hole penetrates the first insulating layer and the color resist layer and exposes the common wiring, and the second via hole penetrates the planar layer and exposes the shielding line or the connecting line;

[0025] The shielding line or the connecting line is connected to the common line through the first via hole, and the common electrode is correspondingly connected to the shielding line or the connecting line through the second via hole.

[0026] Optionally, in some embodiments of the present application, the array substrate further includes a first isolation layer, the first isolation layer is arranged between the thin film transistor structure layer and the color resistance layer, the first isolation layer covers the data line and the common wiring, the array substrate is further provided with a first contact hole and a second contact hole, the first contact hole penetrates the first insulating layer and the color resistance layer, the second contact hole penetrates the second insulating layer and the planar layer, and in the orthographic projection direction of the array substrate, the first contact hole is located outside the second contact hole;

[0027] The black light shielding layer further includes a transition portion spaced apart from the shielding line, the transition portion is connected to the output electrode of the thin film transistor through the first contact hole, and the pixel electrode is connected to the transition portion through the second contact hole.

[0028] Optionally, in some embodiments of the present application, any two shielding lines are insulated from each other, and the shielding lines are multiplexed as touch control lines.

[0029] Optionally, in some embodiments of the present application, the black light-shielding layer is a stacked structure of a metal oxide or metal layer and an inorganic insulating layer.

[0030] Correspondingly, an embodiment of the present application further provides a display panel, which includes an opposing substrate and an array substrate as described in any one of the above embodiments.

[0031] In the embodiment of the present application, shielding lines of a black shading layer are integrated into the array substrate to shield the data lines, so that the curved display panel avoids vertical misalignment between the black matrix and the data lines, and maintains or improves the aperture ratio of the display panel; in addition, the shielding lines are connected to the common signal, so that during the display process, the shielding lines have a constant voltage signal, reducing the risk of interference signals entering the shielding lines, thereby reducing the influence of the black shading layer on the driving electric field. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a structural schematic diagram of a display panel provided by the related technology;

[0033] Figure 2 is a schematic diagram of a top view of the structure of an array substrate provided in an embodiment of the present application;

[0034] Figure 3 is a schematic diagram of the cross-sectional structure of an array substrate provided in an embodiment of the present application;

[0035] Figure 4 is another schematic diagram of a top view of the structure of the array substrate provided in an embodiment of the present application;

[0036] Figure 5 is another schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present application;

[0037] Figure 6 is another schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present application;

[0038] Figure 7 is a schematic diagram of a top view of the structure of a display panel provided in an embodiment of the present application;

[0039] Figure 8 It is a schematic diagram of the cross-sectional structure of the display panel provided in the embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0041] The embodiments of the present application provide an array substrate and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0042] like Figure 1 As shown, in the related technology of liquid crystal panel, the array substrate Ar and the color film substrate Cf are arranged relative to each other, and liquid crystal Lc is arranged between the array substrate Ar and the color film substrate Cf. Among them, the key film layer that affects the display aperture ratio is the black matrix layer BM of the color film substrate Cf. When the screen is bent, the array substrate Ar and the color film substrate Cf are misaligned, resulting in the alignment of the black matrix layer BM and the data line Da of the array substrate Ar being offset. Widening the black matrix layer BM can ensure that the black matrix layer BM blocks the data line Da, but it will result in a loss of aperture ratio.

[0043] The embodiment of the present application uses a black shading layer whose shielding lines are integrated into the array substrate to shield the data lines, so that the curved display panel avoids vertical misalignment between the black matrix and the data lines, and maintains or improves the aperture ratio of the display panel; in addition, the shielding lines are connected to the common signal, so that during the display process, the shielding lines have a constant voltage signal, reducing the risk of interference signals entering the shielding lines, thereby reducing the influence of the black shading layer on the driving electric field.

[0044] Please refer to Figure 2 and Figure 3 An embodiment of the present application provides an array substrate 100 , which includes a substrate 11 , a thin film transistor structure layer 12 , a black light shielding layer 13 , a common electrode 14 and a pixel electrode 15 .

[0045] The thin film transistor structure layer 12 is disposed on the substrate 11 . The thin film transistor structure layer 12 includes a data line 121 .

[0046] The black light shielding layer 13 is disposed on the side of the thin film transistor structure layer 12 away from the substrate 11. The black light shielding layer 13 includes a shielding line 131. Figure 2 ), the shielding line 131 is extended along the extension direction of the data line 121, and the black shielding layer 13 covers the data line 121.

[0047] The common electrode 14 is disposed in a different layer from the data line 121 and the black light shielding layer 13. The pixel electrode 15 is disposed in a different layer from the data line 121 and the black light shielding layer 13.

[0048] The data line 121 is configured to access a common signal.

[0049] The array substrate 100 of the embodiment of the present application uses a black shading layer 13 with a shielding line 131 integrated in the array substrate 100 to shield the data line 121, so that the curved display panel avoids vertical misalignment between the black matrix and the data line, and maintains or improves the aperture ratio of the display panel; in addition, the shielding line 131 is connected to the common signal, so that during the display process, the shielding line 131 has a constant voltage signal, reducing the risk of interference signals entering the shielding line 131, thereby reducing the influence of the black shading layer 13 on the driving electric field.

[0050] It should be understood that the common signal is a constant voltage signal, and the common electrode 14 is also connected to the same common signal. The driving electric field refers to the voltage difference between the common electrode 14 and the pixel electrode 15, so that an electric field is formed between the two to drive the liquid crystal to deflect.

[0051] Optionally, the black light shielding layer 13 is a stacked structure of metal oxide or a metal layer and an inorganic insulating layer, such as molybdenum oxide or molybdenum / silicon nitride / molybdenum stacked layers.

[0052] Optionally, the pixel electrode 15 and the common electrode 14 can be arranged in different layers or in the same layer. When they are arranged in different layers, it is an FFS driving architecture, and when they are arranged in the same layer, it is an IPS driving architecture. This application takes the pixel electrode 15 and the common electrode 14 arranged in different layers as an example for explanation.

[0053] Optionally, the thin film transistor structure layer 12 includes a thin film transistor TFT, which may be a top gate, bottom gate or dual gate thin film transistor. The present application embodiment is described by taking the top gate thin film transistor TFT as an example, but is not limited thereto.

[0054] The thin film transistor structure layer 12 includes a light blocking layer Ls, a buffer layer Bu, an active layer P1, an inorganic layer Gi, a gate Ge, a scanning line Sc, an interlayer dielectric layer Ild and a metal layer Js, which are arranged on the substrate 11. The metal layer Js includes a source electrode 123, a drain electrode 124, a common wiring 122 and a data line 121.

[0055] The gate Ge and the scan line Sc are arranged in the same layer. The gate Ge and the scan line Sc are formed by the same metal material layer and patterned by the same photomask. The scan line Sc is connected to the gate Ge.

[0056] Optionally, one of the source electrode 123 and the drain electrode 124 is an input electrode, and the other is an output electrode. This application is described by taking the example that the source electrode 123 is the input electrode of the thin film transistor TFT, and the drain electrode 124 is the output electrode of the thin film transistor TFT.

[0057] In one embodiment of the present application, the common electrode 14 is arranged on the side of the black light shielding layer 13 away from the substrate 11, the pixel electrode 15 is arranged in a different layer from the common electrode 14 and is located on the side of the common electrode 14 away from the substrate 11, and the thin film transistor structure layer 12 also includes a common wiring 122.

[0058] The black light shielding layer 13 further includes a connection line 132 connected to the plurality of shielding lines 131 , and the common wiring 122 is electrically connected to the connection line 132 .

[0059] This embodiment uses the common line 122 to connect to the connection line 132, thereby avoiding the use of the common line 122 to directly connect multiple shielding lines 131, and simplifying the connection structure.

[0060] Optionally, the common wiring 122 is arranged in the same layer as the data line 121. The array substrate 100 further includes a color resist layer sz, a planar layer pt, a first insulating layer j1, and a second insulating layer j2. The color resist layer sz is arranged on a side of the data line 121 and the common wiring 122 away from the substrate 11. The planar layer pt covers the color resist layer sz. The black light shielding layer 13 is arranged on a side of the planar layer pt away from the substrate 11. The first insulating layer j1 covers the black light shielding layer 13. The common electrode 14 is arranged on a side of the first insulating layer j1 away from the substrate 11. The second insulating layer j2 covers the common electrode 14 and the first insulating layer j1. The pixel electrode 15 is arranged on a side of the second insulating layer j2 away from the substrate 11.

[0061] The array substrate 100 is further provided with a first via hole k1 and a second via hole k2. The first via hole k1 penetrates the first insulating layer j1 and the planar layer pt and exposes the common trace 122. The second via hole k2 penetrates the first insulating layer j1 and exposes the connection line 132.

[0062] The array substrate 100 further includes a transfer line zjx disposed in the same layer and connected to the common electrode 14. The transfer line zjx is connected to the common wiring 122 through a first via hole k1. The transfer line zjx is connected to the connection line 132 through a second via hole k2.

[0063] In one embodiment of the present application, the array substrate 100 further includes a first isolation layer gl1 and a second isolation layer gl2. The first isolation layer gl1 is disposed between the thin film transistor structure layer 12 and the color resist layer sz. The first isolation layer gl1 covers the data line 121 and the common wiring 122. The second isolation layer gl2 is disposed between the black light shielding layer 13 and the flat layer pt, and the second isolation layer gl2 covers the flat layer pt.

[0064] The first isolation layer gl1 is used to isolate the color resist layer sz and the metal layer Js from each other. The second isolation layer gl2 is used to isolate the black light shielding layer 13 and the flat layer pt from each other.

[0065] For example, the color resist layer sz and the planar layer pt are both made of organic materials, and their vapor permeability is poorer than that of inorganic layers. Therefore, a first isolation layer gl1 and a second isolation layer gl2 made of inorganic materials are added to reduce the risk of water vapor corroding the black light shielding layer 13 and the metal layer Js.

[0066] In addition, the first isolation layer gl1, the second isolation layer gl2 and the first insulating layer j1 are prepared using one mask so that the first via k1 penetrates the first isolation layer gl1, the second isolation layer gl2 and the first insulating layer j1, and the second via k2 penetrates the first insulating layer j1, thereby saving masks.

[0067] Optionally, the switching line zjx and the common electrode 14 are formed by patterning the same transparent conductive layer.

[0068] Optionally, in one embodiment, the adapter line zjx is also connected to the common electrode 14, that is, the adapter line zjx is simultaneously connected to the common wiring 122, the connecting line 132 and the common electrode 14, thereby avoiding the risk of multiple punching.

[0069] In one embodiment of the present application, the array substrate 100 is further provided with a contact hole c1, which penetrates the second insulating layer j2, the first insulating layer j1, the second isolation layer gl2, the planar layer pt and the first isolation layer gl1. The pixel electrode 15 is connected to the output electrode of the thin film transistor tft through the contact hole c1.

[0070] Optionally, compared to the above embodiments, Figure 4 As shown, the difference in another embodiment of the present application is that the common wiring 122 is connected to the shielding wire 131. That is, one common wiring 122 is correspondingly connected to one shielding wire 131.

[0071] That is, the black light shielding layer 13 does not need to be provided with additional connection lines 132. One shielding line 131 is connected to an independent common signal, any two shielding lines 131 are insulated from each other, and the shielding lines 131 are not electrically connected to the common electrode 14.

[0072] The shielding line 131 can be reused as a touch line, so that there is no need to set up an additional touch line, which can further improve the aperture ratio.

[0073] Optional, based on Figure 3 Corresponding to the film layer structure of the above embodiment, the second via hole k2 penetrates the first insulating layer j1 and exposes the shielding line 131. The adapter line zjx is connected to the shielding line 131 through the second via hole k2.

[0074] Please refer to Figure 5 In another embodiment of the present application, the common wiring 122 is arranged in the same layer as the data line 121. The array substrate 100 also includes a color resist layer sz, a planar layer pt, a first insulating layer j1 and a second insulating layer j2. The color resist layer sz is arranged on a side of the data line 121 and the common wiring 122 away from the substrate 11. The planar layer pt covers the color resist layer sz. The black light shielding layer 13 is arranged on a side of the planar layer pt away from the substrate 11. The first insulating layer j1 covers the black light shielding layer 13. The common electrode 14 is arranged on a side of the first insulating layer j1 away from the substrate 11. The second insulating layer j2 covers the common electrode 14 and the first insulating layer j1. The pixel electrode 15 is arranged on a side of the second insulating layer j2 away from the substrate 11.

[0075] The array substrate 100 further includes a first isolation layer gl1 and a second isolation layer gl2. The first isolation layer gl1 is disposed between the thin film transistor structure layer 12 and the color resist layer sz. The first isolation layer gl1 covers the data line 121 and the common wiring 122. The second isolation layer gl2 is disposed between the black light shielding layer 13 and the flat layer pt. The second isolation layer gl2 covers the flat layer pt.

[0076] The thin film transistor structure layer 12 includes a thin film transistor tft. The array substrate 100 is also provided with a contact hole c1, which penetrates the second insulating layer j2, the first insulating layer j1, the second isolation layer gl2, the planar layer pt and the first isolation layer gl1. The pixel electrode 15 is connected to the output electrode of the thin film transistor tft through the contact hole c1.

[0077] Compared with the above-mentioned embodiments, another embodiment of the present application is different in that: the array substrate 100 is further provided with a first via hole k1 and a second via hole k2. The first via hole k1 penetrates the second insulating layer j2, the first insulating layer j1 and the flat layer pt and exposes the common trace 122. The second via hole k2 penetrates the second insulating layer j2 and the first insulating layer j1 and exposes the shielding line 131 or the connecting line 132.

[0078] The array substrate 100 further includes a transfer line zjx disposed in the same layer as the pixel electrode 15. A transfer line zjx is connected to the common wiring 122 through a first via hole k1. The transfer line zjx is connected to the shielding line 131 or the connecting line 132 through a second via hole k2.

[0079] Optionally, the second via hole k2 penetrates the second insulating layer j2 and the first insulating layer j1 and exposes the connecting line 132. The transfer line zjx is connected to the connecting line 132 through the second via hole k2.

[0080] It should be noted that, in some embodiments, when a shielding line 131 corresponds to an independent common signal, any two shielding lines 131 are insulated from each other, and there is no electrical connection between the shielding line 131 and the common electrode 14, the shielding line 131 can be reused as a touch control line.

[0081] Optionally, in an embodiment of the present application, the array substrate 100 is further provided with a third via hole k3, and the third via hole k3 penetrates the second insulating layer j2 and exposes the common electrode 14. The adapter line zjx is connected to the common electrode 14 through the third via hole k3.

[0082] That is to say, the adapter line zjx simultaneously connects the common line 122, the connection line 132 and the common electrode 14, reducing the risk of multiple punching. The second insulating layer j2, the first insulating layer j1, the first isolation layer gl1 and the second isolation layer gl2 are patterned using the same mask to form the first via k1, the second via k2 and the third via k3, saving the mask.

[0083] Optionally, the switching line zjx and the pixel electrode 15 are formed by patterning the same transparent conductive layer using the same photomask.

[0084] Please refer to Figure 6 , another embodiment of the present application is different from the above embodiment in that the common wiring 122 is arranged in the same layer as the data line 121. The array substrate 100 also includes a color resist layer sz, a first insulating layer j1, a planar layer pt and a second insulating layer j2. The color resist layer sz is arranged on a side of the data line 121 and the common wiring 122 away from the substrate 11. The first insulating layer covers the color resist layer sz. The black light shielding layer 13 is arranged on a side of the first insulating layer j1 away from the substrate 11. The planar layer pt covers the black light shielding layer 13 and the first insulating layer j1. The common electrode 14 is arranged on a side of the planar layer pt away from the substrate 11. The second insulating layer j2 covers the common electrode 14 and the planar layer pt. The pixel electrode 15 is arranged on a side of the second insulating layer j2 away from the substrate 11.

[0085] The array substrate 100 is further provided with a first via hole k1 and a second via hole k2. The first via hole k1 penetrates the first insulating layer j1 and the color resist layer sz and exposes the common wiring 122. The second via hole k2 penetrates the planar layer pt and exposes the shielding line 131 or the connecting line 132.

[0086] The shielding line 131 or the connecting line 132 is connected to the common wiring 122 through the first via hole k1 , and the common electrode 14 is correspondingly connected to the shielding line 131 or the connecting line 132 through the second via hole k2 .

[0087] Optionally, the second via hole k2 penetrates the planar layer pt and exposes the connection line 132. The connection line 132 is connected to the common wiring 122 through the first via hole k1, and the common electrode 14 is correspondingly connected to the connection line 132 through the second via hole k2. Such a setting can be the number of holes.

[0088] Optionally, the array substrate 100 further includes a first isolation layer gl1 , which is disposed between the thin film transistor structure layer 12 and the color resist layer sz. The first isolation layer gl1 covers the data line 121 and the common wiring 122 .

[0089] The first isolation layer gl1 is used to isolate the color resist layer sz and the metal layer Js from each other. For example, the color resist layer sz is an organic material, and its vapor permeability is poorer than that of the inorganic layer, so the first isolation layer gl1 of inorganic material is added to reduce the risk of water vapor corroding the metal layer Js.

[0090] The array substrate 100 is further provided with a first contact hole c11 and a second contact hole c12. The first contact hole c11 penetrates the first insulating layer j1 and the color resist layer sz. The second contact hole c12 penetrates the second insulating layer j2 and the planar layer pt. In the orthographic projection direction of the array substrate 100, the first contact hole c11 is located outside the second contact hole c12.

[0091] The black light shielding layer 13 further includes a transition portion zjb spaced apart from the shielding line 131. The transition portion zjb is connected to the output electrode of the thin film transistor tft through the first contact hole c11, and the pixel electrode 15 is connected to the transition portion zjb through the second contact hole c12.

[0092] Among them, the first contact hole c11 and the second contact hole c12 are staggered, which reduces the risk of the pixel electrode 15 being easily broken due to climbing, and improves the yield and performance compared with the deep hole nesting design (the above embodiment).

[0093] Please refer to Figure 7 and Figure 8 Accordingly, the embodiment of the present application further provides a display panel 1000, which includes an opposing substrate 200 and an array substrate 100 as described in any one of the above embodiments.

[0094] It should be noted that the display panel 1000 is a liquid crystal display panel. The array substrate 100 of the display panel 1000 of the present embodiment is similar or identical in structure to the array substrate 100 of any of the above embodiments. Figure 3 The corresponding embodiments are provided as examples but are not limited thereto.

[0095] In addition, the counter substrate 200 further includes a base 21 , a black matrix layer 22 formed on a side of the base 21 close to the array substrate 100 , and a spacer 23 disposed on a side of the black matrix layer 22 close to the array substrate 100 .

[0096] In the top view of the display panel 1000 , the black matrix layer 22 covers the scan lines Sc and the thin film transistors tft.

[0097] Optionally, the spacer 23 includes a main spacer 231 and a sub-spacer 232, and the height of the main spacer 231 is greater than the height of the sub-spacer 232. The sub-spacer 232 is aligned with the contact hole c1.

[0098] The display panel 1000 of the embodiment of the present application uses a black shading layer 13 with a shielding line 131 integrated in the array substrate 100 to shield the data line 121, so that the curved display panel avoids vertical misalignment between the black matrix and the data line, and maintains or improves the aperture ratio of the display panel; in addition, the shielding line 131 is connected to a common signal, so that during the display process, the shielding line 131 has a constant voltage signal, reducing the risk of interference signals entering the shielding line 131, thereby reducing the influence of the black shading layer 13 on the driving electric field.

[0099] The above is a detailed introduction to an array substrate and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A thin film transistor structure layer is arranged on the substrate, and the thin film transistor structure layer includes a data line, a common line and a thin film transistor; a black light shielding layer, arranged on a side of the thin film transistor structure layer away from the substrate, the black light shielding layer comprising shielding lines and connecting lines connected to a plurality of the shielding lines, the common wiring being electrically connected to the connecting lines, the shielding lines extending along the extending direction of the data lines in a top view of the array substrate, the shielding lines covering the data lines, and the connecting lines being located outside the thin film transistors; A common electrode is disposed in different layers from the data line and the black light shielding layer, and the common electrode is disposed on a side of the black light shielding layer away from the substrate; as well as A pixel electrode is disposed in a different layer from the data line and the black light shielding layer, and the pixel electrode is disposed in a different layer from the common electrode and is located on a side of the common electrode away from the substrate; Wherein, the shielding line is configured to access a public signal.

2. The array substrate according to claim 1, characterized in that: The common wiring is arranged on the same layer as the data wiring, and the array substrate further comprises a color resist layer, a planar layer, a first insulating layer, and a second insulating layer, the color resist layer is arranged on a side of the data wiring and the common wiring away from the substrate, the planar layer covers the color resist layer, the black light shielding layer is arranged on a side of the planar layer away from the substrate, the first insulating layer covers the black light shielding layer, the common electrode is arranged on a side of the first insulating layer away from the substrate, the second insulating layer covers the common electrode and the first insulating layer, and the pixel electrode is arranged on a side of the second insulating layer away from the substrate; The array substrate is further provided with a first via hole and a second via hole, the first via hole penetrates the first insulating layer and the planar layer and exposes the common wiring, and the second via hole penetrates the first insulating layer and exposes the connecting wire; The array substrate further includes a transfer line on the same layer as the common electrode, the transfer line is connected to the common wiring through the first via hole, and the transfer line is connected to the connection line through the second via hole.

3. The array substrate according to claim 1, characterized in that: The common wiring is arranged on the same layer as the data wiring, and the array substrate further comprises a color resist layer, a planar layer, a first insulating layer, and a second insulating layer, the color resist layer is arranged on a side of the data wiring and the common wiring away from the substrate, the planar layer covers the color resist layer, the black light shielding layer is arranged on a side of the planar layer away from the substrate, the first insulating layer covers the black light shielding layer, the common electrode is arranged on a side of the first insulating layer away from the substrate, the second insulating layer covers the common electrode and the first insulating layer, and the pixel electrode is arranged on a side of the second insulating layer away from the substrate; The array substrate is further provided with a first via hole and a second via hole, the first via hole penetrating the second insulating layer, the first insulating layer and the planar layer and exposing the common wiring, and the second via hole penetrating the second insulating layer and the first insulating layer and exposing the connecting wire; The array substrate further includes a transfer line disposed on the same layer as the pixel electrode, wherein the transfer line is connected to the common wiring through the first via hole, and the transfer line is connected to the connection line through the second via hole.

4. The array substrate according to claim 3, characterized in that: The array substrate is further provided with a third via hole, the third via hole penetrates the second insulating layer and exposes the common electrode, and the adapter is connected to the common electrode through the third via hole.

5. The array substrate according to any one of claims 2 to 4, characterized in that: The array substrate further includes a first isolation layer and a second isolation layer, wherein the first isolation layer is disposed between the thin film transistor structure layer and the color resist layer, and covers the data line and the common wiring, and the second isolation layer is disposed between the black light shielding layer and the flat layer, and covers the flat layer; The thin film transistor structure layer includes a thin film transistor, and the array substrate is also provided with a contact hole, which passes through the second insulating layer, the first insulating layer, the second isolation layer, the planar layer and the first isolation layer, and the pixel electrode is connected to the output electrode of the thin film transistor through the contact hole.

6. The array substrate according to claim 1, characterized in that: The common wiring is arranged on the same layer as the data wiring, and the array substrate further comprises a color resist layer, a first insulating layer, a planar layer, and a second insulating layer, the color resist layer is arranged on a side of the data wiring and the common wiring away from the substrate, the first insulating layer covers the color resist layer, the black light shielding layer is arranged on a side of the first insulating layer away from the substrate, the planar layer covers the black light shielding layer and the first insulating layer, the common electrode is arranged on a side of the planar layer away from the substrate, the second insulating layer covers the common electrode and the planar layer, and the pixel electrode is arranged on a side of the second insulating layer away from the substrate; The array substrate is further provided with a first via hole and a second via hole, the first via hole penetrates the first insulating layer and the color resist layer and exposes the common wiring, and the second via hole penetrates the planar layer and exposes the connecting wire; The connecting line is connected to the common wiring through the first via hole, and the common electrode is correspondingly connected to the connecting line through the second via hole.

7. The array substrate according to claim 6, characterized in that: The array substrate further includes a first isolation layer, which is disposed between the thin film transistor structure layer and the color resist layer, and covers the data line and the common wiring. The array substrate is further provided with a first contact hole and a second contact hole, the first contact hole penetrates the first insulating layer and the color resist layer, and the second contact hole penetrates the second insulating layer and the planar layer, and the first contact hole is located outside the second contact hole in the orthographic projection direction of the array substrate; The black light shielding layer further includes a transition portion spaced apart from the shielding line, the transition portion is connected to the output electrode of the thin film transistor through the first contact hole, and the pixel electrode is connected to the transition portion through the second contact hole.

8. The array substrate according to any one of claims 1 to 3, characterized in that: Any two shielding lines are insulated from each other, and the shielding lines are reused as touch control lines.

9. The array substrate according to any one of claims 1 to 4, 6 to 7, characterized in that: The black light shielding layer is a stacked structure of a metal oxide or metal layer and an inorganic insulating layer.

10. A display panel, characterized in that: It comprises an opposing substrate and an array substrate as claimed in any one of claims 1 to 9.

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