Numerical simulation method of short channel negative capacitance gate-all-around field effect transistor

Abstract

The application provides a numerical simulation method of a short channel negative capacitance surrounding gate field effect transistor, constructs a source-drain current model of a short channel negative capacitance surrounding gate field effect transistor NC-GAAFET with the structure of MFIS; the source-drain current model of a conventional GAAFET is analyzed, the electrostatic potential obtained by solving a cylindrical two-dimensional Poisson equation is obtained; the source-drain current I ds is obtained according to the boundary conditions near the source region and the drain region, and the drain-induced barrier lowering effect parameter is calculated; the source-drain current model of the conventional short channel GAAFET is coupled, and the source-drain current model of the NC-GAAFET is obtained by combining the flexoelectric effect; the subthreshold swing of the NC-GAAFET is calculated; step 6: repeating steps 2 to 5, adjusting different ferroelectric layer thicknesses, structure parameters and flexoelectric coefficients, and obtaining electrical properties under different conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of numerical simulation of negative capacitance transistor performance, in particular but not exclusively to a numerical simulation method of short channel negative capacitance gate-all-around field effect transistor. BACKGROUND

[0002] Negative capacitance field effect transistor is a promising low power application device, which uses the negative capacitance behavior of ferroelectric material to enhance the surface potential. The experiment of negative capacitance field effect transistor shows subthreshold swing (SS) lower than 60mv / dev and high on-current. Gate-all-around (GAA) structure is considered as a potential candidate for the next generation of CMOS, which can improve the drain-induced barrier lowering, subthreshold swing (SS) and I ON / I OFF , which provides effective inhibition of short channel effect. The experimental and numerical research of GAAFET-based CMOS circuit shows that it has better device performance in off-state, lower circuit delay and faster switching speed compared with fin field effect transistor (FinFET), which can integrate the advantages of GAA architecture and NCFET to optimize performance.

[0003] The analytical model of source-drain current of long channel device will lose its accuracy when the device size is reduced to nanometer size due to the influence of short channel effect, especially when the device works in the subthreshold region. Since the NCFET was proposed, a large number of reports on NC-FET research have appeared, but these rarely model the short channel NCFET of MFIS structure. At the same time, considering that due to the flexoelectric effect, the strain gradient is equivalent to providing an internal electric field in the material, which may affect the electrical characteristics of the device.

[0004] Therefore, it is necessary to provide a new structure or method to solve at least part of the above problems. SUMMARY

[0005] In view of one or more problems in the prior art, the present application provides a numerical simulation method of short channel negative capacitance gate-all-around field effect transistor (NC-GAAFET), which analytically models the source-drain current model of NC-GAAFET, and considers the influence of flexoelectricity on electrical performance.

[0006] The technical solution for achieving the purpose of the present application is as follows:

[0007] A numerical simulation method of short channel negative capacitance gate-all-around field effect transistor, comprising:

[0008] Step 1: constructing a source-drain current model of a short-channel negative capacitance gate-all-around field effect transistor (NC-GAAFET) with a structure of metal-ferroelectric-insulating layer-semiconductor (MFIS);

[0009] Step 2: performing Poisson equation analysis on a source-drain current model of a conventional short-channel gate-all-around field effect transistor (GAAFET), and obtaining electrostatic potential of the conventional short-channel GAAFET by solving a cylindrical two-dimensional Poisson equation;

[0010] Step 3: obtaining source-drain current I ds of the conventional short-channel GAAFET according to boundary conditions near source and drain regions of the conventional short-channel GAAFET, and calculating a drain-induced barrier lowering effect parameter;

[0011] Step 4: coupling the source-drain current model of the conventional short-channel GAAFET, and obtaining a source-drain current model of the NC-GAAFET in combination with a flexoelectric effect;

[0012] Step 5: calculating a subthreshold swing of the NC-GAAFET;

[0013] Step 6: repeating steps 2 to 5, adjusting a ferroelectric layer thickness, a structure parameter and a flexoelectric coefficient of the short-channel NC-GAAFET source-drain current model, and obtaining electrical performance of the short-channel NC-GAAFET under different conditions.

[0014] Further, the numerical simulation method of the short-channel negative capacitance gate-all-around field effect transistor provided by the application, the step 2 of obtaining the electrostatic potential of the conventional short-channel GAAFET by solving the cylindrical two-dimensional Poisson equation comprises:

[0015] Step 2-1: the cylindrical two-dimensional Poisson equation is as follows:

[0016]

[0017] wherein 0 < r < R, 0 < y < L, r is a length in a radial direction of the channel, R is a radius of a channel of the GAAFET, y is a length in a length direction of the channel, L is a length of a channel of the GAAFET, i.e., a length of an electron flow direction, N b is a doping concentration of the silicon channel, ε Si is a dielectric constant of the silicon material, ψ(·) is a potential function, representing a potential at a (r, y) position in the semiconductor device, and q is an elementary charge;

[0018] A parabolic modeling method is used to obtain the potential in the silicon channel along the source-drain direction, and an initial solution form of the cylindrical two-dimensional Poisson equation is as follows:

[0019] ψ(r, y) = r 2 A(r, y) + B(r, y)

[0020] Among them, A(r,y) and B(r,y) are unknown functions that depend on the radial coordinate r and the axial coordinate y. r represents the radial length of the channel, and y represents the longitudinal length of the channel.

[0021] Step 2-2: According to Gauss's theorem, the channel surface satisfies the following boundary conditions:

[0022]

[0023] in, Represents the capacitance per unit area of ​​the gate insulation layer, ε in represents the dielectric constant of the insulating layer, R represents the radius of the gate electrode, and t in Indicates the thickness of the insulating layer; V mos Represents the effective gate voltage, V mos =V mos实际 -φ ms , V mos实际 Indicates the actual gate voltage of GAAFET, φ ms is the work function difference between gate and silicon; ψ s is the channel surface potential; ε Si is the dielectric constant of silicon material;

[0024] Step 2-3: Approximate A(r,y) and B(r,y) as A r (y) and B r (y), get the variables r and A r The two-dimensional electric potential function of (y):

[0025]

[0026] And the solved Poisson equation is obtained:

[0027]

[0028] Step 2-4: Calculate the channel center potential function ψ0(y) and the surface potential distribution function ψ at the interface between the channel and the gate insulation layer based on the solved Poisson equation R (y), then the two-dimensional potential distribution function is:

[0029]

[0030] where ψ(r,y) represents the solution of the cylindrical two-dimensional Poisson equation, ψ R (y) represents the surface potential distribution function at the interface between the channel and the gate insulating layer, ψ0(y) represents the potential function at the center of the channel, R represents the distance at the interface between the channel and the gate insulating layer, and r represents the distance from the center of the channel.

[0031] Further, the numerical simulation method of the short channel negative capacitance surrounding gate field effect transistor of the present application, the channel center potential function ψ0(y) in steps 2-4 is:

[0032]

[0033] Wherein, C1 and C2 are constants.

[0034] Further, the numerical simulation method of the short channel negative capacitance surrounding gate field effect transistor of the present application, C1 and C2 are calculated by the boundary conditions along the source-drain direction, specifically comprising:

[0035] Solving the boundary conditions near the source and drain regions in the channel center:

[0036] ψ0(0) = V bi

[0037] ψ0(L) = V bi + V ds

[0038] Wherein, ψ0(0) represents the value of the potential function at the boundary r = 0 of the source and drain regions, ψ0(L) represents the value at the boundary r = L of the source and drain regions, r is the radial direction of the channel, L represents the length of the source and drain regions in the channel center, V bi represents the built-in potential value between the channel and the source-drain region, V ds is the source-drain voltage;

[0039] Then the constants C1 and C2 are:

[0040]

[0041]

[0042] Wherein, Sinh represents the hyperbolic sine function.

[0043] Further, the numerical simulation method of the short channel negative capacitance surrounding gate field effect transistor of the present application, the surface potential distribution function ψ R (y) at the interface between the channel and the gate insulating layer in step 2-4 is:

[0044]

[0045] Wherein, C3 and C4 are constants.

[0046] Further, the numerical simulation method of the short channel negative capacitance surrounding gate field effect transistor of the present application, C3 and C4 are calculated according to the boundary conditions near the source and drain regions, specifically comprising:

[0047] Solving the boundary conditions near the source and drain regions at the channel and gate insulator interface:

[0048] ψ R (0) = V bi

[0049] ψ R (L) = V bi + V ds

[0050] Wherein, ψ R (0) represents the value of the potential function at the channel and gate insulator interface r = 0, ψ R (L) represents the value of the potential function at the channel and gate insulator interface r = L, r is the radial direction of the channel, L represents the length of the source and drain regions at the channel and gate insulator interface, V bi represents the built-in potential value between the channel and the source and drain regions, V ds is the source and drain voltage;

[0051] The constants C3 and C4 are obtained as follows:

[0052]

[0053]

[0054] Wherein, Sinh represents the hyperbolic sine function.

[0055] Further, in the numerical simulation method of the short channel negative capacitance gate-all-around field effect transistor of the present application, the source and drain current I ds and the drain-induced barrier lowering effect parameter DIBL are:

[0056]

[0057]

[0058] Wherein, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, V ds is the drain-source voltage, u is the electron mobility, n i is the intrinsic carrier concentration in silicon.

[0059] Further, in the numerical simulation method of the short channel negative capacitance gate-all-around field effect transistor of the present application, step 4, coupling the source and drain current model of the conventional short channel GAAFET and combining the flexoelectric effect to obtain the source and drain current model of the NC-GAAFET includes:

[0060] Step 4-1: coupling the conventional GAAFET model, then the gate surface charge density Q gmos model is:

[0061]

[0062] where L g represents the length from the gate to the drain;

[0063] Step 4-2: According to the L-K equation, the threshold voltage V fe with the mobile charge density Q gmos is expressed as:

[0064]

[0065] where the coefficients a0and b0are related to the Landau parameters of the ferroelectric material, f 12 is the flexoelectric coefficient, t fe represents the effective oxide thickness between the gate and the source / drain, t in represents the thickness of the insulating layer;

[0066] Step 4-3: The voltage balance condition for the short-channel NC-GAAFET with flexoelectric effect is:

[0067]

[0068] where V gs is the gate-source voltage, V mos represents the potential between the channel and the gate, V fe represents the threshold voltage, a HfO2 , and b HfO2 are the Landau parameters of HfO2, used to adjust the relationship between the mobile charge density and the threshold voltage.

[0069] Step 4-4: When the gate voltage V gs of the NC-GAAFET, the effective gate voltage V mos of the GAAFET corresponds to the source-drain current I ds is:

[0070]

[0071] where k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, V ds is the drain-source voltage, u is the electron mobility, and n i is the intrinsic carrier concentration in silicon.

[0072] Further, the numerical simulation method of the short-channel negative capacitance surrounding-gate field effect transistor of the present application, the sub-threshold swing of the NC-GAAFET is calculated in step 5:

[0073]

[0074] Where SS0 represents the subthreshold swing of GAA-FET.

[0075] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0076] 1. This invention addresses the short-channel effect: Traditional analytical models for source-drain current in long-channel devices lose accuracy when device dimensions shrink to subnanometers, particularly in the subthreshold region. This invention proposes a short-channel NCFET model based on the MFIS structure, which more accurately describes the source-drain current behavior of devices at nanometer scale, thereby addressing the short-channel effect.

[0077] 2. This invention considers the influence of the flexoelectric effect on the device's electrical properties. The flexoelectric effect introduces internal electric fields within the material, potentially affecting device performance. By accounting for this effect, the model of this invention can more accurately predict the device's electrical properties, improving its performance and reliability.

[0078] 3. The present invention takes into account the advantages of negative capacitance and GAA structure: The present invention combines the advantages of negative capacitance effect and GAA structure to realize low-power, high-performance application devices. The negative capacitance behavior of ferroelectric materials is used to enhance the surface potential. At the same time, the GAA structure is used to provide superior electrostatic control to effectively suppress the short channel effect, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The accompanying drawings are used to provide a further understanding of the present invention and, together with the description, to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0080] Figure 1 A schematic diagram of the MFIS short-channel all-around gate field-effect transistor is shown.

[0081] Figure 2 shows different gate lengths L g Under y=L, GAA-FET g / 2The channel potential distribution along the radius r.

[0082] Figure 3 shows different gate lengths L g Surface potential distribution and center potential distribution of GAA-FET along the source-drain direction.

[0083] Figure 4 shows different ferroelectric layer thickness t fe Under the condition of NC-GAAFET, the subthreshold swing SS is related to the gate length L. g relationship.

[0084] Figure 5 The different flexoelectric coefficients f 12 The drain current I ds The relationship between the NC-GAAFET gate voltage V gs .

[0085] Figure 6 The different flexoelectric coefficients f 12 The relationship between the gate surface charge density Q and the NC-GAAFET gate voltage V gs .

[0086] Figure 7 The different flexoelectric coefficients f 12 The relationship between the subthreshold swing SS and the NC-GAAFET gate voltage V gs .

[0087] Figure 8 The different flexoelectric coefficients f 12 The relationship between the NC-GAAFET gate voltage and the effective gate voltage V mos of the conventional GAAFET.

[0088] Figure 9 The numerical simulation method flow chart of the short channel negative capacitance gate-all-around field effect transistor of the present application is shown. DETAILED DESCRIPTION

[0089] In order to further understand the present application, the preferred embodiments of the present application are described below in conjunction with the examples, but it should be understood that these descriptions are only for further illustrating the features and advantages of the present application, and are not limitations of the claims of the present application.

[0090] The description of this part is only for typical examples, and the present application is not limited to the scope described in the examples. The combination of different examples, the mutual replacement of some technical features in different examples, and the mutual replacement of the same or similar prior art means and some technical features in the examples are also within the description and protection scope of the present application.

[0091] The present application proposes a numerical simulation method of a short channel negative capacitance gate-all-around field effect transistor, which adds the influence of flexoelectricity on the short channel NC-GAAFET on the basis of the undoped cylindrical metal-ferroelectric-insulator-semiconductor (MFIS) GAA-NCFET short channel core model. As shown in Figure 9 The method comprises the following steps:

[0092] Step 1, first build a model of GAA-NCFET (as shown in Figure 1), the model is MFIS instead of MFMIS structure, because the presence of this metal floating gate can hinder the negative capacitance effect if the ferroelectric is leaky. It can also cause other problems, such as threshold voltage variation when there is charge trapping and de-trapping in the metal.

[0093] Step 2, model analysis of conventional short-channel GAAFET, electrostatic potential is obtained by solving the cylindrical two-dimensional Poisson equation.

[0094] Step 3, source-drain current Ids is obtained according to the boundary conditions near the source-drain, and the drain-induced barrier lowering effect parameter is calculated. The boundary conditions usually include the continuity requirements of potential and electric field on the interface, and the potential of the source region and the drain region, which is determined by the external circuit conditions.

[0095] Step 4, the source-drain current model of NC-GAAFET is obtained by coupling the model of conventional short-channel GAAFET with the consideration of flexoelectric effect.

[0096] Step 5, the subthreshold swing of NC-GAAFET is calculated.

[0097] Step 6, repeat steps 2 to 5, adjust different ferroelectric layer thickness, structure parameters and flexoelectric coefficient to obtain the electrical performance under different conditions.

[0098] Wherein, steps 2 to 5 are as follows:

[0099] First, the electrostatic potential obtained by solving the cylindrical two-dimensional Poisson equation.

[0100]

[0101] Where 0 < r < R, 0 < y < L, N b is the doping concentration of the silicon channel; ε Si is the dielectric constant of silicon material. Since the device is in the subthreshold region, the movable electron concentration can be ignored. The potential in the silicon channel along the source-drain direction can be modeled using a parabolic method, and the initial solution form of the two-dimensional Poisson equation can be guessed as:

[0102] ψ(r, y) = r 2 A(r, y) + B(r, y) (2)

[0103] Where A(r, y) and B(r, y) are strongly related to variable y and weakly related to variable r, so A(r, y) and B(r, y) can be approximated as A r (y) and B r (y), which can be obtained by solving the approximate two-dimensional Poisson equation under specific boundary conditions. In order to obtain functions A r (y) and B rThe analytical form of (y) is obtained by first substituting equation (2) into equation (1) to get

[0104]

[0105] According to Gauss theorem, the boundary condition for the channel surface should be satisfied:

[0106]

[0107] where C represents the unit area capacitance of the gate insulating layer, where V mos V mos eff is defined as the effective gate voltage, V mos实际 eff = V ms g - φ mos实际 , V ms g represents the actual gate voltage of the GAAFET, φ s is the difference between the gate and the silicon work function, ψ r is the channel surface potential, and B r (y) can be obtained according to equation (4):

[0108]

[0109] Substituting equation (5) back into equation (2) can obtain the two-dimensional potential function about the variables r and A r (y):

[0110]

[0111] Substituting equation (5) into equation (3) can obtain:

[0112]

[0113] At the center of the channel (i.e., when r = 0), let A r (y) = A0(y) and substitute it into equation (7) to obtain the relationship that the function A0(y) should satisfy:

[0114]

[0115] Solving equation (8) can obtain:

[0116]

[0117] where C1 and C2 are constants, which can be obtained by solving the boundary condition along the source-drain direction. Substituting equation (9) into equation (6) can obtain the approximate channel center potential:

[0118]

[0119] According to the boundary conditions near the source and drain regions:

[0120] ψ0(0) = V bi (11)

[0121] ψ0(L) = V bi + V ds (12)

[0122] where V bi represents the built-in potential value between the channel and the source-drain regions, V ds is the source-drain voltage. Thus, the two coefficients C1 and C2 can be obtained as:

[0123]

[0124]

[0125] At the interface between the channel and the gate insulating layer, r = R, at this time, let the function A r (y) = A R (y), then the function A R (y) should satisfy the equation:

[0126]

[0127] where Equation (15) can be solved to obtain the following form of solution:

[0128]

[0129] Substituting equation (16) into equation (6), the surface potential distribution function can be obtained as follows:

[0130]

[0131] According to the boundary conditions near the source and drain regions:

[0132] ψ R (0) = V bi (18)

[0133] ψ R (L) = V bi + V ds (19)

[0134] The coefficients C3 and C4 can be obtained as:

[0135]

[0136]

[0137]

[0138] Substituting equations (10) and (17) into equation (22), we get the two-dimensional potential distribution function. ds It can be obtained as:

[0139]

[0140] The drain-induced barrier lowering parameter DIBL can be calculated as:

[0141]

[0142] By coupling the conventional GAAFET model, the gate surface charge density Q gmos The model can be obtained:

[0143]

[0144] According to the LK equation, V fe The mobile charge density Q can be expressed as gmos Expressed as:

[0145]

[0146] The coefficients a0 and b0 are related to the Landau parameters of the ferroelectric material, f 12 is the flexoelectric coefficient.

[0147] The voltage balance condition of the short-channel NC-GAAFET considering the flexoelectric effect is:

[0148]

[0149] NC-GAAFET gate voltage V gs When the effective gate voltage of GAAFET is V mos The corresponding source-drain current I ds It can be obtained as:

[0150]

[0151] The subthreshold swing SS of NC-GAAFET is:

[0152]

[0153] where SS0 is the subthreshold swing of the GAA-FET.

[0154] like Figures 2 to 8 As shown in Figure 2, by adjusting the ferroelectric layer thickness, structural parameters and flexoelectric coefficient of the short channel NC-GAAFET source-drain current model, the electrical performance of the short channel NC-GAAFET under different conditions can be obtained. Figure 2Different gate length L g Channel potential distribution along radial direction r for lower GAA-FET at y = L g Channel potential distribution along radial direction r for lower GAA-FET at y = L Figure 3 Different gate length L g Surface potential distribution along source-drain direction and central potential distribution for lower GAA-FET Figure 4 Different ferroelectric layer thickness t fe Subthreshold swing SS vs. gate length L for lower NC-GAAFET g Subthreshold swing SS vs. gate length L for lower NC-GAAFET Figure 5 Different flexoelectric coefficient f 12 Source-drain current I vs. gate voltage V for NC-GAAFET ds Source-drain current I vs. gate voltage V for NC-GAAFET gs Source-drain current I vs. gate voltage V for NC-GAAFET Figure 6 Different flexoelectric coefficient f 12 Gate surface charge density Q vs. gate voltage V for NC-GAAFET gs Gate surface charge density Q vs. gate voltage V for NC-GAAFET Figure 7 Different flexoelectric coefficient f 12 Subthreshold swing SS vs. gate voltage V for NC-GAAFET gs Subthreshold swing SS vs. gate voltage V for NC-GAAFET Figure 8 Different flexoelectric coefficient f 12 Effective gate voltage V for conventional GAAFET corresponding to NC-GAAFET gate voltage mos .

[0155] The description and applications of the present application are illustrative, and not intended to limit the scope of the present application. The related descriptions of effects or advantages of the present application described in the specification can not be embodied in the actual application, and the related descriptions of effects or advantages of the present application are not used to limit the scope of the present application. Variations and changes of the embodiments disclosed herein are possible, and various components of the embodiments are known to those skilled in the art. It should be clear to those skilled in the art that the present application can be realized in other forms, structures, arrangements, proportions, and with other components, materials and parts, without departing from the spirit or essential characteristics of the present application. Other variations and changes of the embodiments disclosed herein can be made without departing from the scope and spirit of the present application.

Claims

1. A numerical simulation method for a short-channel negative capacitance gate field effect transistor, characterized in that: include: Step 1: Construct a source-drain current model of a short-channel negative capacitance gate-all-around field-effect transistor (NC-GAAFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. Step 2: Analyze the Poisson equation for the source-drain current model of the conventional short-channel gate-all-around field-effect transistor (GAAFET). The electrostatic potential of the conventional short-channel GAAFET is obtained by solving the cylindrical two-dimensional Poisson equation. Step 3: Obtain the source-drain current I according to the boundary conditions near the source and drain regions of a conventional short-channel GAAFET ds , and calculate the leakage-induced barrier lowering effect parameters; Step 4: Couple the source-drain current model of the conventional short-channel GAAFET and combine it with the flexoelectric effect to obtain the source-drain current model of the NC-GAAFET; include: Step 4-1: Couple the conventional GAAFET model, then the gate surface charge density Q gmos The model is: Among them, L g Indicates the length from gate to drain; Step 4-2: According to the LK equation, the threshold voltage V fe With the mobile charge density Q gmos Expressed as: Among them, the coefficients a0 and b0 are related to the Landau parameters of the ferroelectric material, f 12 is the flexoelectric coefficient, t fe represents the effective oxide thickness between the gate and the source / drain, t in Indicates the thickness of the insulation layer; Step 4-3: The voltage balance condition of the short-channel NC-GAAFET with flexoelectric effect is: Among them, V gs is the gate-source voltage, V mos Represents the potential between the channel and the gate, V fe represents the threshold voltage, α HfO2 , and β HfO2 is the Landau parameter of HfO2, which is used to adjust the relationship between mobile charge density and threshold voltage; Step 4-4: When the gate voltage V gs When the effective gate voltage V mos The corresponding source-drain current I ds for: Among them, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, V ds is the drain-source voltage, u is the electron mobility, n i is the intrinsic carrier concentration in silicon; Step 5: Calculate the subthreshold swing of NC-GAAFET; Step 6: Repeat steps 2 to 5 to adjust the ferroelectric layer thickness, structural parameters, and flexoelectric coefficient of the short-channel NC-GAAFET source-drain current model to obtain the electrical performance of the short-channel NC-GAAFET under different conditions.

2. The numerical simulation method of the short channel negative capacitance gate field effect transistor according to claim 1, characterized in that: Solving the cylindrical two-dimensional Poisson equation in step 2 yields the electrostatic potential of a conventional short-channel GAAFET: Step 2-1: The cylindrical two-dimensional Poisson equation is: Among them, 0 < r < R, 0 < y < L, r is the radial direction length of the channel, R is the radius of the GAAFET channel, y is the length direction length of the channel, L is the channel length of the GAAFET, that is, the length in the electron flow direction, N b is the doping concentration of the silicon channel, ε Si is the dielectric constant of the silicon material, ψ(·) is the electric potential function, representing the electric potential at the (r, y) position in the semiconductor device, and q is the elementary charge; The parabolic modeling method is used to obtain the potential along the source-drain direction in the silicon channel. The initial solution of the cylindrical two-dimensional Poisson equation is assumed to be: ψ(r,y)=r 2 A(r,y)+B(r,y) Among them, A(r,y) and B(r,y) are unknown functions that depend on the radial coordinate r and the axial coordinate y. r represents the radial length of the channel, and y represents the longitudinal length of the channel. Step 2-2: According to Gauss's theorem, the channel surface satisfies the following boundary conditions: in, Represents the capacitance per unit area of ​​the gate insulation layer, ε in represents the dielectric constant of the insulating layer, R represents the radius of the gate electrode, and t in Indicates the thickness of the insulating layer; V mos Represents the effective gate voltage, V mos =V mos实际 -φ ms , V mos实际 Indicates the actual gate voltage of GAAFET, φ ms is the work function difference between gate and silicon; ψ s is the channel surface potential; ε Si is the dielectric constant of silicon material; Step 2-3: Approximate A(r,y) and B(r,y) as A r (y) and B r (y), get the variables r and A r The two-dimensional electric potential function of (y): And the solved Poisson equation is obtained: Step 2-4: Calculate the channel center potential function ψ0(y) and the surface potential distribution function ψ at the interface between the channel and the gate insulation layer based on the solved Poisson equation R (y), then the two-dimensional potential distribution function is: where ψ(r,y) represents the solution of the cylindrical two-dimensional Poisson equation, ψ R (y) represents the surface potential distribution function at the interface between the channel and the gate insulating layer, ψ0(y) represents the potential function at the center of the channel, R represents the distance at the interface between the channel and the gate insulating layer, and r represents the distance from the center of the channel.

3. The numerical simulation method of the short channel negative capacitance gate field effect transistor according to claim 2, characterized in that: The channel center potential function ψ0(y) in steps 2-4 is: in, C1 and C2 are constants.

4. The numerical simulation method of the short channel negative capacitance gate field effect transistor according to claim 3, characterized in that: C1 and C2 are calculated using the boundary conditions along the source-drain direction, including: Solve the boundary conditions near the source and drain regions in the center of the channel: ψ0(0)=V bi ψ0(L)=V bi +V ds Where ψ0(0) represents the value of the potential function at the boundary r=0 between the source and drain regions, ψ0(L) represents the value at the boundary r=L between the source and drain regions, r is the radial direction of the channel, L represents the length of the source and drain regions at the center of the channel, V bi Represents the built-in potential between the channel and the source and drain regions, V ds is the source-drain voltage; Then the constants C1 and C2 are obtained as: Here, Sinh represents the hyperbolic sine function.

5. The numerical simulation method of the short channel negative capacitance gate field effect transistor according to claim 2, characterized in that: The surface potential distribution function ψ at the interface between the channel and the gate insulating layer in step 2-4 R (y) is: in, C3 and C4 are constants.

6. The numerical simulation method of the short channel negative capacitance gate field effect transistor according to claim 5, characterized in that: Calculate C3 and C4 based on the boundary conditions near the source and drain regions, specifically including: Solve the boundary conditions near the source and drain regions at the interface between the channel and the gate insulator: ψ R (0)=V bi ψ R (L)=V bi +V ds Among them, ψ R (0) represents the value of the potential function at the interface between the channel and the gate insulating layer at r = 0, ψ R (L) represents the value of the potential function at the interface between the channel and the gate insulating layer at r = L, r is the radial direction of the channel, L represents the length of the source and drain regions at the interface between the channel and the gate insulating layer, V bi Represents the built-in potential between the channel and the source and drain regions, V ds is the source-drain voltage; Then the constants C3 and C4 are obtained as: Here, Sinh represents the hyperbolic sine function.

7. The numerical simulation method of the short channel negative capacitance gate field effect transistor according to claim 1, characterized in that: The source-drain current I in step 3 ds And the drain-induced barrier lowering effect parameter DIBL is: Among them, k B is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, V ds is the drain-source voltage, u is the electron mobility, n i is the intrinsic carrier concentration in silicon.

8. The numerical simulation method of the short channel negative capacitance gate field effect transistor according to claim 1, characterized in that: The subthreshold swing of NC-GAAFET calculated in step 5 is: Where SS0 represents the subthreshold swing of GAA-FET.

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