Synchronous circuit device

Abstract

The present invention provides a synchronization circuit device and a method for generating a synchronization signal. The synchronization circuit device includes: a carrier frequency offset blind estimation circuit, which is configured to receive a multi-bit frequency domain data stream and a synchronization signal fed back from an address synchronization circuit, and output a first carrier frequency offset estimation value; a carrier frequency offset compensation circuit, which is configured to perform carrier frequency offset compensation on the received multi-bit frequency domain data stream according to the first carrier frequency offset estimation value, and output a frequency domain data stream without carrier frequency offset as a single bit; and an address synchronization circuit, which is configured to receive the frequency domain data stream without carrier frequency offset as a single bit, and output a synchronization signal.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and more particularly to a synchronization circuit device and method for executing a synchronization signal generation method in a coded physical layer (coded PHY) mode in a Bluetooth low energy (BLE) device. Background Art

[0002] Physical layer synchronization of Bluetooth data packets plays a crucial role in receiver circuits, ensuring efficient and stable transmission of the transceiver system. However, in real-world Bluetooth product applications, because the system's transceiver and receiver devices utilize different clock sources, the receiver circuitry, including the synchronization and symbol detection circuits, must be able to tolerate significant carrier frequency deviation. Therefore, reducing the crystal accuracy requirements of Bluetooth transceiver devices can effectively reduce the cost of Bluetooth transceiver systems and the difficulty of debugging the equipment. Summary of the Invention

[0003] One aspect of the present invention provides a synchronization circuit device, comprising: a carrier frequency offset blind estimation circuit, configured to receive a multi-bit frequency domain data stream and a synchronization signal fed back from an address synchronization circuit, and output a first carrier frequency offset estimation value; a carrier frequency offset compensation circuit, configured to perform carrier frequency offset compensation on the received multi-bit frequency domain data stream according to the first carrier frequency offset estimation value, and output a frequency domain data stream without carrier frequency offset as a single bit; and an address synchronization circuit, configured to receive a frequency domain data stream without carrier frequency offset as a single bit, and output a synchronization signal.

[0004] According to another aspect of the present invention, a synchronization circuit device is provided, wherein the first carrier frequency offset estimation value is a carrier frequency offset value obtained by blind estimation of 64 symbols.

[0005] According to another aspect of the present invention, a synchronization circuit device is provided, wherein the carrier frequency offset blind estimation circuit is further configured to output a second carrier frequency offset estimation value, which is an accurate carrier frequency offset estimation value obtained from 256 symbols when the synchronization signal is pulled up.

[0006] According to another aspect of the present invention, a synchronization circuit device is provided, wherein the address synchronization circuit is configured to perform a cross-correlation operation on a received single-bit frequency domain data stream and a local address sequence, and output a high-level synchronization signal when a cross-correlation peak value exceeding a threshold is obtained.

[0007] According to another aspect of the present invention, a synchronization circuit device is provided, wherein the carrier frequency offset blind estimation circuit includes a first mean calculation unit, a first storage circuit, a second mean calculation unit, a second storage circuit and a third mean calculation unit, wherein the first mean calculation unit is configured to perform an arithmetic mean calculation on an input data stream of each first plurality of symbols; wherein the first storage circuit is configured to store the mean result of the first plurality of symbols; wherein the second mean calculation unit is configured to receive data from the first storage circuit, and perform an arithmetic mean calculation on the input data stream of each second plurality of symbols, and provide the result of the arithmetic mean calculation performed on the input data stream of each second plurality of symbols as a first carrier frequency offset estimation value; wherein the second storage circuit is configured to store the mean result of the second plurality of symbols; and wherein the third mean calculation unit is configured to receive data from the second storage circuit, and perform an arithmetic mean calculation on the input data stream of each third plurality of symbols, and provide the result of the arithmetic mean calculation performed on the input data stream of each third plurality of symbols as a second carrier frequency offset estimation value when a synchronization signal is determined.

[0008] According to another aspect of the present invention, a synchronous circuit device is provided, wherein the first plurality of symbols is 16 symbols; the second plurality of symbols is 64 symbols; and the third plurality of symbols is 256 symbols.

[0009] According to another aspect of the present invention, a synchronous circuit device is provided, wherein the first storage circuit includes 4 groups of serial storage cells, and the second storage circuit includes 4 groups of serial storage cells, and wherein the storage cells include random access storage cells, FIFOs or shift registers.

[0010] According to another aspect of the present invention, a synchronization circuit device is provided, wherein the carrier frequency offset compensation circuit includes an adder and a sign bit inverter, wherein the adder is configured to subtract a first carrier frequency offset estimate value from a received multi-bit frequency domain data stream, and wherein the sign bit inverter is configured to take the sign bit of the output result of the adder and invert it to generate a single-bit frequency domain data stream without carrier frequency offset.

[0011] According to another aspect of the present invention, a synchronization circuit device is provided, wherein the address synchronization circuit is configured to receive single-bit frequency domain data and to perform a correlation operation using a fourth plurality of input sampling point data and a local address sequence to generate the synchronization signal based on a correlation peak. Preferably, the address synchronization circuit performs the correlation operation using 256×R input sampling point data and the local address sequence, where R is the oversampling ratio of the signal.

[0012] According to another aspect of the present invention, a method for generating a synchronization signal is provided, comprising: demodulating a time domain signal to obtain a multi-bit frequency domain signal; performing blind carrier frequency offset estimation and outputting a first carrier frequency offset estimation value; performing carrier frequency offset compensation to generate a single-bit frequency domain signal; performing a cross-correlation operation on the single-bit frequency domain signal and a local address sequence to generate a synchronization signal; and determining whether a synchronization signal is generated, and if so, outputting a second carrier frequency offset estimation value. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 and Figure 2 The Bluetooth data packet structure in the uncoded mode and the coded mode is shown respectively;

[0014] Figure 3 is a schematic diagram illustrating a method for synchronizing Bluetooth data packets in coding mode;

[0015] Figure 4 is a schematic diagram showing another method of synchronizing Bluetooth data packets in coding mode;

[0016] Figure 5 is a schematic diagram of carrier frequency deviation in the frequency domain;

[0017] Figure 6 is a schematic diagram of a synchronous circuit device according to an embodiment of the present invention;

[0018] Figure 7 is a flow chart illustrating a signal synchronization method according to an embodiment of the present invention;

[0019] Figure 8 is a schematic diagram of a carrier frequency offset blind estimation circuit in a synchronization circuit device according to an embodiment of the present invention;

[0020] Figure 9 is a schematic diagram of a carrier frequency offset compensation circuit of a synchronization circuit device according to an embodiment of the present invention; and

[0021] Figure 10 is a schematic diagram showing a process of determining whether synchronization of a current data packet is correct. DETAILED DESCRIPTION

[0022] Before proceeding with the detailed description below, it may be helpful to set forth the definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate with, intertwine, juxtapose, approach, bound or bound with, have, have an attribute of, have a relationship with, or have a relationship with, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0023] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0024] In this patent document, the application combination of modules and the division level of sub-modules are only used for illustration. Without departing from the scope of this disclosure, the application combination of modules and the division level of sub-modules can have different forms.

[0025] Bluetooth low energy technology uses Gaussian-Frequency-Shift-Keying (GFSK) modulation. Bluetooth low energy protocols 5.0 and above have four data rate modes: 1mbps and 2mbps in uncoded mode, and 125kbps and 500kbps in coded mode.

[0026] Figure 1 and Figure 2 The Bluetooth data packet structures in the non-coding mode and the coding mode are shown respectively.

[0027] like Figure 2As shown in the figure, when the Bluetooth system operates in coded mode, a data packet includes a preamble, synchronization address, payload, and other data fields such as a CRC. Data packet synchronization relies entirely on the preamble and synchronization address. In coded mode, the preamble is 80 symbols long and consists of 10 repeating sequences of '00111100'; the synchronization address is 256 symbols long and consists of 64 sequences of '0011' or '1100'.

[0028] In the coding mode, there are two main existing Bluetooth data packet synchronization methods. Figure 3 FIG. 1 is a schematic diagram illustrating a method for synchronizing Bluetooth data packets in coding mode.

[0029] See also Figure 3 The method includes the following steps: step S301, demodulating the time domain signal to obtain a frequency domain signal; step S302, detecting the preamble code sequence signal in the frequency domain; step S303, averaging the preamble code to obtain a carrier frequency offset estimate, for example, using the equalization characteristic of the Bluetooth preamble code '0' and '1' to obtain the estimated value of the carrier frequency offset; step S304, using the estimated value of the carrier frequency offset to compensate the synchronization sequence for the carrier frequency offset; step S305, correlating the compensated synchronization sequence to obtain a final frame synchronization signal; and step S306, completing the synchronization circuit operation.

[0030] Figure 4 FIG. 4 is a schematic diagram illustrating another method for synchronizing Bluetooth data packets in coding mode.

[0031] See also Figure 4 The method includes the following steps: Step S401, demodulating the time domain signal to obtain a frequency domain signal; Step S402, jointly detecting the carrier frequency offset and the synchronization signal based on a certain criterion; and Step S403, completing the synchronization circuit operation. This method primarily relies on certain criteria, such as the maximum likelihood criterion or the minimum mean square error criterion, to directly perform correlation operations on the frequency domain signal and a locally known address sequence. This method directly utilizes the synchronization sequence without the need for a preamble, demonstrating considerable technological advancement.

[0032] refer to Figure 3The synchronization method has a simple and clear operation process, and it is also suitable for data reception in the uncoded mode of Bluetooth low-power devices. However, in the coded working mode, this method has two major disadvantages: 1) The detection of the preamble code generally uses a cross-correlation operation, which will add a circuit module equivalent to the synchronization circuit. The circuit is more complex, and the hardware cost of the storage unit and the circuit power consumption are both high; 2) In the coded mode, the preamble code of the Bluetooth data packet has only 80 symbols. Under low signal-to-noise ratio conditions, the detection success rate is not high, which in turn affects the subsequent operation process of the physical layer, resulting in low sensitivity of the Bluetooth device in the coded mode. In addition, in the carrier frequency offset estimation stage, the input data needs to be a multi-bit stream, and in the synchronization sequence stage, the compensated data stream can be a single-bit stream.

[0033] refer to Figure 4 The synchronization method generally requires that the input data stream is a multi-bit stream. Assuming that the signal oversampling rate is R and the bit stream width is W, the number of storage cells for synchronous cross-correlation operations is 256*R*W. Because the cross-correlation operation requires all data and the local sequence to be cross-correlated at each sampling point, all data in the storage cell needs to be read at each calculation moment. Even if the amount of read data can be reduced to 1 / R through certain iterative operations, the storage cells that meet the design requirements are usually designed to have a narrow and long structure. Such a structure is not conducive to EDA tool synthesis, resulting in a larger hardware area and relatively high power consumption.

[0034] Aiming at the Bluetooth coded physical layer mode, the present invention designs a synchronization circuit with a relatively simple process, better circuit area and power consumption, and at the same time ensuring higher sensitivity performance of the receiver.

[0035] The present invention primarily leverages the balanced '0' and '1' symbols in the preamble and address sequences of the Bluetooth system in coded mode. It employs a blind estimation algorithm to estimate carrier frequency offset, updating the estimated value at a fixed frequency every 64 symbols. This compensates for the carrier frequency offset in the address sequence in real time, ultimately yielding a single-bit address data stream unaffected by carrier frequency offset, significantly simplifying the cross-correlation operation of the synchronization circuit. Furthermore, the present synchronization method simultaneously generates a more accurate carrier frequency offset derived from the average of 256 symbols, providing accurate carrier frequency offset compensation for subsequent payloads.

[0036] Figure 5 This is a diagram of carrier frequency deviation in the frequency domain. Figure 5The carrier frequency offset causes the overall frequency domain data to shift positively or negatively, with the offset being a function of the carrier frequency offset. Therefore, the system carrier frequency offset can be determined from the offset in the frequency domain data. If the frequency domain data is balanced between positive and negative (i.e., '0' and '1'), the carrier frequency offset can be obtained by taking the average of the frequency domain data.

[0037] Figure 6 is a schematic diagram of a synchronous circuit device according to an embodiment of the present invention.

[0038] refer to Figure 6 , a synchronization circuit device according to an embodiment of the present invention includes: a carrier frequency offset blind estimation circuit, a carrier frequency offset compensation circuit and an address synchronization circuit. The carrier frequency offset blind estimation circuit is configured to receive a multi-bit frequency domain data stream and a synchronization signal fed back from the address synchronization circuit; and output a carrier frequency offset estimation value 1 and a carrier frequency offset estimation value 2, wherein the carrier frequency offset estimation value 1 is a carrier frequency offset value obtained by blind estimation of 64 symbols, which is used for the synchronization circuit to perform carrier frequency offset compensation, and the carrier frequency offset estimation value 2 is an accurate carrier frequency offset estimation value obtained by 256 symbols when the synchronization signal is pulled up (determined). The accurate carrier frequency offset estimation value is output to other circuits of the system to improve the performance of other circuits. The carrier frequency offset compensation circuit is configured to perform carrier frequency offset compensation on the received multi-bit frequency domain data stream according to the carrier frequency offset estimation value 1, and output a frequency domain data stream as a single bit without carrier frequency offset. The address synchronization circuit is configured to receive a single-bit frequency domain data stream without carrier frequency deviation, perform a cross-correlation operation on the single-bit frequency domain data stream and a local address sequence, and output a high-level synchronization signal after obtaining a cross-correlation peak value exceeding a threshold; the high-level synchronization signal is output to other circuit modules of the receiver, and at the same time, it is also fed back to the carrier frequency deviation blind estimation circuit.

[0039] Figure 7 is a flow chart illustrating a signal synchronization method according to an embodiment of the present invention.

[0040] refer to Figure 7 In step S701, the time domain signal is demodulated to obtain a multi-bit frequency domain signal; in step S702, blind carrier frequency offset estimation is performed; in step S703, a carrier frequency offset estimation value 1 is output; in step S704, carrier frequency offset compensation is performed to generate a single-bit frequency domain signal; in step S705, the single-bit frequency domain signal is cross-correlated with a local address sequence (synchronization sequence) to generate an address synchronization signal; in step S706, it is determined whether the synchronization signal is generated. If so, the carrier frequency offset estimation value 2 is output in step S708. If not, the process waits in step S707; in step S709, after the carrier frequency offset estimation value 2 is output, the synchronization circuit operation is completed.

[0041] Figure 84 is a schematic diagram of a carrier frequency offset blind estimation circuit in a synchronization circuit device according to an embodiment of the present invention.

[0042] refer to Figure 8 The carrier frequency deviation blind estimation circuit is configured to receive a frequency domain data stream with a multi-bit width. The multi-bit frequency domain data stream first enters the mean calculation unit 801, which calculates the arithmetic mean for every 16 symbols of the input data stream. Assuming that the oversampling rate of the circuit operation is R, the arithmetic mean calculation is performed once for every 16×R data. After the receiver physical layer is powered on, the synchronization circuit device of the present invention can begin operation. There are no special requirements for the starting operating point, and no need to detect the preamble code.

[0043] Storage circuit 811 stores the 16-symbol mean result and consists of four serially connected storage units 11-14. For every 16 symbols, a new 16-symbol mean result is stored in the storage unit, while the oldest 16-symbol mean result is removed. The storage units of storage circuit 811 can be implemented using, but are not limited to, random access memory cells, FIFOs, or shift registers.

[0044] Mean calculation unit 802 calculates the 64-symbol mean value. This unit calculates the arithmetic mean of the four stored values ​​in circuit 1 to obtain the 64-symbol mean value. This mean value is carrier frequency offset estimate 1. Carrier frequency offset estimate 1 is used for carrier frequency offset compensation in the synchronization circuit.

[0045] Storage circuit 812 stores the '64-symbol average' and consists of four serially connected storage units 21-24. For every 64 symbols, a new '64-symbol average' is stored in the storage unit, while the oldest '64-symbol average' is removed. The storage units of storage circuit 812 can be implemented, but are not limited to, using structures such as random access memory cells, FIFOs, or shift registers.

[0046] Mean calculation unit 803 calculates the mean value for 256 symbols. It calculates the arithmetic mean of the four stored values ​​in storage circuit 812 to obtain the 256-symbol mean value. When the synchronization signal is asserted, this mean value is output as carrier frequency offset estimate 2. Carrier frequency offset estimate 2 is used to compensate for carrier frequency offset in the data packet payload.

[0047] The key to simplifying address synchronization circuit design lies in accurately estimating carrier frequency offset and converting a multi-bit data stream into a single-bit data stream by compensating for the carrier frequency offset. This significantly reduces the address synchronization circuit's circuit area (including the combinational logic for the cross-correlation operation and the data storage unit) and power consumption. It also provides other circuits with a highly accurate carrier frequency offset estimate of the 256-symbol mean, ensuring optimal Bluetooth system reception performance.

[0048] In Bluetooth encoding mode, the preamble consists of an 80-symbol repeating sequence of '00111100'—that is, 10 of these repeating sequences, one after the other. The synchronization address is 256 symbols, consisting of 64 '0011's or '1100's. The number and position of the '0011' and '1100' sequences depend on the specific value of the 32-bit address before encoding and the convolutional encoding circuit: The 32-bit original address sequence passes through the convolutional encoding circuit, outputting a 64-bit address sequence. This is then mapped to '0011's and '1100's to form the final 256 address sequences. Simplifying the input of the address synchronization circuit from multiple bits to a single bit requires a relatively accurate estimation of the carrier frequency offset during the preamble. The total length of the preamble in the coded mode is 80 symbols. According to an embodiment of the present invention, a blind estimation is performed by taking an arithmetic average of every 16 symbols, eliminating the preamble detection circuit and greatly simplifying the circuit. At the same time, the detection effect of the 80-symbol preamble detection under extremely low signal-to-noise ratios is very unsatisfactory. Firstly, the cross-correlation operation of the periodically repeated preamble will produce multiple cross-correlation peaks, making it difficult to determine the position of the highest peak. Secondly, under extremely low signal-to-noise ratios, a preamble with only 80 symbols is easily missed. To achieve a more ideal effect, a length equivalent to that of the address sequence should be used, that is, approximately 256 symbols should be required to obtain a more accurate synchronization detection result. The carrier frequency offset blind estimation algorithm based on the symbol sequence mean of the present invention can meet the accuracy requirements of the synchronization circuit and other circuits for the carrier frequency offset estimation value under low signal-to-noise ratios, thereby enabling the receiver to achieve more ideal performance.

[0049] In the address synchronization circuit, when the address is matched and the frame synchronization signal is raised (determined), 336 symbols have been input into the data packet. Therefore, according to the embodiment of the present invention, 256 symbols, or four complete '64-symbol average results', can be obtained. Therefore, the present invention can obtain a more accurate carrier frequency offset estimate for use in other receiver circuits.

[0050] Regarding the accuracy of the carrier frequency offset estimate of 1, every 16 symbols in the preamble are perfectly balanced between 0s and 1s, resulting in 8 0s and 8 1s. Therefore, ignoring the effects of electrical noise, the carrier frequency offset estimate of 1 in the preamble is perfectly equal to the carrier frequency offset, with no deviation. In the 256-symbol address sequence, because the first 32 symbols are unbalanced, the positions of the 0011 and 1100 sequences are not fixed. Therefore, under worst-case conditions, the blind estimation algorithm will fail to balance out 4 0s or 1s in every 64 symbols. Therefore, the 64-symbol average result will have a minimum normalized carrier frequency offset deviation of 1 / 16. For Bluetooth coded mode with a maximum modulation frequency deviation of 250 kHz, a maximum carrier frequency offset of 15.625 kHz can occur. This deviation is tolerable in the address synchronization circuit and has a minimal impact on performance.

[0051] Regarding the accuracy of the carrier frequency offset estimate 2, as previously mentioned, when averaging every 256 symbols, there is a maximum of four '0' or '1' symbols that cannot be equalized. This results in a normalized carrier frequency offset of 1 / 64, or 3.90625 kHz. However, this magnitude of carrier frequency offset has a very limited impact on subsequent payload reception.

[0052] Figure 9 Schematic diagram of a carrier frequency offset compensation circuit of a synchronization circuit device according to an embodiment of the present invention. Figure 9 , subtract the carrier frequency offset estimate 1 from the multi-bit frequency domain data stream, take the sign bit of the result and invert it (that is, if the result is a negative number, output '0', otherwise, output '1'), and then obtain a single-bit frequency domain data stream, which is provided to the address synchronization circuit.

[0053] The address synchronization circuit is configured to receive single-bit frequency-domain data. It performs a cross-correlation operation between 256 × R input sampling points and the local address sequence. Because the data stream is a single bit, 256 × R shift registers can be used to store the input data. When the cross-correlation value reaches the set cross-correlation threshold, the maximum value is found among the subsequent sampling points. That is, the peak of the cross-correlation peak is found, which serves as the time when the frame synchronization signal is determined. When the frame synchronization signal is determined, the blind carrier frequency offset estimation circuit outputs a carrier frequency offset estimate of 2.

[0054] According to an embodiment of the present invention, after completing the above-mentioned synchronization circuit device operation, a process may further be included to determine whether the synchronization of the current data packet is correct. The specific method process includes: performing a demapping operation on the 256 address symbols of '0011' and '1100', and then using the Viterbi algorithm to decode the convolution code to finally obtain a 32-bit original address sequence. If it completely corresponds to the locally known address sequence, the synchronization of the data packet is considered to be completed. Otherwise, the physical layer is reset and the data packet synchronization process is re-entered.

[0055] Figure 10 is a schematic diagram showing a process of determining whether synchronization of a current data packet is correct.

[0056] refer to Figure 10 In step S1001, 256 bits of address data are obtained; in step S1002, a demapping operation is performed on the 256 bits of address data; in step S1003, deconvolution coding is performed on the demapping result; and in step S1004, the 32-bit address sequence obtained by deconvolution coding is compared with the local address sequence. When they completely correspond, the synchronization of the data packet is considered to be completed.

[0057] The signal synchronization method and circuit according to the embodiment of the present invention are relative to the reference Figure 3 The synchronization method has the following advantages: 1) Blind estimation of carrier frequency offset replaces preamble detection and carrier frequency offset estimation, saving a preamble synchronization circuit; 2) Since preamble synchronization is not required, the performance of the entire Bluetooth receiver system is not limited by the performance of the preamble synchronization circuit. In the existing technology, the preamble length is much shorter than the synchronization address length, so the performance of its detection circuit is much lower than the address synchronization circuit. Therefore, the reference Figure 3 The synchronization method cannot work normally under the receiver demodulation threshold, which has a great impact on system performance. The signal synchronization method according to the embodiment of the present invention adopts a technical solution of blind estimation of long sequences to overcome the above difficulties, so that the receiver can achieve higher sensitivity.

[0058] Compared to reference Figure 4 According to the signal synchronization method of the embodiment of the present invention, when performing address synchronization operation, the operand is single-bit data, and Figure 4 Because the synchronization method does not estimate and correct the carrier frequency offset of the input data, it must use multi-bit data, which is generally about 8 bits. To perform related operations on multi-bit data and local address sequences, a relatively large RAM must be used to temporarily store these multi-bit data. The single-bit stream signal synchronization method according to the present invention can reduce the data volume to about 1 / 8, significantly reducing the size of the storage RAM, saving circuit area and power consumption; in addition, Figure 4The synchronization method performs cross-correlation operation with the carrier frequency offset, which will also increase the number of related circuits for carrier frequency offset estimation and compensation, and its control is complex and the circuit cost is also high.

[0059] In summary, the synchronization circuit in Bluetooth coded mode based on blind estimation of carrier frequency deviation proposed by the concept of the present invention fully utilizes the specific data characteristics of the Bluetooth receiver in this mode, and has relatively large advantages in terms of control complexity, circuit area cost, and system power consumption. Therefore, it effectively solves the physical layer synchronization problem of Bluetooth low energy system in coded mode and has very great practical value.

[0060] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0061] Any description in the present invention should not be construed as implying that any particular element, step, or function is essential to be included in the scope of the claims. The scope of the patented subject matter is defined solely by the claims.

Claims

1. A synchronous circuit device, comprising: a carrier frequency offset blind estimation circuit, configured to receive a multi-bit frequency domain data stream and a synchronization signal fed back from an address synchronization circuit, and output a first carrier frequency offset estimation value; a carrier frequency offset compensation circuit configured to perform carrier frequency offset compensation on a received multi-bit frequency domain data stream according to a first carrier frequency offset estimation value, and output a single-bit frequency domain data stream without carrier frequency offset; as well as an address synchronization circuit configured to receive a frequency domain data stream as a single bit without carrier frequency deviation and output a synchronization signal, The address synchronization circuit is configured to perform a cross-correlation operation on the received single-bit frequency domain data stream and the local address sequence, and output a high-level synchronization signal when a cross-correlation peak value exceeding a threshold is obtained.

2. The synchronous circuit device according to claim 1, wherein: The first carrier frequency offset estimation value is a carrier frequency offset value obtained by blind estimation of 64 symbols.

3. The synchronous circuit device according to claim 1, wherein: The carrier frequency offset blind estimation circuit is further configured to output a second carrier frequency offset estimation value, where the second carrier frequency offset estimation value is an accurate carrier frequency offset estimation value obtained from 256 symbols when the synchronization signal is pulled up.

4. The synchronous circuit device according to claim 1, wherein: The carrier frequency deviation blind estimation circuit includes a first mean value calculation unit, a first storage circuit, a second mean value calculation unit, a second storage circuit and a third mean value calculation unit. wherein the first mean value calculation unit is configured to perform an arithmetic mean value calculation on each input data stream of the first plurality of symbols; The first storage circuit is configured to store the average result of the first plurality of symbols; The second mean value calculation unit is configured to receive data from the first storage circuit, perform an arithmetic mean value calculation on each second plurality of symbols of the input data stream, and provide a result of the arithmetic mean value calculation performed on each second plurality of symbols of the input data stream as a first carrier frequency offset estimate; The second storage circuit is configured to store the average result of the second plurality of symbols; and In which, the third mean calculation unit is configured to receive data from the second storage circuit and perform an arithmetic mean calculation on the input data stream of each third plurality of symbols, and when the synchronization signal is determined, the result of the arithmetic mean calculation performed on the input data stream of each third plurality of symbols is provided as a second carrier frequency offset estimation value.

5. The synchronous circuit device according to claim 4, wherein: The first plurality of symbols is 16 symbols; the second plurality of symbols is 64 symbols and the third plurality of symbols is 256 symbols.

6. The synchronous circuit device according to claim 4, wherein: The first storage circuit includes four groups of memory cells in series, and the second storage circuit includes four groups of memory cells in series, and Wherein, the storage unit includes a random access storage unit, a FIFO or a shift register.

7. The synchronous circuit device according to claim 1, wherein: The carrier frequency offset compensation circuit includes an adder and a sign bit inverter. The adder is configured to subtract the first carrier frequency offset estimate from the received multi-bit frequency domain data stream, and The sign bit inverter is configured to take the sign bit of the output result of the adder and invert it to generate a single-bit frequency domain data stream without carrier frequency offset.

8. The synchronous circuit device according to claim 1, wherein: The address synchronization circuit is configured to receive single-bit frequency domain data and to perform a correlation operation using a fourth plurality of input sampling point data and a local address sequence to generate the synchronization signal according to a correlation peak.

9. A method for generating a synchronization signal, comprising: The demodulation device demodulates the time domain signal to obtain a multi-bit frequency domain signal; The carrier frequency offset blind estimation circuit performs carrier frequency offset blind estimation and outputs a first carrier frequency offset estimation value; The carrier frequency offset compensation circuit performs carrier frequency offset compensation to generate a single-bit frequency domain signal; The address synchronization circuit performs a cross-correlation operation on the single-bit frequency domain signal and the local address sequence to generate a synchronization signal; as well as The carrier frequency offset blind estimation circuit determines whether the synchronization signal is generated, and if generated, outputs a second carrier frequency offset estimation value.

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