Goa circuit and display panel

Abstract

The application discloses a GOA circuit and a display panel. The GOA circuit comprises a plurality of cascaded GOA units. An nth-stage GOA unit comprises a pull-up module, a pull-down module, a pull-down maintenance module and an inverter. The pull-up module is connected with a first high power supply. An output end of the pull-down module is connected with a first low power supply. First and second input ends of the pull-down maintenance module are connected with a second high power supply and a first clock signal respectively. First to third input ends of the inverter are connected with the first clock signal, a second clock signal and a second low power supply respectively. The first clock signal and the second clock signal are in opposite phase. The second high power supply is greater than the first high power supply. The second low power supply is less than the first low power supply. The application is conducive to realizing a narrow-frame or frameless design, and high stability of signal output is realized through the design of double VGH and double VGL.

Description

Technical Field

[0001] This application relates to the field of display panel driving technology, specifically to a GOA circuit and a display panel. Background Technology

[0002] Gate Driver On Array (GOA) is a method of driving the gate row scan on the array substrate by using existing thin-film transistor display array manufacturing processes.

[0003] To ensure proper display, existing GOA circuits often incorporate anti-drift units, requiring a relatively large number of TFTs (Thin Film Transistors) and CKs, resulting in a wider border for the display panel. If the GOA circuit lacks anti-drift units, although the number of TFTs and CKs is lower and the border narrower, the requirements for components are higher. The Vth value must be positively drifted throughout its lifespan, leading to poor stability and impacting product lifespan.

[0004] With people's increasing visual demand for narrower bezels on displays, how to reduce the bezel space occupied by GOA circuits, so that display panels can achieve narrower or bezel-less designs, while ensuring stable signal output is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a GOA circuit that can reduce the frame space occupied by the GOA circuit while ensuring stable signal output.

[0006] This application provides a GOA circuit, including multiple cascaded GOA units, wherein the nth GOA unit includes: The pull-up module has its input terminal connected to a first high voltage terminal to receive a first high power supply; its output terminal connected to the nth scan line to output the nth scan signal; and its control terminal connected to a first node. A pull-down module, the output of which is connected to the output of the pull-up module, and the control terminal of which is connected to the second node; the input terminal of which is connected to a first low voltage terminal to receive a first low power supply, the first low power supply being less than the first high power supply. A pull-down sustaining module, wherein the output terminal of the pull-down sustaining module is connected to a first node, the input terminal of the pull-down sustaining module is connected to a second high voltage terminal to receive a second high power supply, and the control terminal of the pull-down sustaining module is connected to a first clock signal terminal to receive a first clock signal connection, wherein the second high power supply is greater than the first high power supply; An inverter is provided, wherein its first control terminal is connected to the first clock signal terminal to receive the first clock signal; its second control terminal is connected to the second clock signal terminal to receive the second clock signal, which is inverted compared to the first clock signal; its first input terminal is grounded to receive a first common voltage; its second input terminal is connected to a second low voltage terminal to receive a second low power supply, which is lower than the first low power supply; and its third control terminal and output terminal are respectively connected to the first node and the second node to control the potential of the second node. Wherein, the high level of the first clock signal and the second clock signal is greater than the second high power supply, and the low level of the first clock signal and the second clock signal is less than the second low power supply.

[0007] Secondly, this application also provides a display panel including the GOA circuit as described in the first aspect.

[0008] The GOA circuit provided in this application embodiment comprises multiple cascaded GOA units. The nth-level GOA unit includes a pull-up module, a pull-down module, a pull-down sustaining module, and an inverter. The input terminal of the pull-up module is connected to a first high power supply, and the output terminal of the pull-down module is connected to a first low power supply. The first and second input terminals of the pull-down sustaining module are respectively connected to a second high power supply and a first clock signal. The first to third input terminals of the inverter are respectively connected to a first clock signal, a second clock signal, and a second low power supply. The first clock signal and the second clock signal are inverted. The second high power supply is greater than the first high power supply, and the second low power supply is less than the first low power supply. The high level of the first clock signal and the second clock signal is greater than the second high power supply, and the low level of the first clock signal and the second clock signal is less than the second low power supply. This application utilizes the voltage difference between the first and second high power supplies and the voltage difference between the first and second low power supplies to better shut down the transistors in the GOA unit, eliminating the need for an anti-drift unit and reducing the number of TFTs, thus facilitating the implementation of narrow bezel or bezel-less designs. Furthermore, the design of dual low power supplies VGL and dual high power supplies VGH achieves high signal stability output. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the cascaded connection of multi-level GOA units in the GOA circuit provided in the embodiments of this application; Figure 2 This is a circuit diagram of any level GOA unit of the GOA circuit provided in the embodiments of this application; Figure 3 This is a timing diagram provided in an embodiment of this application; Figure 4 This is a circuit diagram of the second-stage GOA unit G2 of the GOA circuit provided in the embodiments of this application; Figure 5 This is a schematic diagram of the transistor being turned on or off during t1 in the second-stage GOA unit G2 of the GOA circuit provided in this application embodiment; Figure 6 This is a schematic diagram of the transistor being turned on or off during t2 in the second-stage GOA unit G2 of the GOA circuit provided in this application embodiment; Figure 7 This is a schematic diagram of the transistor being turned on or off during t3 in the second-stage GOA unit G2 of the GOA circuit provided in this application embodiment; Figure 8 This is a circuit diagram of the third-level GOA unit of the GOA circuit provided in the embodiments of this application; Figure 9 This is a circuit diagram of the fourth-level GOA unit of the GOA circuit provided in the embodiments of this application; Figure 10 This is a circuit diagram of the fifth-level GOA unit of the GOA circuit provided in the embodiments of this application. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0012] In the description of this application, it should be understood that the terms "one end," "the other end," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0013] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a link, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0014] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In the above embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0015] The display panel in this application embodiment can be used in mobile phones, tablets, desktop computers, laptops, e-readers, handheld computers, electronic display screens, laptops, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0016] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0017] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the cascaded connection of multi-level GOA units in the GOA circuit provided in the embodiments of this application. Figure 2 This is a circuit diagram of any level of the GOA unit in the GOA circuit provided in the embodiments of this application. For example... Figure 1 and Figure 2As shown, the GOA circuit includes multiple cascaded GOA units, and the nth-level GOA unit includes: Pull-up module 10, the input terminal of the pull-up module 10 is connected to the first high voltage terminal to receive the first high power supply VGH1; the output terminal of the pull-up module 10 is connected to the nth scan line to output the nth scan signal Gn[n]; the control terminal of the pull-up module 10 is connected to the first node Q; A pull-down module 30 is provided, the output of which is connected to the output of the pull-up module 10, and the control terminal of the pull-down module 30 is connected to the second node Qb. The input terminal of the pull-down module 30 is connected to the first low voltage terminal to receive the first low power supply VGL1, which is less than the first high power supply VGH1. A pull-down sustaining module 40 is provided, the output of which is connected to the first node Q, and the input of which is connected to the second high voltage terminal to receive the second high power supply VGH2. The control terminal of the pull-down sustaining module 40 is connected to the first clock signal terminal to receive the first clock signal CK1. The second high power supply VGH2 is greater than the first high power supply VGH1. An inverter 60 is provided, wherein its first control terminal is connected to the first clock signal terminal to receive the first clock signal CK1; its second control terminal is connected to the second clock signal terminal to receive the second clock signal XCK1, which is inverted from the first clock signal CK1; its first input terminal is connected to the first common terminal; its second input terminal is connected to the second low voltage terminal to receive the second low power supply VGL2, which is less than the first low power supply VGL1; its third control terminal is connected to the first node Q; and its output terminal is connected to the second node Qb to control the potential of the second node Qb. Wherein, the high level of the first clock signal CK1 and the second clock signal XCK1 is greater than the second high power supply VGH2, and the low level of the first clock signal CK1 and the second clock signal XCK1 is less than the second low power supply VGL2.

[0018] Specifically, in the GOA circuit, for the first-stage GOA unit, there is no scanning signal Gn[0] from the previous stage. Therefore, in the first-stage GOA unit, the start signal STV can be set to replace the scanning signal Gn[0] from the previous stage, which will not be described in detail here. Similarly, the scanning signal output by the last-stage GOA unit is not controlled by the next-stage GOA unit. It should be noted that, apart from the above differences, the circuit structure and signal connections of the remaining GOA units in multiple GOA units are the same except for the first-stage GOA unit, which will not be elaborated here.

[0019] Please see Figure 1 , Figure 1 Taking a cascaded GOA unit of level (n-1), level (n), and level (n+1) as an example. When the (n-1)th level GOA unit outputs a high-level scan signal Gn[n-1], it controls the operation of the level (n-1)th level GOA unit. When the level (n)th level GOA unit starts working, it controls the operation of the level (n+1)th level GOA unit when the output of the level (n)th level GOA unit is high. When the (n+1)th level GOA unit outputs a high-level scan signal Gn[n+1], it controls the operation of the level (n+2)th level GOA unit.

[0020] In this application, the GOA circuit includes multiple cascaded GOA units. The nth GOA unit includes a pull-up module 10, a pull-down module 30, a pull-down sustaining module 40, and an inverter 60. The input of the pull-up module 10 is connected to the first high power supply VGH1, and the output of the pull-down module 30 is connected to the first low power supply VGL1. The first and second inputs of the pull-down sustaining module 40 are connected to the second high power supply VGH2 and the first clock signal CK1, respectively. The first to third inputs of the inverter 60 are connected to the first clock signal CK1, the second clock signal XCK1, and the second low power supply VGL2, respectively. The first clock signal CK1 and the second clock signal XCK1 are inverted. The second high power supply VGH2 is greater than the first high power supply VGH1, the second low power supply VGL2 is less than the first low power supply VGL1, and the first low power supply VGL1 is less than the first high power supply VGH1, i.e., the second low power supply VGL2 < the first low power supply VGL1 < the first high power supply VGH1 < the second high power supply VGH2. This application utilizes the voltage difference between two high power supplies (VGH1 and VGH2) and between two low power supplies (VGL1 and VGL2) to better shut down transistors in the GOA unit, preventing negative drift in the GOA unit. This eliminates the need for anti-drift units in the GOA circuit, reduces the number of transistors, ensures the functionality of the GOA circuit while reducing its complexity, and enables a narrow bezel design. This optimizes the GOA circuit architecture and improves yield. Furthermore, the design of two low power supplies (VGL) and two high power supplies (VGH) achieves highly stable signal output.

[0021] In some embodiments, the pull-up module 10 includes a first transistor T21 with a P-type channel, the source S of the first transistor T21 being the input terminal of the pull-up module 10, the gate of the first transistor T21 being the control terminal of the pull-up module 10, and the drain D of the first transistor T21 being the output terminal of the pull-up module 10.

[0022] Specifically, such as Figure 2 and Figure 4 As shown, the first transistor T21 is a PMOS transistor. The source S of the first transistor T21 receives the first high power supply VGH1. The drain D of the first transistor T21 is connected to the nth scan line and outputs the nth scan signal Gn[n]. The gate of the first transistor T21 is connected to the first node Q.

[0023] In some embodiments, the nth-level GOA unit further includes: Pull-up control module 20, the output terminal of the pull-up control module 20 is connected to the first node Q, the input terminal of the pull-up control module 20 is connected to the second common terminal to receive the second common voltage GND2, and the control terminal of the pull-up control module 20 is connected to the corresponding terminal of the previous level GOA unit.

[0024] Specifically, such as Figure 1 and Figure 2 As shown, the control terminal of the pull-up control module 20 of the nth level GOA unit is connected to the corresponding terminal of the previous level GOA unit, for example, as... Figure 1 As shown, the GOA unit above the nth level GOA unit is the (n-1)th level GOA unit. That is, the control terminal of the pull-up control module 20 of the nth level GOA unit is connected to the output terminal of the pull-up module of the (n-1)th level GOA unit, and the output terminal of the pull-up module of the (n-1)th level GOA unit is connected to the (n-1)th level scan line. Thus, the output terminal of the pull-up module of the (n-1)th level GOA unit outputs the (n-1)th level scan signal Gn[n-1] through the (n-1)th level scan line. The (n-1)th level scan signal Gn[n-1] generated by the (n-1)th level GOA unit is transmitted to the control terminal of the pull-up control module 20 of the nth level GOA unit, and the output terminal of the pull-up module of the nth level GOA unit outputs the nth level scan signal Gn[n] through the nth level scan line.

[0025] In some embodiments, the pull-up control module 20 includes: a second transistor T11 with an N-type channel; The drain D of the second transistor T11 is the output terminal of the pull-up control module 20, the source S of the second transistor T11 is the input terminal of the pull-up control module 20, and the gate of the second transistor T11 is the control terminal of the pull-up control module 20.

[0026] Specifically, such as Figure 2 and Figure 4 As shown, the second transistor T11 is an NMOS transistor. The drain D of the second transistor T11 is connected to the first node Q, and the source S of the second transistor T11 is connected to the second common terminal to access the second common voltage GND2. The gate of the second transistor T11 is connected to the corresponding terminal of the previous stage GOA unit. That is, the gate of the second transistor T11 of the nth stage GOA unit is connected to the drain D of the first transistor T21 of the (n-1)th stage GOA unit to access the (n-1)th stage scan signal Gn[n-1) output by the (n-1)th stage GOA unit.

[0027] In some embodiments, the pull-down sustaining module 40 includes: a third transistor T42 of P-type channel, a fourth transistor T43 of N-type channel, and a fifth transistor T45; The drain D of the fourth transistor T43 and the drain D of the fifth transistor T45 are both input terminals of the pull-down sustaining module 40; The gate of the fourth transistor T43 and the gate of the fifth transistor T45 are both control terminals of the pull-down sustaining module 40; The drain D of the third transistor T42 and the source S of the fifth transistor T45 are both output terminals of the pull-down sustaining module 40; The gate of the third transistor T42 is connected to the second node Qb, and the source S of the third transistor T42 is connected to the source S of the fourth transistor T43.

[0028] Specifically, such as Figure 2 and Figure 4 As shown, the third transistor T42 is a PMOS transistor, while the fourth transistor T43 and the fifth transistor T45 are both NMOS transistors. The drain D of the third transistor T42 is connected to the drain D of the second transistor T11 and the first node Q, respectively. The gate of the third transistor T42 is connected to the second node Qb, and the source S of the third transistor T42 is connected to the source S of the fourth transistor T43. The gates of both the fourth transistor T43 and the fifth transistor T45 are connected to the first clock signal terminal to receive the first clock signal CK1. The drain D of both the fourth transistor T43 and the fifth transistor T45 is connected to the second high voltage terminal to receive the second high power supply VGH2. The source S of the fifth transistor T45 is connected to the first node Q.

[0029] In some embodiments, the inverter 60 includes: a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, and a ninth transistor T41, all of which are of type N-channel. The gate of the sixth transistor T51 is the first control terminal of the inverter 60, and the drain D of the sixth transistor T51 is the first input terminal of the inverter 60. The gate of the eighth transistor T53 and the gate of the ninth transistor T41 are both the second control terminals of the inverter 60, and the source S of the eighth transistor T53 and the source S of the ninth transistor T41 are both the second input terminals of the inverter 60. The gate of the seventh transistor T52 is the third control terminal of the inverter 60. The source S of the sixth transistor T51, the drain D of the seventh transistor T52, and the drain D of the ninth transistor T41 are all output terminals of the inverter 60. The source S of the seventh transistor T52 is connected to the drain D of the eighth transistor T53.

[0030] Specifically, such as Figure 2 and Figure 4As shown, transistors T51, T52, T53, and T41 are all NMOS transistors. Specifically, the drain (D) of transistor T51 is connected to the first common terminal to receive the first common voltage, the source (S) of transistor T51 is connected to the second node Qb, and the gate of transistor T51 is connected to the first clock signal terminal to receive the first clock signal CK1. The gate of transistor T52 is connected to the first node Q, the drain (D) of transistor T52 is connected to the second node Qb, and the source (S) of transistor T52 is connected to the drain (D) of transistor T53. The sources (S) of transistors T53 and T41 are both connected to the second low voltage terminal to receive the second low power supply VGL2. The gates of transistors T53 and T41 are both connected to the second clock signal terminal to receive the second clock signal XCK1. The drain (D) of transistor T41 is connected to the second node Qb.

[0031] In some embodiments, the pull-down module 30 includes: a tenth transistor T31 with an N-type channel; The drain D of the tenth transistor T31 is the input terminal of the pull-down module 30, the gate of the tenth transistor T31 is the control terminal of the pull-down module 30, and the source S of the tenth transistor T31 is the output terminal of the pull-down module 30.

[0032] Specifically, such as Figure 2 and Figure 4 As shown, the tenth transistor T31 is an NMOS transistor, wherein the drain D of the tenth transistor T31 is connected to the drain D of the first transistor T21, the gate of the tenth transistor T31 is connected to the first node Q, and the source S of the tenth transistor T31 is connected to the first low voltage terminal to receive the first low power supply VGL1.

[0033] In some embodiments, the nth-level GOA unit further includes: A global reset module 50 is provided, the output of which is connected to the first node Q, the control terminal of which is connected to the control signal VST, and the input terminal of which is connected to the second high voltage terminal to access the second high power supply VGH2.

[0034] In some embodiments, the global reset module 50 includes: an eleventh transistor T44 of type N; The source S of the eleventh transistor T44 is the output terminal of the global reset module 50, the gate of the eleventh transistor T44 is the control terminal of the global reset module 50, and the drain D of the eleventh transistor T44 is the input terminal of the global reset module 50.

[0035] Specifically, as Figure 2 and Figure 4 shown, the eleventh transistor T44 is an NMOS transistor. The source S of the eleventh transistor T44 is connected to the first node Q. The gate of the eleventh transistor T44 is connected to the control signal VST. The drain D of the eleventh transistor T44 is connected to the second high voltage terminal to access the second high power supply VGH2.

[0036] In some embodiments, it further includes: The first common terminal and the second common terminal are ground terminals; The first common voltage GND1 is greater than the first low power supply VGL1, and the second common voltage GND2 is less than the first high power supply VGH1.

[0037] Specifically, both the first common terminal and the second common terminal of the present application can adopt ground GND. In fact, the first common terminal can also be connected to a constant voltage low level VGL3. The second common terminal can also be connected to a constant voltage high level VGH3. The high level VGH3 of the voltage connected to the ground terminal is greater than the first low power supply VGL1. Because the second high power supply VGH2 is greater than the first high power supply VGH1, the second low power supply VGL2 is less than the first low power supply VGL1, the first common voltage GND1 is greater than the first low power supply VGL1, and the second common voltage GND2 is less than the first high power supply VGH1. Therefore, VGH3 < VGH1 < VGH2, and VGL3 > VGL1 > VGL2. It is preferred that both the first common terminal and the second common terminal of the present application adopt ground GND to achieve.

[0038] Exemplarily, as Figure 2 and Figure 4 shown, the nth - stage GOA unit includes the first transistor T21 to the eleventh transistor T44. The first transistor T21 and the third transistor T42 are both PMOS. The second transistor T11, the fourth transistor T43 to the eleventh transistor T44 are all NMOS. The waveform of the nth - stage scan signal Gn[n] output by the nth - stage scan line is as Figure 3 shown, Figure 3The relationship between the multi-level scan signals and the first clock signal CK1 and the second clock signal XCK1 is shown. The pulse widths of both the first clock signal CK1 and the second clock signal XCK1 are twice the pulse width of the nth level scan signal Gn[n]. Furthermore, the first clock signal CK1 and the second clock signal XCK1 are out of phase. The second high power supply VGH2 is greater than the first high power supply VGH1, the second low power supply VGL2 is less than the first low power supply VGL1, and the first low power supply VGL1 is less than the first high power supply VGH1, i.e., second low power supply VGL2 < first low power supply VGL1 < first high power supply VGH1 < second high power supply VGH2. The high potentials of the first clock signal CK1 and the second clock signal XCK1 are greater than the second high power supply VGH2, and the low potentials of the first clock signal CK1 and the second clock signal XCK1 are less than the second low power supply VGL2. In addition, since the first common voltage GND1 is greater than the first low power supply VGL1, and the second common voltage GND2 is less than the first high power supply VGH1, that is, the low potential VGL of the first clock signal CK1 and the second clock signal XCK1 < the second low power supply VGL2 < the first low power supply VGL1 < the first common voltage GND1 (or low level VGL3), and the second common voltage GND2 (or high level VGH3) < the first high power supply VGH1 < the second high power supply VGH2 < the high potential VGH of the first clock signal CK1 and the second clock signal XCK1.

[0039] The following description uses the second-level GOA unit G2, the second clock signal XCK1, and the first clock signal CK1 as examples: During period t1: such as Figure 3 , Figure 4 and Figure 5As shown, for the second-level GOA unit G2, when the (n-1)th level scanning signal provided by the (n-1)th level GOA unit to the second-level GOA unit G2, i.e., the first level scanning signal Gn[1], is high, since the second transistor T11 is an NMOS and the source S of the second transistor T11 is connected to the second common terminal, the second common voltage GND2 connected to the second common terminal is low. Therefore, the second transistor T11 in the second-level GOA unit G2 is turned on, and the second common voltage GND2 connected to the second common terminal is written to the first node Q through the second transistor T11. Since the first transistor T21 is a PMOS and the source S of the first transistor T21 is connected to the first high power supply VGH1, the first transistor T21 is turned on. The second-level GOA unit G2 is connected to the first clock signal CK1 and the second clock signal XCK1. During t1, the second clock signal XCK1 is high and the first clock signal CK1 is low. Its pulse width is twice that of Gn. Therefore, during the high-level writing of the first-stage scan signal Gn[1] and the high-level output of the second-stage scan signal Gn[2], the third transistor T42, the seventh transistor T52, the eighth transistor T53 and the ninth transistor T41 are turned on, and the sixth transistor T51, the fourth transistor T43 and the fifth transistor T45 are turned off. Since VST is low, the eleventh transistor T44 is turned off. The voltage for writing to the first node Q is the second common voltage GND2, and the first transistor T21 is a PMOS transistor, so the first transistor T21 is turned on. Since the source S of the first transistor T21 is connected to the first high power supply VGH1, the second-stage scan signal Gn[2] output by the drain D of the first transistor T21 changes from low to high. Since the sixth transistor T51 is off and the ninth transistor T41, the seventh transistor T52, and the eighth transistor T53 are on, the voltage written to the second node Qb through the ninth transistor T41 is the second low power supply VGL2. Since the tenth transistor T31 is off, although the third transistor T42 is on, the fourth transistor T43 is off. Therefore, the potential of the first node Q will not be pulled down through the fourth transistor T43. Thus, the potential of the first node Q is maintained at the second common voltage GND2.

[0040] During period t2, the voltage level is low. Therefore, the potential of the first node Q is maintained at the second high power supply VGH2, continuously turning off or shutting down the first transistor T21.

[0041] During period t3: such as Figure 3 , Figure 4 and Figure 7As shown, the first clock signal CK1 and the second clock signal XCK1 are reversed again. The second clock signal XCK1 is at a high level, the first clock signal CK1 is at a low level, and the second-level scan signal Gn[2] is at a low level. Therefore, the seventh transistor T52, the eighth transistor T53 and the ninth transistor T41 are turned on, and the first transistor T21, the second transistor T11, the fourth transistor T43, the fifth transistor T45 and the sixth transistor T51 are turned off. Since the sixth transistor T51 is turned off, and the seventh transistor T52, the eighth transistor T53 and the ninth transistor T41 are turned on, the source S of the ninth transistor T41 is connected to the second low power supply VGL2. Therefore, the second node Qb is pulled down to the second low power supply VGL2 through the ninth transistor T41, and the potential of the first node Q is maintained at the second high power supply VGH2.

[0042] During t4: such as Figure 2 , Figure 4 and Figure 6 As shown, during t4, the second clock signal XCK1 is at a low level, the first clock signal CK1 is at a high level, and the voltage of the second-level scan signal Gn[2] remains at a low level.

[0043] The GOA circuit of this application employs NMOS and PMOS processes. The NMOS can be an oxide device or an LTPS device, or it can be an indium gallium zinc oxide thin-film transistor or a transistor made of other materials. For the output transistor of VGH, a high-mobility PMOS device is used. In this application, the high potential VGH of the first clock signal CK1 / second clock signal XCK1 > the second high power supply VGH2 > the first high power supply VGH1, and the low potential VGL of the first clock signal CK1 / second clock signal XCK1 < the second low power supply VGL2 < the first low power supply VGL1. Furthermore, since the first common voltage GND1 is greater than the first low power supply VGL1, and the second common voltage GND2 is less than the first high power supply VGH1, that is, the low potential VGL of the first clock signal CK1 and the second clock signal XCK1 < the second low power supply VGL2 < the first low power supply VGL1 < the first common voltage GND1 (or low level VGL3), and the second common voltage GND2 (or high level VGH3) < the first high power supply VGH1 < the second high power supply VGH2 < the high potential VGH of the first clock signal CK1 and the second clock signal XCK1. This allows for better shutdown of the TFT in the GOA circuit by utilizing the voltage difference between the high and low power supplies, thereby eliminating the need for the anti-drift TFT.

[0044] For example, such as Figure 3 , Figure 4 and Figure 5As shown, during period t1, when the first level GOA unit G1 write stage, i.e. the first level scan signal Gn[1] is high, since the first clock signal CK1 is low, taking the first node Q controlling the first transistor T21 and the second node Qb controlling the tenth transistor T31 as an example, the first transistor T21 is a PMOS. Assuming that the threshold voltage Vth of the first transistor T21 has a negative drift phenomenon, the potential of the first node Q connected to the gate of the first transistor T21 during period t1 is the second common voltage GND2. The source S of the first transistor T21 is connected to the first high power supply VGH1. Since the voltage difference between the second common voltage GND2 and the first high power supply VGH1 is small, the voltage difference between the gate and source of the first transistor T21, i.e. VGS, is still less than the threshold voltage Vth. The first transistor T21 can still be turned on normally, so the anti-negative drift unit can be removed.

[0045] For example, such as Figure 3 , Figure 4 and Figure 5 As shown, during period t1, when the first-level GOA unit G1 write stage, i.e., the first-level scan signal Gn[1] is high, since the first clock signal CK1 is low, therefore, taking the fourth transistor T43 and the fifth transistor T45 as examples, the fourth transistor T43 and the fifth transistor T45 are both NMOS. Assuming that the threshold voltage Vth of the fourth transistor T43 or the fifth transistor T45 has a negative drift phenomenon, the first clock signal CK1 connected to the gate of the fourth transistor T43 or the fifth transistor T45 is low during period t1, and the source of the fourth transistor T43 and the source of the fifth transistor T45 are both connected to the second common voltage GND2. Since the low level VGL of the first clock signal CK1 is less than the second common voltage GND2, the voltage difference between the gate and source of the fourth transistor T43, i.e., VGS, is negative, which is much less than the threshold voltage Vth, so the fourth transistor T43 can be turned off well. Similarly, the fifth transistor T45 can also be turned off well, so the anti-negative drift unit can be removed.

[0046] For example, such as Figure 3 , Figure 4 and Figure 5As shown, during period t1, when the first-level GOA unit G1 is written, i.e., the first-level scan signal Gn[1] is high, the first clock signal CK1 is low. Therefore, taking the sixth transistor T51 as an example, the sixth transistor T51 is an NMOS. The gate of the sixth transistor T51 is connected to the first clock signal CK1 at a low level, and the source of the sixth transistor T51 is connected to the first common voltage GND1. Since the low level VGL of the first clock signal CK1 is less than the first common voltage GND1, the voltage difference between the gate and source of the sixth transistor T51, i.e., VGS, is negative, which is much less than the threshold voltage Vth. The sixth transistor T51 can be turned off well, so the anti-negative drift unit can be removed.

[0047] For example, such as Figure 3 , Figure 4 and Figure 6 As shown, the tenth transistor T31 is an NMOS. Assuming a negative drift occurs in the threshold voltage of the tenth transistor T31, the potential of the second node Qb connected to the gate of the tenth transistor T31 during period t2 is the first common voltage GND1. The source S of the first transistor T21 is connected to the first low power supply VGL1. Since the voltage difference between the first common voltage GND1 and the first low power supply VGL1 is large, still greater than the threshold voltage Vth, the tenth transistor T31 can still be turned on normally. Therefore, the anti-drift unit can be removed. The working principle is the same in other stages, thus realizing the removal of the anti-drift TFT unit.

[0048] For example, such as Figure 3 , Figure 4 and Figure 6 As shown, during period t2, both the eighth transistor T53 and the ninth transistor T41 are NMOS transistors. Assuming that the threshold voltages of both transistors exhibit negative drift, the second clock signal XCK1 connected to the gates of transistors T53 and T41 is at a low level. The sources S of transistors T53 and T41 are connected to a second low power supply VGL2. Since VGL2 is greater than the low level VGL of the second clock signal XCK1 (VGL < VGL2), the voltage difference between the gate and source of transistor T53, VGS, is negative, much less than the threshold voltage Vth, effectively turning off transistor T53. Similarly, the voltage difference between the gate and source of transistor T41, VGS, is also negative, much less than the threshold voltage Vth, effectively turning off transistor T41 as well. Therefore, the anti-drift unit can be eliminated.

[0049] This application utilizes a high-mobility PMOS device for the output transistor of VGH and employs a dual VGH and VGL design to achieve highly stable signal output. Simultaneously, the TFT of the anti-drift unit can be eliminated, enabling a narrow-border design. Furthermore, the first node Q and the second node Qb only require the first common voltage GND1 and the second common voltage GND2 to achieve good output of high and low potential scanning signals for the GOA circuit. While maintaining its narrow border, it exhibits low power consumption, good stability, and fulfills the normal functions of the GOA, resulting in a long service life.

[0050] In some embodiments, it also includes: The (n-1)th level GOA unit, the nth level GOA unit, the (n+1)th level GOA unit, and the (n+2)th level GOA unit have the same structure, where n is a positive integer greater than 1; where, In the (n+2)th level GOA unit, the second input terminal of the pull-down module 30 and the first input terminal of the inverter 60 are both connected to the second clock signal terminal to receive the second clock signal XCK1. In the (n+2)th level GOA unit, the second input terminal of the inverter 60 is connected to the first clock signal terminal to receive the first clock signal CK1. The second input terminal of the pull-down module 30 and the first input terminal of the inverter 60 in the (n+1)th level GOA unit are both connected to the third clock signal terminal to receive the third clock signal CK2. The second input terminal of the inverter 60 in the (n+1)th level GOA unit is connected to the fourth clock signal terminal to receive the fourth clock signal XCK2. The second input terminal of the pull-down module 30 and the first input terminal of the inverter 60 in the (n-1)th level GOA unit are both connected to the fourth clock signal terminal to receive the fourth clock signal XCK2. The second input terminal of the inverter 60 in the (n-1)th level GOA unit is connected to the third clock signal terminal to receive the third clock signal CK2. Wherein, the first clock signal CK1 and the third clock signal CK2 are out of phase by half a time delay period, the second clock signal XCK1 and the fourth clock signal XCK2 are out of phase by half a time delay period, and the third clock signal CK2 and the fourth clock signal XCK2 are out of phase.

[0051] Specifically, such as Figure 1 , Figure 5 , Figures 8 to 9As shown, the circuit structures of the third-level GOA unit G3, the fourth-level GOA unit G4, and the fifth-level GOA unit G5 are the same as those of the second-level GOA unit G2. The control terminal of the pull-up control module 20 of the third-level GOA unit G3 is connected to the output terminal of the pull-up module 10 of the second-level GOA unit G2. Similarly, the control terminal of the pull-up control module 20 of the fourth-level GOA unit G3 is connected to the output terminal of the pull-up module 10 of the third-level GOA unit G3, and the control terminal of the pull-up control module 20 of the fifth-level GOA unit G3 is connected to the output terminal of the pull-up module 10 of the fourth-level GOA unit G2. The gates of the fourth transistor T43, the fifth transistor T45, and the sixth transistor T51 of the second-level GOA unit G2 receive the first clock signal CK1, and the gates of the eighth transistor T53 and the ninth transistor T41 receive the second clock signal XCK1. However, the third-level GOA unit G3 receives another set of clock signals, namely the third clock signal CK2 and the fourth clock signal XCK2. That is to say, as... Figure 4 and Figure 8 As shown, in the third-stage GOA unit G3, compared to the second-stage GOA unit G2, the gates of the fourth transistor T43, the fifth transistor T45, and the sixth transistor T51 of the third-stage GOA unit G3 receive the third clock signal CK2, while the gates of the eighth transistor T53 and the ninth transistor T41 receive the fourth clock signal XCK2. The TFT turn-off of the third-stage GOA unit G3 can be referred to the embodiment of the second-stage GOA unit G2 described above, and will not be repeated here.

[0052] In this unit, the fourth-level GOA unit G4 is the same as the second-level GOA unit G2, connecting the first clock signal CK1 and the second clock signal XCK1. However, in the fourth-level GOA unit G4, the TFT originally connected to the first clock signal CK1 is now connected to the second clock signal XCK1, and the TFT originally connected to the second clock signal XCK1 is now connected to the first clock signal CK1. For example... Figure 4 and Figure 9 As shown, in the fourth-stage GOA unit G4, compared to the second-stage GOA unit G2, the gates of the fourth transistor T43, the fifth transistor T45, and the sixth transistor T51 of the fourth-stage GOA unit G4 receive the second clock signal XCK1, while the gates of the eighth transistor T53 and the ninth transistor T41 receive the first clock signal CK1. The TFT turn-off of the fourth-stage GOA unit G4 can be referred to the embodiment of the second-stage GOA unit G2 described above, and will not be repeated here.

[0053] In this unit, the fifth GOA unit G5 is the same as the third GOA unit G3, connected to the third clock signal CK2 and the fourth clock signal XCK2. However, in the fifth GOA unit G5, the TFT originally connected to the third clock signal CK2 is now connected to the fourth clock signal XCK2, and the TFT originally connected to the fourth clock signal XCK2 is now connected to the third clock signal CK2. For example... Figure 8 and Figure 10 As shown, in the fifth GOA unit G5, relative to the third-stage GOA unit G3, the gates of the fourth transistor T43, the fifth transistor T45, and the sixth transistor T51 receive the fourth clock signal XCK2, while the gates of the eighth transistor T53 and the ninth transistor T41 receive the third clock signal CK2. The TFT turn-off of the fifth GOA unit G5 can be referred to the embodiment of the second-stage GOA unit G2 described above, and will not be repeated here. In summary, similarly, the circuit structure and clock signal of the fifth-stage GOA unit G1 are the same as those of the first-stage GOA unit G1; the circuit structure and clock signal of the sixth-stage GOA unit G6 are the same as those of the second-stage GOA unit G2; and the circuit structure and clock signal of the seventh-stage GOA unit G7 are the same as those of the third-stage GOA unit G3. That is, G1 is the same as G5, G6 is the same as G2, and G7 is the same as G3.

[0054] This circuit design eliminates the need for the anti-drift unit, reducing the number of TFTs and achieving the narrow border requirement. Simultaneously, the dual VGL and VGH design ensures signal output stability, and grounding controls the voltages of the first node Q and second node Qb, further enhancing signal stability. Slight fluctuations in the first node Q and second node Qb, or severe device drift, will not affect the stable scanning signal output of the GOA circuit. The GOA circuit provided in this application utilizes a combination of PMOS and NMOS technology, eliminating the need for the anti-drift unit and reducing the number of TFTs to meet the panel's GOA display scanning signal output requirements and narrow border specifications. The dual VGL and VGH design improves output stability, and the capacitors can be reduced while maintaining functionality and device requirements, thus extending the panel's lifespan and product specifications. The GOA circuit structure of this application is simple, reducing circuit layout space while ensuring functionality, thus meeting the narrow bezel requirement of the display panel.

[0055] The foregoing has provided a detailed description of a GOA circuit and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A GOA circuit, characterized in that, It includes multiple cascaded GOA units, and the nth level GOA unit includes: Pull-up module (10), the input terminal of the pull-up module (10) is connected to the first high voltage terminal to receive the first high power supply (VGH1); the output terminal of the pull-up module (10) is connected to the nth scan line to output the nth scan signal (Gn[n]); the control terminal of the pull-up module (10) is connected to the first node (Q); A pull-down module (30) is provided, the output of which is connected to the output of the pull-up module (10), and the control terminal of the pull-down module (30) is connected to the second node (Qb). The input terminal of the pull-down module (30) is connected to the first low voltage terminal to receive a first low power supply (VGL1), which is less than the first high power supply (VGH1). A pull-down sustaining module (40) is provided, the output of which is connected to a first node (Q), and the input of which is connected to a second high voltage terminal to receive a second high power supply (VGH2). The control terminal of the pull-down sustaining module (40) is connected to a first clock signal terminal to receive a first clock signal (CK1). The second high power supply (VGH2) is greater than the first high power supply (VGH1). An inverter (60) is provided, wherein the first control terminal of the inverter (60) is connected to the first clock signal terminal to receive the first clock signal (CK1); the second control terminal of the inverter (60) is connected to the second clock signal terminal to receive the second clock signal (XCK1), the second clock signal (XCK1) being inverted from the first clock signal (CK1); the first input terminal of the inverter (60) is grounded to receive a first common voltage; the second input terminal of the inverter (60) is connected to the second low voltage terminal to receive a second low power supply (VGL2); the second low power supply (VGL2) is less than the first low power supply (VGL1); the third control terminal of the inverter (60) is connected to the first node (Q); and the output terminal of the inverter (60) is connected to the second node (Qb) to control the potential of the second node (Qb). Wherein, the high level of the first clock signal (CK1) and the second clock signal (XCK1) is greater than the second high power supply (VGH2), and the low level of the first clock signal (CK1) and the second clock signal (XCK1) is less than the second low power supply (VGL2).

2. The GOA circuit according to claim 1, characterized in that, The pull-up module (10) includes a first transistor (T21) of P-type channel, the source of the first transistor (T21) is the input terminal of the pull-up module (10), the gate of the first transistor (T21) is the control terminal of the pull-up module (10), and the drain of the first transistor (T21) is the output terminal of the pull-up module (10).

3. The GOA circuit according to claim 2, characterized in that, The nth-level GOA unit also includes: Pull-up control module (20), the output terminal of the pull-up control module (20) is connected to the first node (Q), the input terminal of the pull-up control module (20) is connected to the second common terminal to receive the second common voltage (GND2), and the control terminal of the pull-up control module (20) is connected to the output terminal of the pull-up module of the (n-1)th level GOA unit.

4. The GOA circuit according to claim 3, characterized in that, The pull-up control module (20) includes: a second transistor (T11) of type N; The drain of the second transistor (T11) is the output terminal of the pull-up control module (20), the source of the second transistor (T11) is the input terminal of the pull-up control module (20), and the gate of the second transistor (T11) is the control terminal of the pull-up control module (20).

5. The GOA circuit according to claim 4, characterized in that, The pull-down sustaining module (40) includes: a third transistor (T42) of P-type channel, a fourth transistor (T43) of N-type channel, and a fifth transistor (T45); The drain of the fourth transistor (T43) and the drain of the fifth transistor (T45) are both input terminals of the pull-down sustaining module (40); The gates of the fourth transistor (T43) and the fifth transistor (T45) are both control terminals of the pull-down sustaining module (40); The drain of the third transistor (T42) and the source of the fifth transistor (T45) are both output terminals of the pull-down sustaining module (40); The gate of the third transistor (T42) is connected to the second node (Qb), and the source of the third transistor (T42) is connected to the source of the fourth transistor (T43).

6. The GOA circuit according to claim 5, characterized in that, The inverter (60) includes: a sixth transistor (T51), a seventh transistor (T52), an eighth transistor (T53), and a ninth transistor (T41) of type N. The gate of the sixth transistor (T51) is the first control terminal of the inverter (60), and the drain of the sixth transistor (T51) is the first input terminal of the inverter (60). The gate of the eighth transistor (T53) and the gate of the ninth transistor (T41) are both the second control terminals of the inverter (60), and the source of the eighth transistor (T53) and the source of the ninth transistor (T41) are both the second input terminals of the inverter (60). The gate of the seventh transistor (T52) is the third control terminal of the inverter (60). The source of the sixth transistor (T51), the drain of the seventh transistor (T52), and the drain of the ninth transistor (T41) are all output terminals of the inverter (60). The source of the seventh transistor (T52) is connected to the drain of the eighth transistor (T53).

7. The GOA circuit according to claim 6, characterized in that, The pull-down module (30) includes: a tenth transistor (T31) of type N; The drain of the tenth transistor (T31) is the output terminal of the pull-down module (30), the gate of the tenth transistor (T31) is the control terminal of the pull-down module (30), and the source of the tenth transistor (T31) is the input terminal of the pull-down module (30).

8. The GOA circuit according to claim 7, characterized in that: The (n-1)th level GOA unit, the nth level GOA unit, the (n+1)th level GOA unit, and the (n+2)th level GOA unit have the same structure, where n is a positive integer greater than 1; where, The second input terminal of the pull-down module (30) and the first input terminal of the inverter (60) in the (n+2)th level GOA unit are both connected to the second clock signal terminal to receive the second clock signal (XCK1). The second input terminal of the inverter (60) in the (n+2)th level GOA unit is connected to the first clock signal terminal to receive the first clock signal (CK1). The second input terminal of the pull-down module (30) and the first input terminal of the inverter (60) in the (n+1)th level GOA unit are both connected to the third clock signal terminal to receive the third clock signal (CK2). The second input terminal of the inverter (60) in the (n+1)th level GOA unit is connected to the fourth clock signal terminal to receive the fourth clock signal (XCK2). The second input terminal of the pull-down module (30) and the first input terminal of the inverter (60) in the (n-1)th level GOA unit are both connected to the fourth clock signal terminal to receive the fourth clock signal (XCK2). The second input terminal of the inverter (60) in the (n-1)th level GOA unit is connected to the third clock signal terminal to receive the third clock signal (CK2). Wherein, the first clock signal (CK1) is half a time delay period different from the third clock signal (CK2), the second clock signal (XCK1) is half a time delay period different from the fourth clock signal (XCK2), and the third clock signal (CK2) is out of phase with the fourth clock signal (XCK2).

9. The GOA circuit according to any one of claims 3 to 8, characterized in that: The second common terminal is the ground terminal; The first common voltage (GND1) is greater than the first low power supply (VGL1), and the second common voltage (GND2) is less than the first high power supply (VGH1).

10. A display panel, characterized in that, Includes the GOA circuit as described in any one of claims 1 to 9.

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