A low voltage power rail circuit applied to a high side floating well of a motor drive circuit

Abstract

The application belongs to the technical field of power management integrated circuits, and particularly relates to a low-voltage power rail circuit applied to a high-side floating basin of a motor driving circuit. The circuit realizes a stable power rail in the floating basin through a super source follower architecture and a bias of MOS tube threshold tracking. The circuit has the advantages that it can track the MOS tube threshold voltage to realize lower static power consumption, can realize fast transient response under different load conditions, has good anti-dv / dt noise capability, and can realize small overshoot voltage during load switching under small decoupling capacitance, thereby reducing the circuit area.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power management integrated circuits, and particularly relates to a low-voltage power rail circuit applied to a high-side floating basin of a motor driving circuit. BACKGROUND

[0002] As a common power management circuit, a low dropout linear regulator (LDO) has the advantages of simple structure, low cost, low noise, low power consumption, and simple peripheral circuit, and is widely used in medical treatment, computers, industrial basic equipment, and portable products. A traditional LDO has good transient response and a power supply ripple rejection ratio (PSRR), but a chip external hanging capacitor area is large, which is not conducive to SOC integration. A design difficulty of a traditional capacitorless LDO (CLDO) is that stability and transient response speed are difficult to be considered. A CLDO based on a super source follower (SSF) structure has a better transient response performance than a CLDO based on a traditional operational amplifier structure under the condition of equivalent power efficiency, and is a current research hotspot.

[0003] A high side of a traditional double NMOS high-voltage motor driving circuit is generally driven by using a thick gate oxide process, and a MOS gate source can withstand high voltage, which is convenient for circuit design and has good process robustness, but has a large area and slow speed, which is not conducive to high-speed and small-area applications. A thin gate oxide process can overcome the above shortcomings, but due to the voltage resistance limit of VGS, the circuit design difficulty is increased. A low-voltage power rail is arranged in the driving high-side basin, which can greatly simplify the circuit design difficulty of the thin gate oxide process under the condition of meeting the circuit reliability application condition. SUMMARY

[0004] The purpose of the application is to provide an implementation circuit of a simple power rail applied to a high-side floating basin of a high-voltage motor driving circuit. The circuit can realize good transient performance and stability under a small decoupling capacitor, has the characteristics of anti-dv / dt noise ability and low static power consumption, and can meet the application with low DC precision requirement.

[0005] The technical scheme of the application is as follows:

[0006] A low-voltage power rail circuit applied to a high-side floating basin of a motor driving circuit comprises a threshold tracking bias module and a regulator module.

[0007] The threshold tracking bias module comprises a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a Zener diode Z0, and is used to generate a bias voltage of the regulator circuit.

[0008] The regulator module comprises a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, and a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6, for generating a stable low-voltage power rail in a high-side floating basin.

[0009] Wherein, the anode of the Zener tube Z0 is connected to the floating ground SW, and the cathode is connected to the high-side bus power rail BST through the first resistor R1, and a first bias voltage BN is generated at the connection between the cathode of the Zener tube Z0 and the first resistor R1; the gate of the first NMOS tube MN1 is connected to the drain thereof, and the gate and the drain of the first NMOS tube MN1 are connected to the first bias voltage BN, and the source of the first NMOS tube MN1 is connected to the source of the first PMOS tube MP1; the gate of the first PMOS tube MP1 is connected to the drain of the second PMOS tube MP2 and the source of the third PMOS tube MP3, the source of the first PMOS tube MP1 is connected to the source of the first NMOS tube MN1, and the drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2 through the second resistor R2; the gate of the second PMOS tube MP2 is connected to the gate and the drain of the third PMOS tube MP3, the drain of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1 and the source of the third PMOS tube MP3, and the source of the second PMOS tube MP2 is connected to the second resistor R2 to generate a second bias voltage BP; the gate of the third PMOS tube MP3 is connected to the drain thereof and the gate of the second PMOS tube MP2, and the drain of the third PMOS tube MP3 is connected to the floating ground SW through the third resistor R3; the first capacitor C1 has two ends connected to the first bias voltage BN and the second bias voltage BP; the second capacitor C2 has two ends connected to the second bias voltage BP and the floating ground SW; and the third capacitor C3 is connected to the first bias voltage BN and the floating ground SW.

[0010] The gate of the fourth PMOS MP4 is connected with the drain of the fourth PMOS MP4, and the gate of the fifth PMOS MP5 and the drain of the second NMOS MN2 are connected, the source of the fourth PMOS MP4 is connected with the high side bus power rail BST; the gate of the fifth PMOS MP5 is connected with the gate and the drain of the fourth PMOS MP4, the drain of the fifth PMOS is connected with the source of the second NMOS MN2, the source of the sixth PMOS MP6 and the drain of the fourth NMOS MN4, the connecting point is the output end output voltage OUT, the source of the fifth PMOS MP5 is connected with the high side bus power rail BST; the gate of the second NMOS MN2 is connected with the first bias voltage BN, the drain of the second NMOS MN2 is connected with the gate and the drain of the fourth PMOS MP4 and the gate of the fifth PMOS MP5, the source of the second NMOS MN2 is connected with the output end; the gate of the sixth PMOS MP6 is connected with the second bias voltage BP, the drain of the sixth PMOS is connected with the gate and the drain of the third NMOS MN3 and the gate of the fourth NMOS, the source of the sixth PMOS is connected with the output end; the gate and the drain of the third NMOS MN3 are connected, the gate of the fourth NMOS MN4 and the drain of the sixth PMOS MP6 are connected, and the source is connected with the floating ground SW; the source of the fourth NMOS MN4 is connected with the floating ground SW; the two ends of the fourth capacitor C4 are connected with the gate of the fifth PMOS MP5 and the output end respectively; the two ends of the fifth capacitor C5 are connected with the gate of the fourth NMOS and the output end respectively; the two ends of the sixth capacitor C6 are connected with the output end and the floating ground SW respectively.

[0011] The driving high side simple power rail implementation circuit based on the super source follower architecture regulator with bidirectional load capacity of pull current and fill current is provided in the application, compared with the existing super source follower structure regulator, small load jump peak can be realized under small decoupling capacitor, the transient performance of the circuit is enhanced, and the circuit area is reduced; in order to reduce the power consumption of the bidirectional load regulator, the threshold tracking bias circuit is specially designed, as long as the size of the tube is properly set, the circuit can extract the threshold of the MOS tube, ensure that the regulator is biased in the subthreshold region, and the power consumption is reduced. The circuit provided in the application is applied to driving the high side, a stable and reliable low voltage power rail is provided, the design difficulty of the thin gate oxide process high voltage drive stage circuit is greatly simplified, and the integration degree of the circuit unit is increased. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 The circuit diagram of the threshold tracking bias part of the application.

[0013] Figure 2 The circuit diagram of the regulator part of the application. DETAILED DESCRIPTION

[0014] The application will be further described below with reference to the accompanying drawings.

[0015] As Figure 1 shown, the Zener Z0 and resistor R1 in the threshold tracking bias module constitute a low-precision power rail providing bias for the threshold extraction circuit and power supply for the biasing network BN. The threshold extraction circuit is composed of MN1, MP1, MP2, MP3, R2 and R3.

[0016] When the circuit is working, MP2 works in the linear region, and the rest of the MOS transistors work in the saturation region, so the following relationship is obtained:

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023] Take , , through equations (1)-(6) the following can be obtained:

[0024]

[0025] Thus the threshold extraction tracking function is realized, as long as the size of MN1 is set, the regulator part can be guaranteed to be biased in the sub-threshold region at static state. Capacitors C1-C3 act as decoupling capacitors for biasing BN and BP.

[0026] As Figure 2As shown, MN2 and MP4, MP5 in the regulator part constitute a pull current negative feedback fast loop. When the load suddenly increases, due to the small decoupling capacitor C6, the OUT potential rapidly decreases, MN2 will enter the saturation region from the sub-threshold region, and MP6 will enter the cutoff region from the sub-threshold region. Due to MP4, MP5 and MN3, MN4 respectively constitute a 1-to-24 current mirror, resulting in the current of power transistor MP5 rapidly increasing, the current of power transistor MN4 rapidly decreasing, forming a push-pull, rapidly charging C6 to increase the OUT potential. MP6 and MN3, MN4 constitute a pull current negative feedback fast loop, the principle is the same as above. The transient response speed of the two fast loops is very fast, so even if C6 is only pf level, the ΔVOUT when the load jumps can also be controlled within a reasonable range. Capacitors C4, C5 act as Miller compensation capacitors, splitting the main and secondary poles of the loop, ensuring the stability of the loop.

[0027] In summary, compared with the traditional CLDO circuit, the transient performance of the present application is stronger while reducing the circuit area, and is suitable for driving high-side driver circuit such as DC precision requirement not too high power rail application.

Claims

1. A low voltage power rail circuit applied to a high side floating well of a motor drive circuit, characterized in that, Threshold tracking bias module and regulator module are included; The threshold tracking bias module includes a first NMOS tube MN1, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a Zener tube Z0, which are used to generate a bias voltage of a regulator circuit; The regulator module includes a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6, which are used to generate a stable low-voltage power supply rail in a high-side floating basin; The anode of the Zener tube Z0 is connected to a floating ground SW, and the cathode is connected to a high-side bus power supply rail BST through the first resistor R1, and a first bias voltage BN is generated at the connection between the cathode of the Zener tube Z0 and the first resistor R1; the gate of the first NMOS tube MN1 is connected to the drain thereof, and the gate and the drain of the first NMOS tube MN1 are connected to the first bias voltage BN, and the source of the first NMOS tube MN1 is connected to the source of the first PMOS tube MP1; the gate of the first PMOS tube MP1 is connected to the drain of the second PMOS tube MP2 and the source of the third PMOS tube MP3, the source of the first PMOS tube MP1 is connected to the source of the first NMOS tube MN1, and the drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2 through the second resistor R2; the gate of the second PMOS tube MP2 is connected to the gate and the drain of the third PMOS tube MP3, the drain of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1 and the source of the third PMOS tube MP3, and the source of the second PMOS tube MP2 is connected to the second resistor R2 to generate a second bias voltage BP; the gate of the third PMOS tube MP3 is connected to the drain thereof and the gate of the second PMOS tube MP2, and the drain of the third PMOS tube MP3 is connected to the floating ground SW through the third resistor R3; the first capacitor C1 has two ends connected to the first bias voltage BN and the second bias voltage BP; the second capacitor C2 has two ends connected to the second bias voltage BP and the floating ground SW; and the third capacitor C3 is connected to the first bias voltage BN and the floating ground SW. The gate of the fourth PMOS MP4 is connected with its drain, and the gate of the fifth PMOS MP5 and the drain of the second NMOS MN2 are connected, the source of the fourth PMOS MP4 is connected with the high side bus power rail BST; the gate of the fifth PMOS MP5 is connected with the gate and the drain of the fourth PMOS MP4, the drain of the fifth PMOS is connected with the source of the second NMOS MN2, the source of the sixth PMOS MP6 and the drain of the fourth NMOS MN4, the connecting point is the output end output voltage OUT, the source of the fifth PMOS MP5 is connected with the high side bus power rail BST; the gate of the second NMOS MN2 is connected with the first bias voltage BN, the drain of the second NMOS MN2 is connected with the gate and the drain of the fourth PMOS MP4 and the gate of the fifth PMOS MP5, the source of the second NMOS MN2 is connected with the output end; the gate of the sixth PMOS MP6 is connected with the second bias voltage BP, the drain of the sixth PMOS is connected with the gate and the drain of the third NMOS MN3 and the gate of the fourth NMOS, the source of the sixth PMOS is connected with the output end; the gate and the drain of the third NMOS MN3 are connected, and the gate of the fourth NMOS MN4 and the drain of the sixth PMOS MP6 are connected, and the source is connected with the floating ground SW; the source of the fourth NMOS MN4 is connected with the floating ground SW; the two ends of the fourth capacitor C4 are connected with the gate of the fifth PMOS MP5 and the output end respectively; the two ends of the fifth capacitor C5 are connected with the gate of the fourth NMOS and the output end respectively; the two ends of the sixth capacitor C6 are connected with the output end and the floating ground SW respectively.

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