A Wide Bandgap Semiconductor MOSFET Device Structure and Its Manufacturing Method

Abstract

The present invention relates to a wide-bandgap semiconductor MOSFET device structure and a manufacturing method thereof. A masking region is fabricated at the bottom of the gate trench in the cell region of the MOSFET device and in the termination region. The masking region is located in the epitaxial layer and a charge storage island is fabricated inside the masking region, and the doping of the charge storage island is opposite to that of the masking region. By forming a masking region at the bottom of the gate trench in the cell region and fabricating a charge storage island inside the masking region, the masking region does not need to be grounded. The masking region constructed under the gate trench can effectively reduce the electric field at the trench corner. The internal charge storage island will assist in the recovery after the depletion of the masking region during dynamic switching, thereby avoiding the loss of the bottom electric field shielding effect due to charge accumulation and recovery relaxation in the masking region during the forward recovery process, and also avoiding the degradation of the dynamic characteristics caused by the voltage floating of the masking region. At the same time, by fabricating a masking region and a charge storage island in the termination region, the electric field distribution in the termination region can be optimized and the termination efficiency of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a wide-bandgap semiconductor MOSFET device structure and a manufacturing method thereof. Background Art

[0002] The high electric field in the drift region of wide-bandgap semiconductor materials causes a very high electric field on the gate dielectric layer, and this problem is exacerbated at the trench corners, resulting in rapid breakdown of the gate dielectric layer at high drain voltages. To better protect the gate oxide layer of trench MOSFETs, especially at the bottom and trench corners, a P-type masking region is usually implanted at the bottom of the trench to protect the bottom of the gate trench. The introduced P-type masking regions must all be grounded. An ungrounded P-type masking region is in a floating state. During the high-speed switching process of the device, on the one hand, the P-type masking region is prone to losing the bottom electrical masking protection effect due to charge accumulation and recovery relaxation during the forward recovery from the reverse depletion to the recovery process. On the other hand, voltage floating will occur due to the inability of the charges inside the P-type masking region to recover quickly, resulting in the degradation of the device's dynamic characteristics. Grounding the P-type masking region requires a more complex process flow, which will increase the preparation difficulty and cost. Summary of the Invention

[0003] Based on the above description, the present invention provides a new wide-bandgap semiconductor MOSFET device structure, which forms a masking region at the bottom of the gate trench in the cell region and forms a charge storage island in the masking region by ion implantation to protect the gate. In addition, a masking region with a charge storage island is also introduced in the terminal region to improve the device characteristics.

[0004] The technical solution of the present invention to solve the above technical problems is as follows: A wide-bandgap semiconductor MOSFET device structure, in which masking regions are fabricated at the bottom of the gate trench in the device cell region and in the terminal region. The masking region is located in the epitaxial layer, and a charge storage island is fabricated inside the masking region. The doping of the charge storage island is opposite to that of the masking region.

[0005] As a preferred embodiment, when the terminal region is a JTE terminal, a charge storage island is fabricated inside the JTE terminal.

[0006] As a preferred embodiment, N charge storage islands are fabricated in the same masking region, where N≥1.

[0007] As a preferred embodiment, the masking regions are distributed at intervals along the gate length direction, and the charge storage islands are distributed in a continuous section along the gate length direction. At positions without a masking region, the charge storage island is in contact with the epitaxial layer.

[0008] As a preferred embodiment, the masking regions are distributed at intervals along the gate length direction, and the charge storage islands are distributed at intervals along the gate length direction and are in contact or not in contact with the epitaxial layer within the masking regions.

[0009] As a preferred embodiment, the masking regions are arranged in rows and / or columns in the epitaxial layer along the X-axis, Y-axis, and Z-axis directions.

[0010] As a preferred embodiment, it further includes an N+ substrate, an N-epitaxial layer, a P-well region, a source P+ region, a source N+ region, a gate, a source, a drain, and a terminal region. The source and the drain are respectively fabricated on two opposite outer surfaces of the N+ substrate. The cell region includes an N+ substrate, an N-epitaxial layer, a P-well region, and a source N+ region that are sequentially stacked. The gate sequentially passes through the source N+ region and the P-well region and is fabricated in the N-epitaxial layer and located between the source and the drain. The source P+ region is disposed on the periphery of the source N+ region. The terminal region includes a terminal structure fabricated in the epitaxial layer and a passivation layer fabricated on the terminal structure. The masking region is a P+ masking region, and the charge storage island is an N+ charge storage island.

[0011] The present invention also provides a manufacturing method for the above-mentioned wide-bandgap semiconductor MOSFET device structure, including the following steps:

[0012] Growing an epitaxial layer 1 on a wide-bandgap semiconductor material substrate, forming a masking region and a charge storage island by ion implantation, and growing an epitaxial layer 2 on the surface for the second time;

[0013] Forming a P-well region, a terminal structure, a source N+ region, and a source P+ region by ion implantation;

[0014] Dry etching to form a gate trench, growing a gate dielectric, growing and etching gate polysilicon, depositing and etching an interlayer dielectric;

[0015] Depositing and etching the source, depositing and etching a dielectric passivation layer, and depositing the drain.

[0016] As a preferred embodiment, the doping concentrations of the epitaxial layer 2 and the epitaxial layer 1 are different.

[0017] By forming a masking region at the bottom of the gate trench in the cell region and fabricating a charge storage island within the masking region in the present invention, the masking region does not need to be grounded. The masking region constructed below the gate trench can effectively reduce the electric field at the trench corner. The internal charge storage island will assist in the recovery after the masking region is depleted during dynamic switching, thereby avoiding the loss of the bottom electric field shielding effect due to charge accumulation and recovery relaxation during the forward recovery of the masking region, and also avoiding the degradation of the dynamic characteristics caused by the voltage floating of the masking region. At the same time, fabricating a masking region and a charge storage island in the terminal region can optimize the electric field distribution in the terminal region and improve the terminal efficiency of the device. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of one of the wide-bandgap semiconductor MOSFET device structures provided by an embodiment of the present invention;

[0019] Figures 2 to 7 It is a schematic structural diagram of several other wide-bandgap semiconductor MOSFET device structures provided by an embodiment of the present invention;

[0020] Figure 8 It is a process flow diagram of one of the wide-bandgap semiconductor MOSFET device structures provided by an embodiment of the present invention;

[0021] In the drawings, the list of components represented by each reference numeral is as follows:

[0022] 1 Gate trench, 2 Masking region, 3 Charge storage island, 4 N+ Substrate, 5 N- Epitaxial layer, 6 P-well region, 7 Source P+ region, 8 Source N+ region. Detailed Embodiments

[0023] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0025] As Figure 1 shown, in a wide-bandgap semiconductor MOSFET device structure, the improvement lies in that masking regions 2 are fabricated at the bottom of the gate trench 1 in the device cell region and in the terminal region. The masking regions 2 are located in the epitaxial layer and charge storage islands 3 are fabricated therein. The doping of the charge storage islands 3 is opposite to that of the masking regions 2.

[0026] In the present invention, a masking region is formed at the bottom of the gate trench in the cell region, and charge storage islands are formed by ion implantation in the masking region. By constructing a masking region under the gate trench, the electric field at the trench corner can be effectively reduced, and the masking region does not need to be grounded. The internal charge storage islands will assist in the recovery after the depletion of the masking region during dynamic switching, thereby avoiding the loss of the bottom electric field shielding effect due to charge accumulation and recovery relaxation in the masking region during the forward recovery process, and also avoiding the degradation of the dynamic characteristics caused by the voltage floating of the masking region. At the same time, by fabricating a masking region and charge storage islands in the terminal region, the electric field distribution in the terminal region can be optimized, and the terminal efficiency of the device can be improved.

[0027] It can be understood that in the present invention, the doping type of the masking region 2 is opposite to that of the epitaxial layer, and the doping type of the charge storage island 3 is opposite to that of the masking region 2. For example, if the epitaxial layer is N-doped, the masking region is P-type doped, and the charge storage island 3 is N-doped.

[0028] Furthermore, in the present invention, the terminal region structure can be either a JTE terminal structure or a field limiting ring structure. Refer to Figure 1 , when the terminal region structure is a JTE terminal structure, charge storage islands 3 are fabricated inside the JTE terminal; refer to Figure 2 , when the terminal structure is a field limiting ring structure, a masking region and charge storage islands are only fabricated in the epitaxial layer region under the field limiting ring.

[0029] Furthermore, refer to Figure 3 , the number of charge storage islands 3 inside the same masking region 2 can be 1 or greater than 1, that is, N charge storage islands are fabricated therein, where N≥1.

[0030] In the present invention, the masking regions can be distributed at intervals or continuously along the gate length direction.

[0031] Furthermore, refer to Figure 4 , the masking regions 2 are distributed at intervals along the gate length direction, and the charge storage islands 3 are continuously distributed along the gate length direction. At the positions without masking regions, the charge storage islands are in contact connection with the epitaxial layer, and the potentials of the two are kept consistent. This structure can clamp the potential of the masking region 2, limit the hole extraction therein, and prevent the masking region from being completely depleted. On the one hand, it avoids the loss of the electric field shielding function of the masking region, and on the other hand, it improves the phenomenon of voltage floating in the masking region, thereby improving the dynamic characteristics of the device.

[0032] Furthermore, the masking regions 2 are distributed at intervals along the gate length direction, and the charge storage islands 3 are distributed at intervals along the gate length direction and are in contact or not in contact with the epitaxial layer inside the masking region. For the non-contact structure, refer to Figure 1 , for the contact structure, refer to Figure 5 、 6 .

[0033] It should be further explained that when it contacts the epitaxial layer, that is, the charge storage island in the masking area is not completely surrounded by the masking area, but contacts the epitaxial layer at a certain position. The contact position is not fixed and can be on the left side, the right side, the corner, etc. Or two or more charge storage islands can be formed inside the masking area and contact the epitaxial layer at different positions. During the switching process, when the device is in the off state, the entire outer epitaxial layer is depleted, and the charge storage island is isolated by the depletion region and the masking area, and the electrons in it cannot leak out. As the device is turned on, the reverse bias gradually decreases, the charge storage island is no longer completely isolated, and the electrons stored in it begin to diffuse into the epitaxial layer, neutralizing the space charge therein, reducing the energy barrier, and enabling the current to flow more smoothly from the drain to the source, thereby improving the switching characteristics of the device.

[0034] In the present invention, the masking area in the epitaxial layer can be either only one layer or arranged in rows and / or columns along the X-axis, Y-axis, and Z-axis directions. For details, please refer to Figure 7 .

[0035] It can be understood that the device structure provided by the present invention further includes an N+ substrate 4, an N-epitaxial layer 5, a P-well region 6, a source P+ region 7, a source N+ region 8, a gate, a source, a drain, and a terminal region. The source and the drain are respectively fabricated on two opposite outer surfaces of the N+ substrate. The cell region includes an N+ substrate 4, an N-epitaxial layer 5, a P-well region 6, and a source N+ region 8 arranged in layers in sequence. The gate passes through the source N+ region 8 and the P-well region 6 in sequence and is fabricated in the N-epitaxial layer 5 and is located between the source and the drain. The source P+ region 7 is arranged on the outer periphery of the source N+ region 8. The terminal region includes a terminal structure fabricated in the epitaxial layer and a passivation layer fabricated on the terminal structure. The masking area 2 is a P+ masking area, and the charge storage island 3 is an N+ charge storage island.

[0036] The present invention also provides a manufacturing method for the above-mentioned wide-bandgap semiconductor MOSFET device structure. Please refer to Figure 8 , which specifically includes the following steps:

[0037] Grow an epitaxial layer one on a wide-bandgap semiconductor material substrate, form the masking area 2 and the charge storage island 3 by ion implantation, and grow an epitaxial layer two on the surface for the second time;

[0038] Form the P-well region 6, the terminal structure, the source N+ region 8, and the source P+ region 7 by ion implantation;

[0039] Dry-etch to form a gate trench, grow a gate dielectric, grow and etch gate polysilicon, deposit and etch an interlayer dielectric;

[0040] Deposit and etch the source, deposit and etch a dielectric passivation layer, and deposit the drain.

[0041] In the present invention, the doping concentrations of epitaxial layer two and epitaxial layer one may be the same or different.

[0042] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A wide bandgap semiconductor MOSFET device structure, characterized in that, A masking region is fabricated at the bottom of the gate trench in the device cell region and in the termination region. The masking region is located in the epitaxial layer and charge storage islands are fabricated inside it. The doping type of the charge storage islands is opposite to that of the masking region. When the termination region is a JTE termination, charge storage islands are fabricated inside the JTE termination. When the termination region is a field limiting ring structure, the masking region and the charge storage islands are only fabricated in the epitaxial layer region under the field limiting ring. N charge storage islands are fabricated in the same masking region, where N≥1. The masking regions are distributed at intervals along the gate length direction. The charge storage islands are distributed at intervals along the gate length direction and are in contact or not in contact with the epitaxial layer inside the masking region.

2. A wide bandgap semiconductor MOSFET device structure, characterized in that, A masking region is fabricated at the bottom of the gate trench in the device cell region and in the termination region. The masking region is located in the epitaxial layer and charge storage islands are fabricated inside it. The doping type of the charge storage islands is opposite to that of the masking region. When the termination region is a JTE termination, charge storage islands are fabricated inside the JTE termination. When the termination region is a field limiting ring structure, the masking region and the charge storage islands are only fabricated in the epitaxial layer region under the field limiting ring. N charge storage islands are fabricated in the same masking region, where N≥1. The masking regions are distributed at intervals along the gate length direction. The charge storage islands are distributed over the entire length along the gate length direction. At positions without a masking region, the charge storage islands are in contact with the epitaxial layer.

3. The wide bandgap semiconductor MOSFET device structure according to claim 1 or 2, characterized in that, The masking regions are arranged in rows and / or columns in the epitaxial layer along the X-axis, Y-axis, and Z-axis directions.

4. The wide bandgap semiconductor MOSFET device structure according to claim 1 or 2, characterized in that, It further includes an N+ substrate, an N-epitaxial layer, a P-well region, a source P+ region, a source N+ region, a gate, a source, a drain, and a termination region. The source and the drain are respectively fabricated on two opposite outer surfaces of the N+ substrate. The cell region includes an N+ substrate, an N-epitaxial layer, a P-well region, and a source N+ region which are sequentially stacked. The gate passes through the source N+ region and the P-well region in sequence and is fabricated in the N-epitaxial layer and located between the source and the drain. The source P+ region is disposed on the outer periphery of the source N+ region. The termination region includes a termination structure fabricated in the epitaxial layer and a passivation layer fabricated on the termination structure. The masking region is a P+ masking region, and the charge storage islands are N+ charge storage islands.

5. The manufacturing method of the wide bandgap semiconductor MOSFET device structure according to any one of claims 1 to 4, characterized in that, It includes the following steps: Grow an epitaxial layer 1 on a wide bandgap semiconductor material substrate, form the masking region and the charge storage islands by ion implantation, and grow an epitaxial layer 2 on the surface for the second time. Form the P-well region, the termination structure, the source N+ region, and the source P+ region by ion implantation. Dry etch to form a gate trench, grow a gate dielectric, grow and etch gate polysilicon, deposit and etch an interlayer dielectric. Deposit and etch the source, deposit and etch a dielectric passivation layer, deposit the drain.

6. The manufacturing method of the wide bandgap semiconductor MOSFET device structure according to claim 5, wherein The doping concentrations of the epitaxial layer 2 and the epitaxial layer 1 are different.

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