A wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof

Abstract

The present invention provides a wide bandgap semiconductor trench MOSFET device structure and a method for manufacturing the same. The structure includes a substrate, an epitaxial layer, a first P+ shielding layer, a second P+ shielding layer, a first source P+ region, and a second source P+ region; the epitaxial layer is grown on the substrate; the first source P+ region, the first P+ shielding layer, the second source P+ region, and the second P+ shielding layer are sequentially spaced apart in the epitaxial layer along a horizontal direction; and a P-Bus region is formed between the first source P+ region and the first P+ shielding layer, and / or between the second source P+ region and the second P+ shielding layer, and / or between the first P+ shielding layer and the second source P+ region to achieve electrical connection between the P+ shielding layer and the source P+ region. This structure not only greatly improves the device's conduction characteristics, but also improves the trade-off between the device's specific on-resistance and gate oxide reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. Background Art

[0002] Currently, silicon carbide (SiC) devices can achieve P-type doping through ion implantation or epitaxial growth. However, it is difficult to achieve P-type doping through ion implantation for materials with wider bandgap widths than silicon carbide, such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN). P-type doping can be achieved through special processes such as epitaxial growth or oxide growth. However, in actual operation, wide bandgap semiconductor trench MOSFET devices still have several problems in process manufacturing and application: (1) The traditional device structure does not provide sufficient protection for the gate, and the electric field at the gate trench corner is easily concentrated, resulting in rapid breakdown of the gate dielectric layer under high drain voltage, and poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit; (2) The traditional device structure uses a bottom P+ shielding layer to reduce the electric field at the gate trench corner. However, in order to ensure the dynamic reliability of the device, it is necessary to sacrifice part of the chip area to keep the P+ shielding layer grounded. However, this solution will sacrifice chip area, resulting in poor conduction characteristics of the device.

[0003] Therefore, it is necessary to design a new structure for the MOSFET device structure. The present invention provides a new wide bandgap semiconductor trench MOSFET device structure. Summary of the Invention

[0004] Based on the above description, the present invention provides a wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof, which can not only improve the conduction characteristics of the device, but also further improve the trade-off relationship between the device's specific on-resistance and gate oxide reliability.

[0005] The technical solution of the present invention to solve the above technical problems is as follows:

[0006] In a first aspect, the present invention provides a wide bandgap semiconductor trench MOSFET device structure, comprising: a substrate, an epitaxial layer, a first P+ shielding layer, a second P+ shielding layer, a first source P+ region, and a second source P+ region;

[0007] The epitaxial layer is grown on the substrate; the first source P+ region, the first P+ shielding layer, the second source P+ region and the second P+ shielding layer are sequentially spaced in the epitaxial layer along a horizontal direction;

[0008] A P-Bus region is fabricated between the first source P+ region and the first P+ shielding layer, and / or the second source P+ region and the second P+ shielding layer, and / or the first P+ shielding layer and the second source P+ region to achieve electrical connection between the P+ shielding layer and the source P+ region.

[0009] On the basis of the above technical solution, the present invention can also be improved as follows.

[0010] Furthermore, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer sequentially stacked on the substrate;

[0011] The first source P+ region and the second source P+ region are located in the first epitaxial layer and the second epitaxial layer, and the first P+ shielding layer and the second P+ shielding layer are located in the first epitaxial layer.

[0012] Furthermore, a P-well region, a source N+ region, a source ohmic contact region and a source electrode are sequentially formed on the epitaxial layer from bottom to top.

[0013] Furthermore, source trenches are respectively provided in the first source P+ region and the second source P+ region;

[0014] The source trench is provided through the source N+ region, the P-well region and a portion of the second epitaxial layer;

[0015] A source dielectric layer is provided on the inner wall side of the source trench, and the source trench is filled with source polysilicon;

[0016] The source polysilicon, the first source P+ region and the second source P+ region are all electrically connected to the source electrode through a source ohmic contact region at the top of the source trench.

[0017] Furthermore, the first P+ shielding layer and the second P+ shielding layer are respectively provided with gate trenches;

[0018] The gate trench is provided through the source N+ region, the P-well region, the second epitaxial layer and a portion of the first epitaxial layer;

[0019] A gate dielectric layer is provided on the inner wall side of the gate trench, and the gate trench is filled with gate polysilicon;

[0020] The gate polysilicon contacts the source electrode through the interlayer dielectric layer at the top of the gate trench.

[0021] Furthermore, the gate trench is a multi-level trench structure.

[0022] Furthermore, the wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode;

[0023] The drain electrode is arranged at the bottom of the substrate.

[0024] In a second aspect, the present invention further provides a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure as described in the first aspect, comprising:

[0025] Epitaxially grow an epitaxial layer on the substrate, then form a P-well region by ion implantation, secondary epitaxy or growth of a P-type oxide, and then form a source N+ region on the P-well region by ion implantation;

[0026] The P-Bus region is produced by ion implantation;

[0027] forming a source trench and a gate trench by dry etching;

[0028] forming a first source P+ region, a first P+ shielding layer, a second source P+ region, and a second P+ shielding layer respectively by P-type ion implantation;

[0029] The gate and source dielectric growth, gate and source polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, and drain metal deposition are sequentially performed to obtain the product.

[0030] On the basis of the above technical solution, the present invention can also be improved as follows.

[0031] Furthermore, the epitaxial growth of the epitaxial layer on the substrate specifically includes:

[0032] A first epitaxial layer and a second epitaxial layer are sequentially epitaxially grown on the substrate.

[0033] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0034] Compared with the prior art, the wide bandgap semiconductor trench MOSFET device structure and the manufacturing method thereof provided by the present invention have the following advantages:

[0035] By constructing a P-Bus region in space to keep the P+ shielding layer and the source P+ region electrically connected, the P+ shielding layer remains grounded at this time, which can improve the dynamic reliability of the device. The cell part with the P-Bus region can still conduct current, and the electron current flows inward through the channel, greatly improving the conduction characteristics of the device. At the same time, the area ratio of the two types of cells (with P-Bus region and without P-Bus region) can be controlled to further improve the compromise relationship between the specific on-resistance and gate oxide reliability of the device.

[0036] Furthermore, the above-mentioned fabrication method and corresponding structure also form an ohmic contact at the source, short-circuiting the source N+ and source P+ regions. The multi-level gate trenches and the P+ shielding layer at the bottom form a masking structure, which can reduce the gate oxide electric field strength and improve the device's gate oxide reliability. Furthermore, this method does not require additional process steps, reducing device complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the three-dimensional structure of a wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0038] Figure 2 A schematic cross-sectional view of a wide bandgap semiconductor trench MOSFET device structure at section A provided by an embodiment of the present invention;

[0039] Figure 3 A schematic cross-sectional structure diagram of a wide bandgap semiconductor trench MOSFET device structure at section B provided by an embodiment of the present invention;

[0040] Figures 4 to 10 Schematic diagram of several configurations of the P-Bus region of the wide bandgap semiconductor trench MOSFET device structure provided by the present invention;

[0041] Figure 11 A schematic diagram of a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure provided by an embodiment of the present invention;

[0042] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0043] 1. Substrate; 2. Epitaxial layer; 201. First epitaxial layer; 202. Second epitaxial layer; 3. First source P+ region; 4. First P+ shielding layer; 5. Second source P+ region; 6. Second P+ shielding layer; 7. P-Bus region; 8. P-well region; 9. Source N+ region; 10. Source ohmic contact region; 11. Source electrode; 12. Source dielectric layer; 13. Source polysilicon; 14. Gate dielectric layer; 15. Gate polysilicon; 16. Interlayer dielectric layer; 17. Drain electrode. DETAILED DESCRIPTION

[0044] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0045] It will be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other element will be oriented as "on" the other element or feature. Therefore, the exemplary terms "on the front side of" and "on the back side of" are only used to define two opposite sides. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] The present invention provides a novel wide bandgap semiconductor trench MOSFET device structure and a method for manufacturing the same. The embodiments of the present invention are further described in detail below with reference to the accompanying drawings and examples. The following examples are intended to illustrate the present invention but are not intended to limit the scope of the present invention.

[0047] First, as Figure 1 As shown, an embodiment of the present invention provides a wide bandgap semiconductor trench MOSFET device structure, including: a substrate 1, an epitaxial layer 2, a first P+ masking layer 4, a second P+ masking layer 6, a first source P+ region 3 and a second source P+ region 5.

[0048] The epitaxial layer 2 is grown on the substrate 1 ; the first source P+ region 3 , the first P+ shielding layer 4 , the second source P+ region 5 and the second P+ shielding layer 6 are sequentially formed in the epitaxial layer 2 in a horizontal direction.

[0049] A P-Bus region 7 is formed between the first source P+ region 3 and the first P+ shielding layer 4, and / or the second source P+ region 5 and the second P+ shielding layer 6, and / or the first P+ shielding layer 4 and the second source P+ region 5 to achieve electrical connection between the P+ shielding layer and the source P+ region.

[0050] Specifically, the epitaxial layer 2 includes a first epitaxial layer 201 and a second epitaxial layer 202 which are sequentially stacked on the substrate; Figure 2 As shown, the first source P+ region 3 and the second source P+ region 5 are located in the first epitaxial layer 201 and the second epitaxial layer 202 , and the first P+ shielding layer 4 and the second P+ shielding layer 6 are located in the second epitaxial layer 202 .

[0051] A P-well region 8 , a source N+ region 9 , a source ohmic contact region 10 and a source electrode 11 are sequentially formed on the epitaxial layer 2 from bottom to top.

[0052] In an optional embodiment, if Figure 1As shown, source trenches are respectively provided in the first source P+ region 3 and the second source P+ region 5 .

[0053] The source trench penetrates the source N+ region 9 , the P-well region 8 and a portion of the second epitaxial layer 202 .

[0054] A source dielectric layer 12 is provided on the inner wall side of the source trench, and the source trench is filled with source polysilicon 13 .

[0055] The source polysilicon 13 , the first source P+ region 3 and the second source P+ region 5 are all electrically connected to the source electrode through the source ohmic contact region at the top of the source trench.

[0056] Correspondingly, such as Figure 1 As shown, the first P+ shielding layer 4 and the second P+ shielding layer 6 are respectively provided with gate trenches.

[0057] The gate trench is provided through the source N+ region 9 , the P-well region 8 , the second epitaxial layer 202 and a portion of the first epitaxial layer 201 .

[0058] A gate dielectric layer 14 is provided on the inner wall of the gate trench, and the gate trench is filled with gate polysilicon 15 .

[0059] The gate polysilicon 15 contacts the source electrode 11 through the interlayer dielectric layer 16 at the top of the gate trench.

[0060] In addition, if Figure 1 As shown, the gate trench is a multi-level trench structure.

[0061] The wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode 17 ; the drain electrode 17 is disposed at the bottom of the substrate 1 .

[0062] It should be noted that the connection between the first source P+ region 3, the first P+ shielding layer 4, the second source P+ region 5 and the second P+ shielding layer 6 includes various embodiments, which are listed as follows: Figure 3 As Figure 7 Shown (only Figure 1 This can be explained by taking the cross section B in FIG. 1 as an example).

[0063] like Figure 3 As shown, the first source P+ region is electrically connected to the first P+ shielding layer and the second source P+ region and the second P+ shielding layer through the P-Bus region.

[0064] It should be noted that: Figure 2 and Figure 3As shown in the figure, schematic diagrams of the electron current paths of section A and section B are given respectively. It can be seen that the cell part of section B where the P-Bus region exists can still conduct current. The electron current flows inward through the channel and then enters section A and merges with the current of section A. Therefore, this scheme can also conduct current in section B where the P+ shielding layer is kept in a grounded state, greatly improving the conduction characteristics of the device.

[0065] like Figure 4 As shown, the first P+ shielding layer is electrically connected to the second source P+ region through the P-Bus region, that is, the P-Bus region in section B can also be on the right side of the multi-level trench gate, so that the P+ shielding layer on the right side of the bottom of the multi-level trench gate and the source P+ are connected, which can also achieve the same effect as mentioned above.

[0066] like Figure 5 As shown, P-Bus regions are made between the first source P+ region and the first P+ shielding layer, between the second source P+ region and the second P+ shielding layer, and between the first P+ shielding layer and the second source P+ region, but are staggered, that is, the P-Bus regions in section B can also be distributed on the left and right sides of the multi-level trench gate, so that part of the region connects the P+ shielding layer on the right side of the gate with the source P+, ​​and part of the region connects the P+ shielding layer on the left side of the gate with the source P+, ​​which can also achieve the same effect as mentioned above.

[0067] like Figure 6 As shown, the first source P+ region, the first P+ shielding layer, the second source P+ region and the second P+ shielding layer are all connected through the P-Bus region, that is, the P-Bus region in section B can also connect the P+ shielding layer and the source P+ at the bottom of all the multi-level trench gates, and can also achieve the same effect as mentioned above.

[0068] like Figure 7 As shown, the gate structure can be a single-stage trench or a multi-stage trench, the number of trenches is N, N≥1; the source can be a trenchless, single-stage or multi-stage trench, the number of trenches is M, M≥0; correspondingly, the cross section B can also be a combination of cross sections B-1, B-2 and B-3 with various different P-Bus areas, and various arrangements can achieve the same effect as mentioned above, realize the on-current, and greatly improve the on-characteristics of the device.

[0069] like Figure 8 As shown, since the P+ shielding layer at the bottom of the multi-level trench gate structure can well protect the gate structure and reduce the electric field at the bottom of the gate oxide, the source P+ region in section A is not required and can be all gate trenches. Section B can simultaneously retain the source P+ region and ground the P+ shielding layer, and the arrangement of the gate trench and the source trench in space can be a top view. Figure 1 , or it can be overlooking Figure 2, or other similar arrangements.

[0070] like Figure 9 As shown, there can be multiple gate trenches between the two source trenches, where K≥1, and the P-Bus region of section B connects the two source electrodes P+ and multiple P+ shielding layers in the middle, so that the P+ shielding layers remain grounded.

[0071] like Figure 10 As shown, P+ implantation is performed at a certain angle at the bottom of the gate trench to form a P+ mask layer and a P+ Halo region with a larger protection range, which can greatly reduce the electric field of the gate oxide layer.

[0072] The above examples are only some embodiments of the present invention, all of which fall within the scope of protection of this application. For other embodiments that conform to the above examples, those skilled in the art can design correspondingly based on the above examples.

[0073] The embodiment of the present invention forms a wide bandgap semiconductor trench MOSFET device structure by constructing a trench gate structure, a source N+ region, a source P+ region, a P-well region, a source electrode, and a drain electrode. By forming an ohmic contact at the source, the source N+ region and the source P+ region are short-circuited together; the multi-level gate trenches and the P+ shielding layer at the bottom form a shielding structure, which can reduce the gate oxide electric field strength and improve the gate oxide reliability of the device; by constructing a P-Bus region in space to keep the P+ shielding layer and the source P+ region electrically connected, the P+ shielding layer remains grounded at this time, which can improve the dynamic reliability of the device; Figure 2 and Figure 3 As shown in the figure, schematic diagrams of the electron current paths in sections A and B are provided, respectively. It can be seen that the cell portion of section B, where the P-Bus region is present, can still conduct current. The electron current flows inward through the channel and then enters section A, where it merges with the current in section A. In other words, the cell portion of section B can still conduct current. Therefore, the embodiments of the present invention greatly improve the conduction characteristics of the device. At the same time, by controlling the area ratio of the cells in sections A and B, the trade-off between the device's specific on-resistance and gate oxide reliability can be further improved.

[0074] In a second aspect, the present invention also provides a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure (using cross sections A and B as examples for illustration), see Figure 11 As shown, the operation is as follows:

[0075] Step S1: (cross section A and cross section B) growing a first N-epitaxial layer on a wide bandgap semiconductor material (SiC / GaN / Ga2O3 / C / AlN, etc.) substrate.

[0076] Step S2: (cross section A and cross section B) growing a second N-epitaxial layer on the first N-epitaxial layer.

[0077] Step S3: (cross section A and cross section B) forming a P-well region by ion implantation, secondary epitaxy, growing a P-type oxide, etc.

[0078] Step S4: (cross section A and cross section B) forming a source N+ region by ion implantation.

[0079] Step S5: (Cross-section B) Forming a P-Bus region by ion implantation.

[0080] Step S6: (Section A and Section B) Dry etching to form source trenches and first-level gate trenches.

[0081] Step S7: (Section A and Section B) dry etching to form a second-level gate trench.

[0082] Step S8: (cross section A and cross section B) simultaneously forming a source P+ region and a P+ masking layer by P-type ion implantation.

[0083] Step S9: (Section A and Section B) Gate and source dielectric layer growth, gate and source polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, drain metal deposition.

[0084] Since this manufacturing method is used to manufacture a wide bandgap semiconductor trench MOSFET device structure, the beneficial effects of the wide bandgap semiconductor trench MOSFET device structure are also applicable to this manufacturing method. For its beneficial effects, please refer to the above description of the effects and will not be repeated here.

[0085] Throughout this specification, reference to terms such as "specific examples" or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and integrate different embodiments or examples, and features of different embodiments or examples, described in this specification, unless otherwise mutually incompatible.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A wide bandgap semiconductor trench MOSFET device structure, characterized in that: include: A substrate, an epitaxial layer, a first P+ shielding layer, a second P+ shielding layer, a first source P+ region, and a second source P+ region; The epitaxial layer is grown on the substrate; the first source P+ region, the first P+ shielding layer, the second source P+ region and the second P+ shielding layer are sequentially spaced in the epitaxial layer along a horizontal direction; forming a P-Bus region between the first source P+ region and the first P+ shielding layer, and / or between the second source P+ region and the second P+ shielding layer, and / or between the first P+ shielding layer and the second source P+ region, so as to achieve electrical connection between the P+ shielding layer and the source P+ region; The epitaxial layer is provided with a P-well region, a source N+ region, a source ohmic contact region and a source electrode in sequence from bottom to top; The epitaxial layer includes a first epitaxial layer and a second epitaxial layer sequentially stacked on the substrate; The first source P+ region and the second source P+ region are located in the first epitaxial layer and the second epitaxial layer, and the first P+ shielding layer and the second P+ shielding layer are located in the first epitaxial layer; The first P+ shielding layer and the second P+ shielding layer are respectively wrapped with gate trenches; The gate trench is provided through the source N+ region, the P-well region, the second epitaxial layer and a portion of the first epitaxial layer; A gate dielectric layer is provided on the inner wall side of the gate trench, and the gate trench is filled with gate polysilicon; The gate polysilicon contacts the source electrode through the interlayer dielectric layer at the top of the gate trench.

2. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: Source trenches are respectively provided in the first source P+ region and the second source P+ region; The source trench is provided through the source N+ region, the P-well region and a portion of the second epitaxial layer; A source dielectric layer is provided on the inner wall side of the source trench, and the source trench is filled with source polysilicon; The source polysilicon, the first source P+ region and the second source P+ region are all in contact with the source electrode through a source ohmic contact region at the top of the source trench.

3. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The gate trench is a multi-level trench structure.

4. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode; The drain electrode is arranged at the bottom of the substrate.

5. A method for manufacturing a wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 4, characterized in that: include: Epitaxially grow an epitaxial layer on the substrate, then form a P-well region by ion implantation, secondary epitaxy or growth of a P-type oxide, and then form a source N+ region on the P-well region by ion implantation; The P-Bus region is produced by ion implantation; forming a source trench and a gate trench by dry etching; forming a first source P+ region, a first P+ shielding layer, a second source P+ region, and a second P+ shielding layer respectively by P-type ion implantation; The gate and source dielectric growth, gate and source polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, and drain metal deposition are sequentially performed to obtain the product.

6. The manufacturing method according to claim 5, characterized in that: The epitaxial growth of the epitaxial layer on the substrate specifically includes: A first epitaxial layer and a second epitaxial layer are sequentially epitaxially grown on the substrate.

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