Method for manufacturing a back contact battery

Abstract

The present invention belongs to the technical field of back contact battery preparation, and specifically relates to a method for preparing a back contact battery. The silicon nitride in the anti-reflection layer is formed by a plasma enhanced chemical vapor deposition process, and the conditions include: the spacing L between the two electrode plates used for deposition is 15-50 mm, silane, ammonia, and nitrogen are introduced with a flow ratio of 1: (0.1-30): (20-100), L and chamber pressure P are 1: (2.0-23.3), and the deposition power density is 0.6-2.8 kW / m 2 ; The deposition temperature is 200-300°C, and the ratio of the deposition temperature to the deposition time is 1:(0.3-1.5). The present invention can achieve uniform growth of silicon nitride in the anti-reflection layer at low temperature, and can effectively avoid damage to the front and back amorphous silicon or microcrystalline film layers, maintain a high passivation level, thereby facilitating the improvement of the performance of the back contact battery, and has wide applicability.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact battery preparation, and in particular relates to a method for preparing a back contact battery. Background Art

[0002] At present, the back side of the back contact battery is provided with a first semiconductor layer and a second semiconductor layer, and the front side is generally provided with a passivation layer and an anti-reflection layer, wherein the second semiconductor layer includes an amorphous silicon or microcrystalline silicon film layer, the passivation layer can be an amorphous silicon or microcrystalline silicon film layer, or can be silicon oxide, etc., and the anti-reflection layer is generally silicon nitride, silicon oxynitride, a stack of silicon nitride and silicon oxynitride, a stack of silicon nitride and silicon oxide, etc.

[0003] Generally, the deposition of silicon nitride in the anti-reflection layer requires a relatively high temperature (300-550°C), but it is not applicable to semiconductor films with amorphous silicon or microcrystalline silicon on the front and back sides, and is prone to thermal damage to the semiconductor films of amorphous silicon or microcrystalline silicon on the front and back sides. Alternatively, in another method, the deposition temperature of silicon nitride is lowered to 25-300°C, and the ICP-CVD inductively coupled plasma deposition method is used, which uses a magnetic field to accelerate electron bombardment to quickly form plasma deposition, but the deposition process of silicon nitride is prone to sputtering damage to the silicon film, and the coating time is too long, usually 10-60 minutes. The accumulated coating temperature also damages the semiconductor films such as amorphous silicon or microcrystalline silicon on the front and back sides. The ICP-CVD deposition method is also rarely used in the photovoltaic field.

[0004] The above two situations are not applicable to the production of back-contact cells containing semiconductor film layers such as amorphous silicon or microcrystalline silicon, and are even less applicable to the production process of large-scale back-contact cells.

[0005] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0006] The purpose of the present invention is to overcome the defect of the prior art that the deposition of silicon nitride in the anti-reflection layer will cause thermal damage to the amorphous silicon or microcrystalline silicon on the front and back sides, and is not suitable for the production of back-contact cells containing semiconductor film layers such as amorphous silicon or microcrystalline silicon. A method for producing a back-contact cell is provided, which can achieve uniform growth of silicon nitride in the anti-reflection layer at a low temperature of 200-300°C, has a suitably high deposition rate, and can effectively avoid damage (including thermal damage or sputtering damage) to the amorphous silicon or microcrystalline film layers on the front and back sides, maintain a high passivation level, and thus is beneficial to improving the performance of the back-contact cell. Moreover, the deposition method has wide applicability and is suitable for all back-contact cell structures.

[0007] In order to achieve the above-mentioned purpose, the present invention provides a method for manufacturing a back-contact battery, comprising: forming a first semiconductor layer and a second semiconductor layer on the back side of a silicon wafer in sequence, and then forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer in sequence, wherein the anti-reflection layer comprises silicon nitride, and the silicon nitride is formed by a plasma enhanced chemical vapor deposition (PECVD) process, and the conditions of the plasma enhanced chemical vapor deposition process include: controlling the spacing L between two electrode plates used for deposition to be 15-50 mm, introducing silane, ammonia and nitrogen, and controlling the volume flow ratio of silane: ammonia: nitrogen to be 1: (0.1-30): (20-100), and controlling the ratio of the value of the spacing L between the two electrode plates in mm to the value of the pressure P in the deposition chamber in Pa to be 1: (2.0-23.3), and the power density of the deposition is 0.6-2.8 kW / m 2 , power density refers to the deposited glow power / coating area; and the deposition temperature is controlled to be 200-300°C, and the ratio of the deposition temperature in °C to the deposition time in seconds is 1:(0.3-1.5).

[0008] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process further include: controlling the ratio of the deposition temperature to the deposition temperature of the second semiconductor layer to be 1:(0.5-1.25).

[0009] In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-250°C.

[0010] In some specific preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-200°C, and the deposition temperature of the silicon nitride in the anti-reflection layer is controlled to be 200-250°C.

[0011] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: controlling the flow rate of nitrogen to be 5000-30000 sccm.

[0012] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process further include: controlling the flow rate of silane to 100-1000 sccm and the flow rate of ammonia to 100-3000 sccm.

[0013] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: P is 50-350Pa.

[0014] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: a deposition time of 100-300 seconds.

[0015] In some preferred embodiments of the present invention, the deposition rate of silicon nitride is 0.5-2 nm / s.

[0016] In some preferred embodiments of the present invention, the refractive index of the silicon nitride is between 1.90 and 2.20.

[0017] In some preferred embodiments of the present invention, the thickness of the silicon nitride is 50-180 nm.

[0018] In some preferred embodiments of the present invention, the anti-reflection layer further comprises silicon oxide, and silicon nitride is located between the passivation layer and the silicon oxide. The thickness of the silicon nitride is 50-100 nm, and the thickness of the silicon oxide is 90-120 nm.

[0019] In some preferred embodiments of the present invention, the passivation layer comprises one or more combinations of an amorphous silicon layer, microcrystalline silicon, polycrystalline silicon, a silicon oxide layer, and an aluminum oxide layer.

[0020] In some preferred embodiments of the present invention, the thickness of the passivation layer is 5-12 nm.

[0021] In some preferred embodiments of the present invention, the first semiconductor layer includes a tunneling silicon oxide layer and a first doped polysilicon layer, the second semiconductor layer includes an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type.

[0022] In some preferred embodiments of the present invention, the first semiconductor layer and the second semiconductor layer are sequentially formed on the back side of the silicon wafer, and then a passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, and the process includes:

[0023] S1, provide silicon wafers;

[0024] S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0025] S3, performing a first etching opening on the first semiconductor layer and the corresponding mask layer on the back surface obtained in S2 to form second semiconductor opening regions arranged at intervals;

[0026] S4, then performing texturing and cleaning on the silicon wafer structure obtained in S3, and during the final cleaning process, it is selected whether to remove the mask layer as required;

[0027] S5, forming a second semiconductor layer on the back surface obtained in S4;

[0028] S6. Forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer obtained in S5.

[0029] In some preferred embodiments of the present invention, after forming the passivation layer and the anti-reflection layer, the method for manufacturing the back contact cell further comprises:

[0030] S7, performing a second etching opening on the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is alternately arranged with the second semiconductor opening region;

[0031] S8, depositing a conductive film layer on the back surface obtained in S7;

[0032] S9, performing a third etching opening on the conductive film layer on the back obtained in S8 to form an insulating groove between the second semiconductor opening region and the first semiconductor opening region;

[0033] S10, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S9.

[0034] Beneficial effects:

[0035] The present invention, through the above technical scheme, especially using the conventional PECVD process, combined with controlling the conditions of a specific plasma enhanced chemical vapor deposition process (such as a suitable gas ratio, an appropriate ratio of deposition temperature to deposition time, matching a suitable power density and a ratio of gas pressure to spacing L), can achieve uniform growth of silicon nitride in the anti-reflection layer at a low temperature of 200-300°C, with a suitably high deposition rate, and can effectively avoid damage to the front and back amorphous silicon or microcrystalline film layers (including thermal damage or sputtering damage), which is beneficial for the battery to maintain a high passivation level. Moreover, the deposition method has a wide range of applicability and is suitable for all back contact battery structures, thereby helping to improve the performance of the back contact battery, especially a higher short-circuit current and a high battery conversion efficiency.

[0036] Among them, the present invention adopts the introduction of silane, ammonia, and nitrogen, and especially adds nitrogen. Nitrogen is used as both a doping gas and a diluent gas. With a suitable gas flow ratio, it can take into account the refractive index and deposition rate of the film layer, which is beneficial to control the deposition rate and the refractive index in the coating process at 1.9-2.2, thereby improving the compactness and corrosion resistance of the silicon nitride film, and ensuring that the silicon nitride film has a better optical anti-reflection effect. At the same time, nitrogen is a cheap gas, which is more in line with the requirements of mass production with high cost performance. Under the same conditions, if nitrogen is not introduced, the deposition rate is too fast, the compactness of the film will be seriously reduced, and the refractive index will be difficult to drop to between 1.9-2.2.

[0037] The present invention also controls the appropriate ratio of deposition temperature to deposition time, which can further avoid the risk of thermal damage to the amorphous silicon film layer due to the additional increase in coating temperature caused by the glow plasma during the deposition process (for example, if the deposition temperature is set to 200°C, the glow temperature will continue to rise to 210°C or 220°C during the deposition process). If the glow time is too long, the greater the temperature rise will be, resulting in the risk of thermal damage to the amorphous silicon film layer caused by the high temperature.

[0038] The present invention also cooperates with controlling the ratio of the appropriate gas pressure and the distance L between the two electrode plates, which is conducive to the sufficient dissociation of the reaction gas in the chamber, and the dissociated ion groups gradually adhere to the silicon wafer to form a film, thereby facilitating the uniform formation of silicon nitride. Under the same conditions, if the ratio is too large, it is easy to cause the film quality to deteriorate, such as pinholes, etc. If the ratio is too small, the gas residence time is too short, the dissociation is insufficient, and the uniformity will decrease.

[0039] The present invention also matches the appropriate ratio of power density and gas pressure to the distance L, which can synergistically avoid sputtering damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 The figure is a process flow chart of the method for manufacturing the back contact battery of the present invention.

[0042] Figure 2 A schematic structural diagram of a back-contact battery obtained by a method for manufacturing a back-contact battery according to a specific embodiment of the present invention.

[0043] Description of Reference Numerals

[0044] 1. Silicon wafer, 2. First semiconductor layer, 2.1. Tunneling silicon oxide layer, 2.2. First doped polysilicon layer, 3. Mask layer, 4. Intrinsic hydrogenated amorphous silicon layer, 5. Second doped amorphous silicon layer, 6. Passivation layer, 7. Anti-reflection layer, 8. Conductive film layer, 9. Metal electrode. DETAILED DESCRIPTION

[0045] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0047] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0048] In the present invention, the front side refers to the light-receiving side.

[0049] The invention provides a method for manufacturing a back contact battery, comprising: forming a first semiconductor layer and a second semiconductor layer on the back of a silicon wafer in sequence, and then forming a passivation layer and an anti-reflection layer on the front of the silicon wafer in sequence, wherein the anti-reflection layer comprises silicon nitride, and the silicon nitride in the anti-reflection layer is formed by a plasma enhanced chemical vapor deposition process, and the conditions of the plasma enhanced chemical vapor deposition process comprise: controlling the spacing L between two electrode plates used for deposition to be 15-50 mm, introducing silane, ammonia and nitrogen, and controlling the volume flow ratio of silane: ammonia: nitrogen to be 1: (0.1-30): (20-100), and controlling the ratio of the value of the spacing L between the two electrode plates in mm to the value of the pressure P in the chamber where the deposition is located in Pa to be 1: (2.0-23.3), and the power density of the deposition to be 0.6-2.8 kW / m 2 , power density refers to the deposited glow power / coating area; and the deposition temperature is controlled to be 200-300°C, and the ratio of the deposition temperature in °C to the deposition time in seconds is 1:(0.3-1.5).

[0050] It is understandable that the plasma enhanced chemical vapor deposition equipment is provided with two electrode plates, namely an upper electrode plate and a lower electrode plate, and the polarities of the two electrode plates are different. In the present invention, the spacing L between the two electrode plates refers to the distance between the upper electrode plate and the lower electrode plate.

[0051] In the present invention, the power density can be adjusted according to the coating area by adjusting the glow power of the glow emitted by the plasma enhanced chemical vapor deposition.

[0052] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: controlling the ratio of the deposition temperature to the deposition temperature of the second semiconductor layer to be 1: (0.5-1.25), preferably 1: (0.80-0.85). In the preferred embodiment of the present invention, controlling the ratio of the deposition temperature of the silicon nitride in the anti-reflection layer to the deposition temperature of the second semiconductor layer to be within a suitable preferred range is conducive to maintaining the passivation effect of the second semiconductor layer to the greatest extent before and after the deposition of the silicon nitride in the anti-reflection layer, and utilizing the hydrogen effect of silicon nitride to generate passivation gain, further improving the effect of the minority carrier life of the battery, and effectively reducing or avoiding the possibility of thermal damage to the second semiconductor layer during the deposition of silicon nitride.

[0053] In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-250°C, preferably 150-210°C.

[0054] In some specific preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-200° C., preferably 150-195° C., and the deposition temperature of the silicon nitride in the anti-reflection layer is controlled to be 200-250° C., more preferably 200-240° C., and further preferably 210-235° C. In this preferred embodiment, the deposition temperature of the second semiconductor layer matches the deposition temperature of the silicon nitride in the anti-reflection layer, which is more conducive to effectively maintaining or even increasing the passivation effect of the second semiconductor layer and improving the minority carrier life of the battery.

[0055] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: controlling the flow rate of nitrogen to be 5000-30000 sccm. Using nitrogen in a suitable flow range is more conducive to controlling the deposition rate in a suitable high range and improving the properties of the film layer.

[0056] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: controlling the flow rate of silane to 100-1000 sccm and the flow rate of ammonia to 100-3000 sccm. Using silane and ammonia in a suitable flow range is more conducive to controlling a suitable refractive index.

[0057] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: P is 50-350Pa.

[0058] In some preferred embodiments of the present invention, the conditions of the plasma enhanced chemical vapor deposition process also include: a deposition time of 100-300 seconds.

[0059] In some preferred embodiments of the present invention, the deposition rate of silicon nitride is 0.5-2 nm / s, preferably 0.5-1.5 nm / s. A suitable deposition rate of silicon nitride is more conducive to controlling the density and uniformity of the film layer.

[0060] In some preferred embodiments of the present invention, the refractive index of the silicon nitride is 1.90-2.20. Silicon nitride with a suitable refractive index can ensure that the film layer has better compactness and uniformity while taking into account better anti-reflection effect.

[0061] In some preferred embodiments of the present invention, the thickness of the silicon nitride is 50-180 nm. At this thickness, the silicon nitride can be a single layer as an anti-reflection layer, or can be combined with other film layers to form an anti-reflection layer.

[0062] In some specific embodiments, the anti-reflection layer is silicon nitride, and the thickness of the silicon nitride is 50-180 nm.

[0063] In some other preferred embodiments of the present invention, the anti-reflection layer further comprises silicon oxide, silicon nitride is located between the passivation layer and the silicon oxide, the thickness of the silicon nitride is 50-100 nm, and the thickness of the silicon oxide is 90-120 nm.

[0064] The anti-reflection layer deposition process of the present invention is applicable to all types or combinations of passivation layers. In some preferred embodiments of the present invention, the passivation layer comprises one or more combinations of an amorphous silicon layer, microcrystalline silicon, polycrystalline silicon, a silicon oxide layer, and an aluminum oxide layer. The anti-reflection layer deposition process of the present invention can prevent the passivation layer of the amorphous silicon layer from being thermally damaged.

[0065] In some preferred embodiments of the present invention, the thickness of the passivation layer is 5-12 nm.

[0066] In some preferred embodiments of the present invention, the first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type. This preferred solution adopts a combined passivation structure and cooperates with the silicon nitride preparation process of the anti-reflection layer, which can take into account both passivation and optical effects, and is more conducive to improving battery performance.

[0067] Furthermore, the second doped silicon layer may be doped amorphous silicon or doped microcrystalline silicon.

[0068] The thickness of the first semiconductor layer and the second semiconductor layer can refer to the range in the prior art. Further preferably, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration is 10 20cm -3 -10 21 cm -3 The thickness of the intrinsic hydrogenated amorphous silicon layer is 4-8nm, the thickness of the second doped silicon layer is 6-15nm, preferably 6-12nm, and the effective doping concentration is 10 19 cm -3 -5×10 20 cm -3 .

[0069] In some preferred embodiments of the present invention, the first semiconductor layer and the second semiconductor layer are sequentially formed on the back side of the silicon wafer, and then a passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, and the process includes:

[0070] S1, provide silicon wafers;

[0071] S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0072] S3, performing a first etching opening on the first semiconductor layer and the corresponding mask layer on the back surface obtained in S2 to form second semiconductor opening regions arranged at intervals;

[0073] S4, then performing texturing and cleaning on the silicon wafer structure obtained in S3, and during the final cleaning process, it is selected whether to remove the mask layer as required;

[0074] S5, forming a second semiconductor layer on the back surface obtained in S4;

[0075] S6. Forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer obtained in S5.

[0076] The silicon wafer in S1 may be a silicon wafer that has been double-sided polished and optionally cleaned. The silicon wafer is preferably an N-type single crystal silicon wafer. The silicon wafer may be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0077] The type and thickness of the mask layer in S2 can refer to the prior art, for example, the type can be at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, preferably silicon nitride. The thickness of the mask layer can be, for example, 40-90 nm.

[0078] The formation of the first semiconductor layer and the mask layer in S2 can refer to the method of the prior art, preferably using a tubular polysilicon deposition furnace to sequentially deposit and high-temperature anneal, and the deposition temperature is 400-500° C. Further, the conditions of high-temperature annealing may include, for example: introducing nitrogen gas, the flow rate of nitrogen gas is 5000-15000sccm, the annealing temperature is 850-950° C., the pressure is 1000-10000Pa, and the time is 40-60min. Exemplarily, the first semiconductor layer includes a tunneling silicon oxide layer and a first doped polysilicon layer, and the deposition conditions of the tunneling silicon oxide layer include: controlling the flow rate of the laughing gas to be 8000-12000sccm, the pressure to be 100-200Pa, the power to be 3-20kW, and the time to be 20-100s; the deposition conditions of the first doped polysilicon layer include: controlling the flow rate of the silane to be 1000-3000sccm, the flow rate of the mixed gas of the hydrogen carrying the doping element gas source to be 1000-4000sccm, the flow rate of the hydrogen to be 7000-9000sccm, the pressure to be 200-800Pa, the power to be 5-20kW, and the time to be 800-1300s. Further preferably, when the doping element gas source is a phosphorus source, the flow rate of the mixed gas is 1000-2500 sccm, and the pressure is controlled to be 400-500 Pa; when the doping element gas source is a boron source, the flow rate of the mixed gas is 2000-4000 sccm, and the pressure is controlled to be 200-800 Pa. Exemplarily, the deposition conditions when the mask layer is silicon nitride include: the flow rate of silane is 1000-2000 sccm, the flow rate of ammonia is 2000-5000 sccm, the pressure is 200-300 Pa, the power is 3-20 kW, and the time is 300-800 s.

[0079] The conditions for the texturing cleaning described in S4 can be carried out with reference to the prior art. For example, the texturing solution used is a mixture of alkali (such as potassium hydroxide or sodium hydroxide), texturing additives and water, wherein the mass percentage of the alkali is 1%-5%, and the mass percentage of the texturing additive is 0.5%-1%. Further, the texturing conditions may include: the texturing time is 8-30min, and the texturing temperature is 75℃-85℃. The texturing additives can be obtained commercially. The final cleaning conditions in the texturing cleaning can be adjusted according to whether the mask layer needs to be removed. For example, when the mask layer needs to be removed, the final cleaning conditions include: the cleaning solution used for the final cleaning is an acid solution such as HF, the mass percentage of HF in the HF acid solution is 0.5%-5%, the mass percentage of deionized water contained is 95%-99.5%, the processing temperature is 20℃-30℃, and the removal time is 60-300s. When there is no need to remove the mask layer, the final cleaning conditions include: the cleaning solution used for the final cleaning is an HF acid solution, wherein the mass percentage of HF is 0.5%-3%, the mass percentage of deionized water contained is 97%-99.5%, the processing temperature is 20°C-30°C, and the removal time is 30-120s.

[0080] The second semiconductor layer in S5 may be formed by referring to the method in the prior art, for example, by plate-type CVD.

[0081] The formation of the passivation layer in S6 may refer to the method in the prior art, which will not be described in detail here.

[0082] In some preferred embodiments of the present invention, after forming the passivation layer and the anti-reflection layer, the method for manufacturing the back-contact battery further includes: S7, performing a second etching opening on the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area that is alternately arranged with the second semiconductor opening area.

[0083] The first etching opening and the second etching opening of the present invention can be independently formed by laser or mask etching, as long as the corresponding semiconductor opening area can be formed. The laser can be ultraviolet or green laser, and the pulse width of the laser is preferably less than 10ns.

[0084] The widths of the first semiconductor opening region and the second semiconductor opening region can be determined according to the range of the prior art and actual needs. For example, the width of the second semiconductor opening region can be 400-800 μm, and the width of the first semiconductor opening region can be 100-250 μm.

[0085] In some preferred embodiments of the present invention, the method for manufacturing the back-contact battery further comprises: S8, depositing a conductive film layer on the back side obtained in S7.

[0086] S8 The formation of the conductive film layer and its thickness and type can refer to the methods of the prior art, for example, physical vapor deposition technology (PVD) or activated plasma deposition technology (RPD) can be used. Exemplarily, the thickness of the conductive film layer is 40-80nm, and the material of the conductive film layer can be an indium oxide-based film doped with at least one of tin, tungsten, titanium, and zinc, or an aluminum and / or boron-doped zinc oxide-based film.

[0087] In some preferred embodiments of the present invention, the method for manufacturing a back-contact battery further includes: S9, performing a third etching opening on the conductive film layer on the back side obtained in S8 to form an insulating groove between the second semiconductor opening region and the first semiconductor opening region.

[0088] S9 The third etching of the opening can refer to the existing method, for example, mask etching or laser etching can be used. After etching, the resistance between the first semiconductor opening area and the second semiconductor opening area is greater than 1 kΩ. The width of the insulating groove can be, for example, 20-100 μm.

[0089] In some preferred embodiments of the present invention, the method for manufacturing the back contact battery further includes: S10, forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S9, respectively.

[0090] The formation of S10 metal electrode may refer to the method in the prior art, for example, the screen printing technology may be used.

[0091] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0092] Example 1

[0093] A method for manufacturing a back contact battery, such as Figure 1 As shown, the details are as follows:

[0094] S1, double-sided polishing of silicon wafer 1:

[0095] The N-type single crystal silicon wafer 1 is double-sided polished and cleaned, and the silicon wafer 1 is a Czochralski single crystal silicon wafer.

[0096] S2, forming a first semiconductor layer 2 and a mask layer 3 on the back side of the silicon wafer 1:

[0097] The first semiconductor layer 2 comprises a tunneling silicon oxide layer 2.1 and an N-type first doped polysilicon layer 2.2. The mask layer 3 is silicon nitride. The tunneling silicon oxide layer 2.1 has a thickness of 1.5 nm, the first doped polysilicon layer 2.2 has a thickness of 90 nm, and an effective doping concentration of 3×10 20 cm -3, the thickness of the first mask layer 3 is 60nm. The tunneling silicon oxide layer 2.1, the first doped polysilicon layer 2.2, and the mask layer 3 are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace, and the deposition temperature is 450°C. When depositing the tunneling oxide layer 2.1, the flow rate of laughing gas is 8000sccm, the pressure is 150Pa, the power supply is 10kW, and the time is 50s. When depositing the first doped polysilicon layer 2.2, the flow rate of silane is 2000sccm, the flow rate of hydrogen carrying phosphine (the flow rate ratio is 2% PH3 / 98% H2) is 2000sccm, the flow rate of hydrogen is 8000sccm, the pressure is 400Pa, the power supply is 6kW, and the time is 1000s. When depositing the silicon nitride mask layer 3, the flow rate of silane is 1500sccm, the flow rate of ammonia is 3000sccm, the pressure is 250Pa, the power is 10kW, and the time is 500s. The high temperature annealing requires the introduction of nitrogen, the flow rate of nitrogen is 10000sccm, the annealing temperature is 850°C, the pressure is 5000Pa, and the time is 50min.

[0098] S3, etching openings on the back side of the silicon wafer 1 for the first time to form second semiconductor opening regions arranged at intervals;

[0099] The first etching opening is performed by laser, as long as the first semiconductor layer 2 and the corresponding mask layer 3 covering it can be removed to form the second semiconductor opening area. The laser is ultraviolet laser with a pulse width of 5ps. The width of the formed second semiconductor opening area is 500μm.

[0100] S4, performing texturing and cleaning on the front and back sides of the silicon wafer 1;

[0101] The corresponding opening areas on the front and back of the silicon wafer 1 are cleaned by texturing, and the texturing liquid is a mixture of potassium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide is 2%, and the mass percentage of the texturing additive is 0.5%. The texturing time is 10 minutes, and the texturing temperature is 80°C.

[0102] S5, forming a second semiconductor layer on the back side of the silicon wafer 1;

[0103] The second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer 4 and a P-type second doped amorphous silicon layer 5. The second semiconductor layer is formed by plate-type CVD. The intrinsic hydrogenated amorphous silicon layer 4 has a thickness of 5 nm, the second doped amorphous silicon layer 5 has a thickness of 10 nm, and an effective doping concentration of 4.8×10 19 cm -3 , the deposition temperature of the second semiconductor layer is 190°C.

[0104] S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer 1;

[0105] The passivation layer is an amorphous silicon passivation layer with a thickness of 10.5 nm.

[0106] The anti-reflection layer is silicon nitride; the silicon nitride is deposited by PECVD, the deposition temperature is 230°C, the gases introduced during deposition are silane, ammonia and nitrogen, the flow rate of silane is 500sccm, the flow rate of ammonia is 1000sccm, and the flow rate of nitrogen is 25000sccm; the flow ratio of silane: ammonia: nitrogen gas is 1:2:50; the spacing L between the two electrode plates deposited (i.e., the distance between the upper electrode plate and the lower electrode plate) is 35mm, the deposition chamber pressure P is 100Pa, the numerical ratio of the spacing L between the two electrode plates to the deposition chamber pressure P is 1:2.86, and the power density of the deposition (i.e., the deposition glow power / coating area) is 1.5kW / m 2 The coating area of ​​silicon nitride is 3.2m 2 , the deposition time is 130s, the ratio of deposition temperature to deposition time is 1:0.57; the deposition rate of silicon nitride film is 1nm / s, the refractive index is 2.05, and the thickness is 86nm; the ratio of deposition temperature of silicon nitride to deposition temperature of the second semiconductor layer is 1:0.83;

[0107] Through the above appropriate gas ratio, appropriate deposition temperature and deposition time ratio, matching the appropriate power density and the ratio of gas pressure to spacing L, the deposited silicon nitride anti-reflection layer can grow the film layer uniformly at low temperature, avoiding thermal damage or sputtering damage to the amorphous silicon film layer on the front and back sides, which is beneficial to improving the performance of the battery.

[0108] S7, etching an opening on the back side of the silicon wafer 1 for the second time to form a first semiconductor opening region;

[0109] The second etching opening is performed by laser, as long as the second semiconductor layer above the first semiconductor layer can be etched away to form the first semiconductor opening area. The laser is ultraviolet laser with a pulse width of 5ps. The width of the formed first semiconductor opening area is 200μm.

[0110] S8, depositing a conductive film layer 8 on the back side of the silicon wafer 1;

[0111] A transparent conductive film layer 8 is deposited on the back of the silicon wafer 1 by physical vapor deposition (PVD). The transparent conductive film layer 8 has a thickness of 50 nm and is made of a tin-doped indium oxide-based film.

[0112] S9, etching an opening on the back side of the silicon wafer 1 for the third time to form an insulating groove:

[0113] By using mask etching, an opening is etched on the back of the silicon wafer 1 to form an insulating groove between the first semiconductor opening area and the second semiconductor opening area. The width of the insulating groove is 20 μm. After etching, the resistance between the first semiconductor opening area and the second semiconductor opening area is greater than 1 kΩ.

[0114] S10, using screen printing technology, metal electrodes 9 are formed at the first semiconductor opening area and the second semiconductor opening area on the back of the silicon wafer 1. The obtained back contact battery is as follows Figure 2 shown.

[0115] Example 2

[0116] The method of Example 1 is referred to, except that during the deposition of silicon nitride in the anti-reflection layer, the flow rate of nitrogen is adjusted to 10000 sccm, so that the volume flow ratio of silane to nitrogen is 1:20. The deposition rate of silicon nitride obtained by this method is 1.4 nm / s and the refractive index is 2.16.

[0117] Example 3

[0118] The method of Example 1 is used, except that during the deposition of silicon nitride in the anti-reflection layer, the spacing L between the two electrode plates used for deposition is 45 mm, and the ratio of the value of L in mm to the value of P in Pa is calculated to be 1:2.22. The deposition rate of silicon nitride obtained by this method is 0.8 nm / s and the refractive index is 1.91.

[0119] Example 4

[0120] The method of Example 1 is referred to, except that during the deposition of silicon nitride in the anti-reflection layer, the deposition gas pressure P is adjusted to 180 Pa, so that the ratio of the value of L in mm to the value of P in Pa is 1:5.14. The deposition rate of silicon nitride obtained by this method is 1.56 nm / s and the refractive index is 2.2.

[0121] Example 5

[0122] The method of Example 1 is followed, except that during the deposition of silicon nitride in the anti-reflection layer, the deposition power density is adjusted to 0.85 kW / m 2 The deposition rate of silicon nitride obtained by this method is 0.76 nm / s and the refractive index is 2.19.

[0123] Example 6

[0124] The method of Example 1 is referred to, except that during the deposition of silicon nitride in the anti-reflection layer, the deposition time is adjusted to 150 seconds, and the ratio of the value of the deposition temperature in ° C to the value of the deposition time in seconds is 1:0.65. The deposition rate of silicon nitride obtained by this method is 1 nm / s and the refractive index is 2.1.

[0125] Example 7

[0126] The method of Example 1 is referred to, except that the deposition temperature of the second semiconductor layer is adjusted to 200°C, so that the ratio of the deposition temperature of the silicon nitride in the anti-reflection layer to the deposition temperature of the second semiconductor layer is 1:0.87, and other conditions remain unchanged. The second semiconductor layer obtained in this example: the intrinsic hydrogenated amorphous silicon layer has a thickness of 8nm, the second doped amorphous silicon layer has a thickness of 15nm, and the effective doping concentration is 5.3×10 19 cm -3 .

[0127] Example 8

[0128] The method of Example 1 is referred to, except that the deposition temperature of silicon nitride in the anti-reflection layer is adjusted to 240°C, so that the ratio of the deposition temperature of silicon nitride in the anti-reflection layer to the deposition temperature of the second semiconductor layer is 1:0.79, and other conditions remain unchanged. The deposition rate of silicon nitride obtained by this method is 1.38 nm / s and the refractive index is 2.14.

[0129] Example 9

[0130] The method of Example 1 is referred to, except that the deposition temperature of silicon nitride in the anti-reflection layer is adjusted to 250°C, so that the ratio of the deposition temperature of silicon nitride in the anti-reflection layer to the deposition temperature of the second semiconductor layer is 1:0.76, and other conditions remain unchanged. The deposition rate of silicon nitride obtained by this method is 1.41 nm / s and the refractive index is 2.17.

[0131] Example 10

[0132] The method of Example 1 is referred to, except that during the deposition of silicon nitride in the anti-reflection layer, the deposition rate is adjusted to 1.9 nm / s, and the parameter that needs to be adjusted to meet the deposition rate is to increase the flow rate of silane to 950 sccm.

[0133] Embodiment 11

[0134] The method of Example 1 is referred to, except that the passivation layer on the front side of the silicon wafer is a silicon dioxide layer with a thickness of 5 nm.

[0135] Example 12

[0136] The method of Example 1 is followed, except that the first semiconductor layer is an intrinsic hydrogenated amorphous silicon layer (with a thickness of 5 nm) and a first doped amorphous silicon layer (with a thickness of 7 nm and an effective doping concentration of 2.5×10 20 cm -3 ).

[0137] Example 13

[0138] The method of Example 1 is referred to, except that the anti-reflection layer is composed of a stack of silicon nitride and silicon dioxide, and silicon dioxide is deposited on the back of the silicon nitride, with a thickness of 120 nm.

[0139] Comparative Example 1

[0140] The method of Example 1 is used as reference, except that, during the deposition of silicon nitride in the anti-reflection layer, nitrogen is not introduced, but only silane and ammonia are introduced, and other conditions remain unchanged. The deposition rate of silicon nitride obtained by this method is 2.65 nm / s and the refractive index is 2.45.

[0141] Comparative Example 2

[0142] The method of Example 1 is referred to, except that during the deposition of silicon nitride in the anti-reflection layer, the flow rate of nitrogen is adjusted to 5000 sccm, so that the volume flow ratio of silane to nitrogen is 1:10. The deposition rate of silicon nitride obtained by this method is 1.85 nm / s and the refractive index is 2.31.

[0143] Comparative Example 3

[0144] The method of Example 1 is referred to, except that during the deposition of silicon nitride in the anti-reflection layer, the distance L between the two electrode plates used for deposition is 55 mm. The deposition rate of silicon nitride obtained by this method is 0.51 nm / s and the refractive index is 1.83.

[0145] Comparative Example 4

[0146] The method of Example 1 is used, except that during the deposition of silicon nitride in the anti-reflection layer, the deposition gas pressure P is adjusted to 850 Pa, so that the ratio of the value of L in mm to the value of P in Pa is 1:24.3. The deposition rate of silicon nitride obtained by this method is 2.43 nm / s and the refractive index is 2.33.

[0147] Comparative Example 5

[0148] The method of Example 1 is followed, except that during the deposition of silicon nitride in the anti-reflection layer, the deposition power density is adjusted to 0.54 kW / m 2 The deposition rate of silicon nitride obtained by this method is 0.41 nm / s and the refractive index is 2.25.

[0149] Comparative Example 6

[0150] The method of Example 1 is referred to, except that during the deposition of silicon nitride in the anti-reflection layer, the deposition time is adjusted to 400 seconds, and the ratio of the value of the deposition temperature in ° C to the value of the deposition time in seconds is 1:1.74. The deposition rate of silicon nitride obtained by this method is 1.15 nm / s and the refractive index is 2.31.

[0151] Test Case

[0152] The back contact cells obtained in the above-mentioned embodiments and comparative examples were subjected to various performance tests, and the results are shown in Table 1. The test methods for the same performance indicators of different examples are the same. The various performance indicators of each embodiment and comparative example were converted using Example 1 as a reference benchmark. The data of Example 1 is normalized benchmark 1, and the other examples are converted based on Example 1, such as the minority carrier lifetime gain ratio of Comparative Example 1 / minority carrier lifetime gain ratio of Example 1 is 0.975.

[0153] Among them, the minority carrier lifetime gain ratio refers to the ratio of (minority carrier lifetime after silicon nitride deposition - minority carrier lifetime before silicon nitride deposition) / minority carrier lifetime before silicon nitride deposition, which is used to characterize the change of passivation level before and after silicon nitride deposition. The specific test method is: place the silicon wafer on the Sinton test machine platform to test the minority carrier lifetime A before silicon nitride deposition, and place the silicon wafer on the Sinton test machine platform to test the minority carrier lifetime B after silicon nitride deposition, and calculate the change of (BA) / A.

[0154] PL brightness refers to the brightness of the silicon wafer after silicon nitride deposition, which is tested by PL (photoluminescence measurement system). It is used to characterize whether the silicon nitride deposition causes damage to the passivation or other effects. The PL brightness can reflect the overall passivation and surface damage of the silicon wafer.

[0155] The short-circuit current Isc and battery conversion efficiency are both obtained by conducting corresponding tests on back-contact batteries.

[0156] Table 1

[0157]

[0158] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can achieve uniform growth of silicon nitride in the anti-reflection layer at a low temperature of 200-300°C, with a suitably high deposition rate, and can effectively avoid damage to the front and back amorphous silicon or microcrystalline film layers (including thermal damage or sputtering damage), maintain a high passivation level, ensure the passivation effect and optical anti-reflection effect, increase the short-circuit current, and facilitate the improvement of battery conversion efficiency.

[0159] Furthermore, according to Example 1 and Examples 7-12, it can be seen that the use of the preferred deposition condition schemes of the present invention can further improve passivation and current density, which is more conducive to improving battery conversion efficiency.

[0160] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A method for manufacturing a combined passivation back contact cell, comprising: A first semiconductor layer and a second semiconductor layer are sequentially formed on the back side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, the second doped silicon layer is doped amorphous silicon or doped microcrystalline silicon, the deposition temperature of the second semiconductor layer is 150-195° C., one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type, and then a passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, the anti-reflection layer comprises silicon nitride, and the silicon nitride in the anti-reflection layer is formed by a plasma enhanced chemical vapor deposition process, and the conditions of the plasma enhanced chemical vapor deposition process include: The spacing L between the two electrode plates used for deposition is controlled to be 35-50 mm, and silane, ammonia and nitrogen are introduced. The flow rate of silane is 100-1000 sccm, the flow rate of ammonia is 100-3000 sccm, and the volume flow rate ratio of silane: ammonia: nitrogen is controlled to be 1: (0.1-30): (20-100). The ratio of the value of the spacing L between the two electrode plates in mm to the value of the pressure P in the deposition chamber in Pa is controlled to be 1: (2.22-2.86), P is 50-350 Pa, and the power density of the deposition is 0.6-1.5 kW / m 2 , power density refers to the deposited glow power / coating area; and the deposition temperature of silicon nitride is controlled to be 210-235°C, the ratio of the deposition temperature of silicon nitride to the deposition temperature of the second semiconductor layer is controlled to be 1:(0.80-0.85), and the ratio of the deposition temperature in °C to the deposition time in s is 1:(0.3-1.5), the deposition rate of silicon nitride is 0.5-1.5nm / s, and the refractive index of silicon nitride is 1.90-2.

20.

2. The method for manufacturing a combined passivation back contact cell according to claim 1, characterized in that: The conditions of the plasma enhanced chemical vapor deposition process also include: controlling the flow rate of nitrogen to be 5000-30000 sccm.

3. The method for manufacturing a combined passivation back contact cell according to claim 1, characterized in that: The conditions of the plasma enhanced chemical vapor deposition process also include: the deposition time is 100-300s.

4. The method for manufacturing a combined passivated back contact cell according to any one of claims 1 to 3, characterized in that: The thickness of the silicon nitride is 50-180 nm.

5. The method for manufacturing a combined passivation back contact cell according to claim 1, characterized in that: The anti-reflection layer further comprises silicon oxide, and silicon nitride is located between the passivation layer and the silicon oxide. The thickness of the silicon nitride is 50-100 nm, and the thickness of the silicon oxide is 90-120 nm.

6. The method for manufacturing a combined passivation back contact cell according to claim 1, characterized in that: The passivation layer comprises one or more combinations of an amorphous silicon layer, microcrystalline silicon, polycrystalline silicon, a silicon oxide layer, and an aluminum oxide layer. The thickness of the passivation layer is 5-12 nm.

7. The method for manufacturing a combined passivation back contact cell according to claim 1, characterized in that: The process of sequentially forming a first semiconductor layer and a second semiconductor layer on the back side of the silicon wafer, and then sequentially forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer includes: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S3, performing a first etching opening on the first semiconductor layer and the corresponding mask layer on the back surface obtained in S2 to form second semiconductor opening regions arranged at intervals; S4, then performing texturing and cleaning on the silicon wafer structure obtained in S3, and during the final cleaning process, it is selected whether to remove the mask layer as required; S5, forming a second semiconductor layer on the back surface obtained in S4; S6. Forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer obtained in S5.

8. The method for manufacturing a combined passivation back contact cell according to claim 7, characterized in that: After forming the passivation layer and the anti-reflection layer, the method for manufacturing the combined passivation back contact cell further includes: S7, performing a second etching opening on the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region that is alternately arranged with the second semiconductor opening region; S8, depositing a conductive film layer on the back surface obtained in S7; S9, performing a third etching opening on the conductive film layer on the back obtained in S8 to form an insulating groove between the second semiconductor opening region and the first semiconductor opening region; S10, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S9.

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