Superconducting quantum bit capacitor, superconducting quantum bit, and superconducting quantum circuit

Abstract

The application relates to the technical field of superconducting quantum computing, in particular to a novel superconducting quantum bit capacitor with a long decoherence time, a superconducting quantum bit containing the capacitor and a superconducting quantum circuit, wherein the superconducting quantum bit capacitor is designed to comprise: oppositely arranged first and second electrode plates and a dielectric between the first and second electrode plates; a first wave surface is formed on the inner side surface of the first electrode plate; a second wave surface matching the structure of the first wave surface is formed on the inner side surface of the second electrode plate; the wave crests and wave troughs of the first and second wave surfaces alternately match each other; and a gap is arranged between the first and second wave surfaces. The application can improve the performance of the superconducting quantum bit, prolong the decoherence time of the superconducting quantum bit, and can be applied to the parallel replacement of the superconducting quantum bit in the current superconducting quantum computer chip design, especially in the core microstructure, and has the characteristics of easy replacement and high performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of superconducting quantum computing, in particular to a novel superconducting quantum bit capacitor with a long decoherence time, and a superconducting quantum bit and a superconducting quantum circuit comprising the capacitor. BACKGROUND

[0002] With the development of quantum information technology, superconducting quantum bits are now generally considered to be a feasible solution to realize a practical quantum computer, and the design goal is to increase the number of integrated quantum bits on a chip while improving the performance of individual superconducting quantum bits as much as possible. In order to put practical quantum computers into practical application fields such as network information security, big data, artificial intelligence, chemical and biological pharmaceuticals, financial engineering, and intelligent manufacturing, high-precision control of quantum bits is still needed to complete the accelerated processing of specific problems.

[0003] Since the superconducting quantum circuit design scheme appeared, it has played a certain role in integration technology and large-scale manipulation technology. At the same time, the number of quantum bits on a single chip has also broken through the three-digit number. However, with the continuous upgrading of software and hardware of classical computers, the hardware architecture is more diversified, and the software algorithm is more efficient. At the same time, the number of manipulable quantum bits realized in the physical system of quantum computers limits the size of the algorithm that can be run. In order to maintain the superiority of superconducting quantum computing, it is necessary to solve the problems of the current number of quantum bits on a single chip, connectivity, and decoherence time. At the same time, a large number of physical bits are needed in the process of constructing logical bits, which will lead to a rapid increase in the number of bits in the future. The problems of parasitic modes, circuit crosstalk, and charge noise caused by the corresponding increase will greatly affect the quality of quantum bits. Therefore, whether it is to reduce the error rate or to improve the integration of superconducting quantum chips, in-depth research is needed in material preparation, quantum bit design, and chip processing.

[0004] The existing design scheme is a superconducting quantum bit "Transmon" with a large parallel capacitor plate, which suppresses charge noise by applying a capacitor to the Josephson junction, thereby weakening the decoherence of the superconducting quantum bit and prolonging the decoherence time. However, due to the design of the capacitor plate using a large rectangular metal plate layer, the following problems exist: large space occupation, resulting in low integration of superconducting quantum chips, limiting the number of quantum bits that can be placed on a chip; short decoherence time, which is not sufficient to achieve the number of gate operations required by a practical quantum computer. SUMMARY

[0005] Therefore, the present application provides a novel superconducting quantum bit capacitor with a long decoherence time, and a superconducting quantum bit and a superconducting quantum circuit comprising the capacitor, which solves the problem of low integration and short decoherence time of existing superconducting quantum chips.

[0006] According to the design scheme provided by the application, in one aspect, a superconducting quantum bit capacitor is provided, comprising: oppositely arranged first and second electrode plates, and a dielectric between the first and second electrode plates, a first wave surface is formed on the inner side surface of the first electrode plate, a second wave surface matching the structure of the first wave surface is formed on the inner side surface of the second electrode plate, the wave crests and wave troughs of the first and second wave surfaces are alternately matched, and a gap is arranged between the first and second wave surfaces.

[0007] As the superconducting quantum bit capacitor of the application, further, the gap between the first and second wave surfaces is a wave structure, and the wave crests and wave troughs of the wave structure are consistent with the positions of the wave crests and wave troughs in the structure of the second wave surface.

[0008] As the superconducting quantum bit capacitor of the application, further, the gap distance between the first and second wave surfaces is 30±5μm.

[0009] As the superconducting quantum bit capacitor of the application, further, the distance between the wave crests in the first and second wave surfaces is 180±5μm, and the height difference between the wave crest and the wave trough is 90±5μm.

[0010] As the superconducting quantum bit capacitor of the application, further, the first and second electrode plates both adopt an equal-width size structure.

[0011] In another aspect, the application further provides a superconducting quantum bit, comprising: a planar capacitor, a Josephson junction, a coplanar waveguide resonant cavity, and a quantum bit control line, wherein the planar capacitor adopts the superconducting quantum bit capacitor described above.

[0012] As the superconducting quantum bit of the application, further, it further comprises: a readout line coupled to the coplanar waveguide resonant cavity, and the coupling length is 275±5μm.

[0013] As the superconducting quantum bit of the application, further, the size of the Josephson junction is (198±5)nm×(198±5)nm.

[0014] As the superconducting quantum bit of the application, further, the coplanar waveguide resonant cavity is a short-circuit λ / 4 resonant cavity, wherein λ is the wavelength.

[0015] In another aspect, the application further provides a superconducting quantum circuit comprising the superconducting quantum bit described above.

[0016] The application has the following beneficial effects:

[0017] The application can improve the performance of superconducting quantum bits, prolong the decoherence time, and be suitable for parallel replacement of superconducting quantum bits in current superconducting quantum computer chip design, especially in core microstructure, with easy replacement and high performance characteristics, which can improve the performance of superconducting quantum bits and prolong the bit life under the same size. Further through experimental verification, the capacitor structure under the scheme has good performance in time performance under the same size, which can meet the needs of integrated technology and large-scale manipulation technology superconducting quantum computing application scenarios, and has good application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The superconducting quantum bit capacitor structure in the embodiment is shown;

[0019] Figure 2 The superconducting quantum bit structure in the embodiment is shown;

[0020] Figure 3 The superconducting quantum circuit structure in the embodiment is shown;

[0021] Figure 4 The plate capacitor structure in the embodiment is shown;

[0022] Figure 5 The Josephson junction structure in the embodiment is shown;

[0023] Figure 6 The co-planar waveguide resonant cavity structure in the embodiment is shown;

[0024] Figure 7 The XY control line structure in the embodiment is shown;

[0025] Figure 8 The degree of cross-section in the embodiment is shown;

[0026] Figure 9 The three interfaces in which the superconducting quantum bit exists energy participation in the embodiment is shown;

[0027] Figure 10 The function relationship between the SA cross-section energy participation ratio and the capacitor design value k in the embodiment is shown;

[0028] Figure 11 The superconducting quantum bit interface energy participation ratio of capacitors of different shapes in the embodiment is shown;

[0029] Figure 12 The superconducting quantum bit model and electric field distribution simulation of capacitors of different shapes in the embodiment is shown;

[0030] Figure 13 The superconducting quantum bit chip layout containing capacitors of different shapes in the embodiment is shown;

[0031] Figure 14 A schematic diagram of a superconducting quantum chip in an embodiment;

[0032] Figure 15 A schematic diagram of a scanning electron microscope image of a superconducting quantum chip in an embodiment;

[0033] Figure 16 A schematic diagram of a cavity frequency scan of a co-planar waveguide resonator in an embodiment;

[0034] Figure 17 A schematic diagram of a quantum bit frequency scan in an embodiment;

[0035] Figure 18 A schematic diagram of a quantum bit Rabi oscillation in an embodiment;

[0036] Figure 19 A schematic diagram of a quantum bit decoherence evolution in an embodiment;

[0037] Figure 20 A schematic diagram of a quantum bit Ramsey test result in an embodiment;

[0038] Figure 21 A schematic diagram of a superconducting quantum chip decoherence time test result in an embodiment. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the present application clearer and more apparent, the present application will be further described in detail below with reference to the drawings and technical solutions.

[0040] In view of the integration and decoherence time of the superconducting quantum chip described in the background art, the embodiment of the present application provides a superconducting quantum bit capacitor, as shown in Figure 1 The capacitor includes oppositely arranged first and second electrode plates 1 and 2, and a dielectric between the first and second electrode plates 1 and 2. The inner side surface of the first electrode plate 1 is formed with a first wavy surface, and the inner side surface of the second electrode plate 2 is formed with a second wavy surface matching the structure of the first wavy surface. The wave crests and troughs of the first and second wavy surfaces alternately cooperate with each other, and a gap is provided between the first and second wavy surfaces.

[0041] The miniaturization of the quantum bit structure is closely related to the capacitor structure of the superconducting quantum bit. In the embodiment, the inner side surface of the electrode plate of the capacitor is provided with a wavy surface structure to improve the performance of the superconducting quantum bit and prolong the decoherence time.

[0042] The gap between the first wave surface and the second wave surface is a wave structure, and the wave peak and the wave valley of the wave structure are consistent with the positions of the wave peak and the wave valley in the second wave surface structure. The gap between the first wave surface and the second wave surface can be 30±5 μm. The distance between the wave peak and the wave peak in the first wave surface and the second wave surface can be 180±5 μm, and the height difference between the wave peak and the wave valley can be 90±5 μm. The first electrode plate and the second electrode plate can adopt an equal-width size structure.

[0043] Further, the embodiment of the present application also provides a superconducting quantum bit, referring to Figure 2 and 3 as shown, comprising: a planar capacitor, a Josephson junction, a co-planar waveguide resonant cavity and a quantum bit control line, the planar capacitor adopts the superconducting quantum bit capacitor described above.

[0044] The Josephson junction and the capacitor are designed as independent physical entities. The size of the Josephson junction can be designed as 198±5 nm×198±5 nm. Its natural capacitance can be ignored, because its size is small, and the junction defects are statistically unlikely to occur. The capacitor is made of millimeter-level material with relatively large size, and in experiments, the distance therebetween can be designed as 30 μm, which can generate a capacitance of about 60 fF for the quantum bit; the distance between the wave peak and the wave peak in the first wave surface and the second wave surface can be set as 180 μm, the height difference between the wave peak and the wave valley can be set as 90 μm, and the size of the Josephson junction can be set as 198 nm×198 nm.

[0045] In the “transmon” structure, the superconducting quantum bit capacitor structure unit as shown in Figure 4 , the Josephson junction is connected in parallel with a pair of opposite planar parallel plate capacitors. As shown in Figure 5 (a) Josephson junction structure unit and (b) non-linear energy level distribution diagram, the Josephson junction is a special device formed by two superconductors and a thin insulator in between. Due to the tunneling effect of the superconducting Cooper pair, the Josephson junction is not an insulator, but a non-linear inductive element, which can make the circuit form a non-linear harmonic oscillator level. In order to achieve the input impedance equivalent to the general LCR resonant circuit, the co-planar waveguide resonant cavity selected in the embodiment is a short-circuit λ / 4 resonant cavity. In the superconducting quantum bit, the frequency of the read resonant cavity can be 6-7 GHz. According to the required frequency, the length of the co-planar waveguide can be designed as one quarter of the wavelength to obtain the read resonant cavity. As shown in Figure 6 , one end of the resonant cavity is coupled with the read line, and the coupling length can be designed as 275 μm. In the embodiment, the quantum bit XY control line is as shown in Figure 7As shown, the superconducting quantum chip drives the quantum bit by the XY control line with microwave, when the input frequency is the same as the quantum bit frequency (which can satisfy the energy difference of |0> energy level transition to |1> energy level), the quantum state transitions from the ground state to the excited state. Figure 8 As shown, the readout line is generally realized by a coplanar waveguide, and the measurement signal is mainly applied to the quantum bit through the readout line. Since the common characteristic impedance in the external circuit is 50Ω, in order to achieve impedance matching, the impedance value can be adjusted when designing the readout line of the superconducting quantum chip.

[0046] Further, the embodiment of the present application also provides a superconducting quantum circuit comprising the superconducting quantum bit.

[0047] To verify the effectiveness of the scheme, the following experimental data are further explained:

[0048] When the capacitor is designed as a control line with weak coupling to the external circuit, the energy loss is mainly from the dielectric surface loss of the superconductor and the substrate, and the dephasing time suppressed by the two-level system (TLS) in the dielectric is:

[0049]

[0050] Among the three interface layers on the surface of the quantum bit, the energy participation ratio of the substrate-metal (SM) interface is the largest, which brings more loss and has a more serious impact on the dephasing of the quantum bit. In comparison, the impact of the other two interfaces can be ignored.

[0051] It is known that the dielectric loss of the superconducting quantum bit is derived from the substrate-air (SA), substrate-metal (SM) and metal-air (MA) three interfaces, as shown in Figure 9 As shown, the energy participation ratio between the three interfaces is proportional, and the formula is:

[0052]

[0053]

[0054]

[0055] Among them, P SA , P SM and P MA respectively represent the energy participation ratio of the substrate-air (SA), substrate-metal (SM) and metal-air (MA) three interfaces, ε SA , ε SA and ε SArespectively. k = a / b, where 2a refers to the capacitor gap, and 2b refers to the distance between the outer edges of the capacitor.

[0056] From the perspective of energy participation ratio, the influence of different k values on the energy participation ratio is analyzed. Due to the proportional relationship between the three interfaces, only P SA The function image and optimal solution of k = a / b can be used to determine the increase and decrease of the function, and the function image between them is shown in FIG. 10. Because the energy participation ratio P SA With the change of k = a / b, there is a minimum value in the interval [0, 1]. To improve the quantum bit decoherence time and reduce the dielectric loss of the quantum bit surface, it is necessary to make the energy participation ratio as small as possible, which can be improved in theory by adjusting the capacitor gap and the distance between the outer edges of the capacitor.

[0057] To calculate the total energy participation of the quantum bit surface, the energy participation ratio of each cross section is calculated and integrated. Assuming that the capacitor width is consistent (all 425um), the integral is solved from l = 0 to 425um to obtain the overall interface energy participation ratio of the capacitor, as shown in FIG. 8. Figure 11

[0058] The analysis result shows that the energy participation ratio of the S-mon II-shaped capacitor quantum bit achieves the minimum value. To further verify the design, computer modeling simulation and electric field analysis are performed on the quantum bits with different capacitor shapes.

[0059] Modeling simulation: The capacitor plate is set to 425um wide, and different shapes of quantum bit capacitors can be designed according to the theoretical analysis.

[0060] To evaluate the advantages and disadvantages of quantum bits with different capacitor shapes, the superconducting quantum bit decoherence time T1 needs to be calculated. In this process, the Maxwell capacitor matrix of the superconducting quantum bit capacitor is calculated by using the Q3D modeling simulation tool of the third party simulation tool Ansys, and the electric field distribution result of the superconducting quantum bit in the ideal conductor case is simulated by using the HFSS tool. The simulation model and electric field distribution are shown in FIG. 9, and the theoretical values of the parameters of the five different capacitor shapes of the quantum bit are shown in Table 1. Figure 12

[0061] Table 1 Simulation calculation results of quantum bit parameters

[0062]

[0063] Based on the theory of energy participation ratio and the analysis of the cause of dielectric loss, and according to the simulation of electric field distribution, it is found that the simulation result is consistent with the theoretical analysis, and the S-mon II-shaped capacitor structure in the embodiment can be applied to the design of new quantum bits. The capacitor structure can be named as "S-mon".​​

[0064] The main parameters to consider in layout design are: the relative permittivity ε of the substrate. r Metallic materials, cavity frequency ω r Bit frequency ω0, Josephson junction inductance L n Capacitor C n and resistance R n The coupling strength α between the quantum bit and the readout resonant cavity, chip wiring methods, etc.

[0065] Through comparative experiments, five types of capacitor-shaped qubits were used in the layout: circular plate capacitor, S-mon II capacitor, S-mon I capacitor, rectangular capacitor, and interdigitated capacitor. To avoid manufacturing errors, two of each type of qubit were used. The GDS layout is shown below. Figure 13 As shown. The specific parameter values ​​of the chip are shown in Table 2:

[0066] Table 2 Design parameters for superconducting quantum chips with capacitors of different shapes

[0067]

[0068] The chip substrate is made of sapphire, and the dielectric constant is ε based on empirical data from the manufacturing process. sa =10.6; The metal material used for chip wiring is tantalum (Ta), a superconducting material, which has lower losses than aluminum (Al) but is relatively more difficult to manufacture; To avoid frequency conflicts between resonant cavities on the same transmission line, different cavity frequencies are set for the read resonant cavities corresponding to the five bits, with design values ​​from right to left as 6.95GHz, 6.756GHz, 6.563GHz, 6.371GHz, and 6.178GHz; The bit frequency design values ​​from right to left are 5.3GHz, 5.1GHz, 4.9GHz, 4.7GHz, and 4.5GHz; The coupling strength between the quantum bit and the read resonant cavity is approximately -70MHz; The inductance, capacitance, and resistance values ​​of the Josephson junction are closely related to the bit frequency.

[0069] The chip fabrication process can be described as follows:

[0070] 1. Wafer coating: Using sapphire as a substrate and tantalum as a superconducting metal material, it has greater stability and can reduce losses caused by material defects.

[0071] 2. Formulation: The designed 10-bit chip layout is made into a transparent photomask, which is used to expose the designed circuit diagram during the photolithography process.

[0072] 3. Metal deposition: Tantalum is deposited on the chip surface using electron beam evaporation and then allowed to stand naturally.

[0073] 4. Photoetching: Photoresist AZ6112 is coated on the wafer at 4000 rpm for 30 s, and then baked at 100°C for 120 s. The chip circuit is projected onto the wafer surface by using a fixed intensity ultraviolet light to pass through the photoetching mask plate.

[0074] 5. Developing: The photoresist is dissolved by immersing the chip in developing solution 3038 for 30-38 s, and the remaining photoresist and the circuit of the photoetching mask plate are left. Figure 1 .

[0075] 6. Hardening: Baking at 110°C for 120 s.

[0076] 7. Etching: Dry etching is used to retain the complete chip circuit, which is observed by an electron microscope.

[0077] 8. Dicing: The completed wafer is diced, and the middle chip is selected for the next experiment to ensure the quality of the chip.

[0078] 9. Packaging: The chip is connected to the packaging box by a wire bonding machine.

[0079] Through theory and simulation, and drawing a layout and micro-nano processing, the final ten-bit superconducting quantum chip is obtained in the laboratory after preparation, dicing and packaging, as shown in Figure 14 and 15 . After obtaining the superconducting quantum chip, it needs to be placed in an extremely low temperature environment provided by a dilution refrigerator for testing. The specific testing process can be described as follows:

[0080] 1. Chip and dilution refrigerator wiring, as shown in Table 3:

[0081] Table 3 Dilution refrigerator wiring diagram

[0082]

[0083] 2. Adjust the quantum measurement and control all-in-one machine: enable the network port and server, connect the server on the remote computer, and start the all-in-one machine server program. The AWG module connects the two ends of the readout line to IN and OUT according to the connection of the chip and the dilution refrigerator, which is used for microwave input and reading, and connects the 10 quantum bit control end ports to the corresponding all-in-one machine interface.

[0084] 3. Cavity frequency: as shown in Figure 16 , a range of microwaves is input to the readout line, and when it is consistent with the frequency of the coplanar waveguide resonant cavity, resonance occurs, which appears as a sharp downward absorption peak on the wave spectrum. The value corresponding to the abscissa is the cavity frequency. Increasing the scanning power causes the scanned cavity frequency to drift in frequency, resulting in dispersion. Therefore, it can be inferred that there are five quantum bits on this readout line.

[0085] 4. Bit frequency: asFigure 17 As shown, under the premise that the frequency of the coplanar waveguide resonant cavity corresponding to the current qubit is determined, a range of microwaves is given to the qubit through the XY control line to find the frequency corresponding to the qubit excitation peak, and the qubit frequency is determined.

[0086] 5, Rabi oscillation: as shown, Figure 18 Determine the two-level system of the qubit, and calibrate the π pulse amplitude.

[0087] 6, T1 test: as shown, Figure 19 The qubit transition is excited through the XY control line, and then the qubit gradually returns to the ground state with energy dissipation. The energy relaxation time measured in this process is the dephasing time T1.

[0088] 7, Ramsey: as shown, Figure 20 T2 test is performed, i.e. the phase relaxation time of the qubit.

[0089] The cavity frequency and bit frequency test results are shown in Table 4. The measured cavity frequency is consistent with the design value, and the deviation of the measured bit frequency from the design value is within a reasonable process error range.

[0090] Table 4 Design and test values of superconducting quantum chip with different shaped capacitors

[0091]

[0092]

[0093] The test results of the dephasing time T1 and the comparison with the classical rectangular capacitor qubit are shown in Table 5. The T1 and T2 test results of the five capacitors on the chip are shown in detail. Figure 21

[0094] Table 5 Comparison of chip test results

[0095]

[0096] The above experiment can be repeated to find that in the actual chip, the dephasing time of "S-mon" is longer than that of the other several capacitors.

[0097] Therefore, based on the above experimental data and theory, it can be found that for any surface loss mechanism, changing the size of the capacitor can reduce the surface loss effect of the qubit device. From the perspective of energy participation ratio, taking the dephasing time as the optimization index, by optimizing the dielectric loss of the substrate-metal interface (SM), the capacitor structure in the present case can prolong the dephasing time and prolong the life of the superconducting qubit, which has good application prospect. ​

[0098] The relative arrangement of components and steps, numerical expressions, and numerical values set forth in the Examples are not intended to limit the scope of the application unless specifically stated otherwise.

[0099] The various embodiments described in this specification are presented by way of example, and each embodiment is not necessarily composed of all features described with respect to other embodiments. The embodiments disclosed in the specification are for a system corresponding to the embodiments disclosed for a method, and thus are described relatively simply, with reference to the description of the method.

[0100] The units and method steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation does not exceed the scope of the present application.

[0101] A person of ordinary skill in the art can understand that all or part of the steps in the above method can be instructed by a program to complete by relevant hardware, and the program can be stored in a computer readable storage medium, such as a read-only memory, a magnetic disk or an optical disk, etc. Alternatively, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits, and accordingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software function module. The present application is not limited to any specific form of combination of hardware and software.

[0102] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present application, which are used to illustrate the technical solutions of the present application, and are not limiting. The protection scope of the present application is not limited thereto, and although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that any person skilled in the art within the technical scope disclosed by the present application can modify or easily think of changes to the technical solutions described in the foregoing embodiments, or make equivalent replacements to some of the technical features; and these modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A superconducting quantum bit capacitor, comprising: a first electrode plate and a second electrode plate disposed opposite to each other, and a dielectric material located between the first electrode plate and the second electrode plate, characterized in that, A first wave surface is formed on the inner side of the first electrode plate, and a second wave surface matching the structure of the first wave surface is formed on the inner side of the second electrode plate. The crests and troughs of the first wave surface and the second wave surface alternate with each other, and a gap is provided between the first wave surface and the second wave surface. The distance between the crests of both the first and second wave surfaces is 180±5μm, and the height difference between the crests and troughs is 90±5μm.

2. The superconducting quantum bit capacitor according to claim 1, characterized in that, The gap between the first wave surface and the second wave surface is a wave structure, and the peaks and troughs of this wave structure are in the same positions as the peaks and troughs in the second wave surface structure.

3. The superconducting quantum bit capacitor according to claim 1 or 2, characterized in that, The gap between the first wave surface and the second wave surface is 30±5μm.

4. The superconducting quantum bit capacitor according to claim 1, characterized in that, The first electrode plate and the second electrode plate are of equal width.

5. A superconducting quantum bit, comprising: a planar capacitor, a Josephson junction, a coplanar waveguide resonant cavity, and a quantum bit control line, characterized in that, The planar capacitor is the superconducting quantum bit capacitor as described in any one of claims 1 to 4.

6. The superconducting quantum bit according to claim 5, characterized in that, It also includes: a readout line coupled to the coplanar waveguide resonant cavity, with a coupling length of 275±5μm.

7. The superconducting quantum bit according to claim 5, characterized in that, The dimensions of the Josephson junction are (198±5)nm×(198±5)nm.

8. The superconducting quantum bit according to claim 5, characterized in that, The coplanar waveguide resonant cavity is a short-circuited λ / 4 resonant cavity, where λ is the wavelength.

9. A superconducting quantum circuit, characterized in that, Includes the superconducting quantum bit as described in claim 6.

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