A method, system, chip and memory for generating an image recognition model

Abstract

The present invention belongs to the field of chip recognition technology, and discloses a method, system, chip and memory for generating an image recognition model, including: obtaining high-definition circuit images of multiple chips, separating key circuit components from background areas in the collected high-definition circuit images of each chip, performing feature extraction, obtaining key information, converting the information into graphic symbols, forming a feature symbol set, and establishing a mapping relationship; designing a basic framework, arranging and combining corresponding graphic symbols, simulating the circuit layout of each chip, generating multiple groups of new circuit structure images, inputting them into a basic processing model as training data for training, and obtaining an image recognition model; optimizing the separation of key circuit components from the background, and effectively extracting and symbolizing component features in the structural feature mapping stage, thereby improving the processing speed, simplifying the recognition process, and providing a more efficient, simplified and low-cost solution for chip circuit image recognition.

Description

Technical Field

[0001] The present invention relates to the field of chip recognition technology, and in particular to a method, system, chip and memory for generating an image recognition model. Background Art

[0002] In today's electronic manufacturing industry, chips are core components, and their quality and performance directly affect the reliability and performance of the final product. With the advancement of technology, the design and manufacturing of chips have become more and more complex, which requires precise quality control and testing during the production process; image recognition technology plays a key role in this process. It can quickly and accurately analyze chip circuit images, identify potential defects and problems, and thus ensure the high quality of the chip. However, with the continuous iteration and complexity of chip design, traditional image recognition technology faces more and more challenges.

[0003] Image recognition of chips in the existing technology mainly relies on complex image processing algorithms and machine learning models. These methods usually require a large amount of data to train the recognition model and rely on high-performance computing resources to process complex circuit images, which not only increases the time cost of the recognition process, but also raises the technical threshold and limits its application in small or medium-sized manufacturing industries. In addition, with the increasing complexity of chip design, traditional methods also face challenges in recognition accuracy and efficiency, especially when dealing with high-density and small-size circuit elements, the accuracy still needs to be improved.

[0004] In view of this, it is necessary to improve the image recognition technology of the chip in the prior art to solve the technical problems of complex recognition process and high cost. Summary of the invention

[0005] The purpose of the present invention is to provide a method, system, chip and memory for generating an image recognition model to solve the above technical problems.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A method for generating an image recognition model, comprising:

[0008] Obtain high-definition circuit images of multiple sample chips, and separate key circuit components from background areas in the collected high-definition circuit images of each chip through image processing technology to obtain images of key circuit components and corresponding background images;

[0009] Extracting features from the separated key circuit component images to obtain key information on the shapes, dimensions and connection modes of the key circuit components, and converting the key information into graphic symbols to form a feature symbol set;

[0010] Based on the characteristic symbol set, establishing a mapping relationship between graphic symbols and key circuit elements;

[0011] Design a basic framework for simulating chip circuit structure, input the characteristic symbol set into the basic framework, and arrange and combine corresponding graphic symbols to simulate the circuit layout of each chip;

[0012] The simulated circuit layout is synthesized with the corresponding background image to generate multiple sets of new circuit structure images, and the new circuit structure images are input into the basic processing model as training data for training to obtain an image recognition model.

[0013] Optionally, the method of acquiring high-definition circuit images of multiple sample chips, separating key circuit components from background areas in the high-definition circuit images of each chip acquired by image processing technology, and obtaining key circuit component images and corresponding background images, specifically includes:

[0014] Collecting high-definition circuit images from a variety of sample chips; wherein the high-definition circuit images include multiple viewing angles and layers of the chip;

[0015] Preprocessing the collected high-definition circuit images; the preprocessing includes denoising, brightness adjustment and contrast enhancement;

[0016] Using an edge detection algorithm, identifying the contour information of key circuit components in the circuit high-definition image, and defining the area outside the contour of each key circuit component as a background area;

[0017] Applying the image segmentation technology of the region growing algorithm, the key circuit element is separated from the background area according to the contour information to obtain the key circuit element image and the background image;

[0018] The obtained background image is post-processed, and the background image includes filling and smooth edge processing.

[0019] Optionally, feature extraction is performed on the separated key circuit element image to obtain key information on the shape, size value and connection mode of the key circuit element; specifically including:

[0020] By detecting the contour curve and corner points of each separated key circuit component image, the geometric features of the key circuit component image are calculated to identify the shape;

[0021] Measure the size of the key circuit component image, convert the size measurement result into an actual size by pixel ratio, and calibrate the actual size based on the resolution of the image and a preset reference size to obtain a size value;

[0022] Analyze the wires and connection points in the circuit high-definition image, and use a path tracing algorithm to identify the wire connection path and its starting and ending points, so as to analyze and obtain the connection mode between each of the key circuit elements;

[0023] Based on the obtained information of shape, size value and connection mode, a feature vector is constructed for each key circuit element.

[0024] Optionally, the key information is converted into graphic symbols to form a characteristic symbol set; specifically including:

[0025] Designing a set of graphic symbols based on the characteristic vectors of the key circuit elements, and incorporating functional attributes of the key circuit elements into the graphic symbols;

[0026] Determine the association between different key circuit components, divide them into associated component groups and unassociated component groups, and set connection marks between the graphic symbols of the associated component groups to establish visual links;

[0027] All of the graphic symbols are summarized to form a characteristic symbol set.

[0028] Optionally, the design of a basic framework for simulating chip circuit structure, inputting the characteristic symbol set into the basic framework, and arranging and combining corresponding graphic symbols to simulate the circuit layout of each chip; specifically includes:

[0029] Designing a basic framework for simulating chip circuit structure according to the specifications of each chip, and inputting the characteristic symbol set into the basic framework;

[0030] Based on the key circuit component images separated from the circuit high-definition image of each chip, and in combination with the mapping relationship between the key circuit components and the graphic symbols, the corresponding type of graphic symbols are selected from the characteristic symbol set, and the quantity of each graphic symbol is set;

[0031] Using an automatic layout algorithm to arrange and combine the selected graphic symbols in the basic framework, simulating the circuit layout of each chip;

[0032] The shortest connection path and the optimal layout of components of the circuit layout are set by using an optimization mechanism to obtain an optimized circuit layout.

[0033] Optionally, the simulated circuit layout is synthesized with the corresponding background image to generate multiple sets of new circuit structure images, and the new circuit structure images are input as training data into a basic processing model for training to obtain an image recognition model; specifically including:

[0034] Using an image synthesis algorithm to fuse the simulated circuit layout into the corresponding background image, generating multiple sets of new circuit structure images, and marking key circuit components in the new circuit structure images;

[0035] A convolutional neural network is selected as a basic processing model, and multiple groups of new circuit structure images are sequentially input into the basic processing model for model training, and the trained basic processing model is used as an image recognition model.

[0036] Optionally, the step of obtaining the image recognition model further includes:

[0037] A high-definition circuit image of a chip in a verification set is input into the image recognition model, the recognition performance of the image recognition model is evaluated, and parameters of the image recognition model are adjusted according to the performance evaluation results to obtain an optimized image recognition model.

[0038] The present invention also provides a system for generating an image recognition model, which is used to implement the method for generating an image recognition model as described above, and the generation system comprises:

[0039] An image acquisition unit, used to obtain high-definition circuit images of various sample chips;

[0040] The image processing module includes a separation unit and a feature extraction unit. The separation unit is used to separate the key circuit components from the background area in the collected circuit high-definition image of each chip to obtain a key circuit component image and a corresponding background image; the feature extraction unit is used to extract features from the separated key circuit component image to obtain key information on the shape, size value and connection mode of the key circuit component;

[0041] A symbolization module, used for converting the key information into graphic symbols to form a characteristic symbol set;

[0042] A circuit simulation unit, used to input the characteristic symbol set in the basic framework, and arrange and combine the corresponding graphic symbols to simulate the circuit layout of each chip;

[0043] An image synthesis unit, used for synthesizing the simulated circuit layout with the corresponding background image to generate multiple sets of new circuit structure images;

[0044] A basic processing model for generating an image recognition model based on a plurality of sets of new circuit structure images as training data;

[0045] The display unit is used to display the simulated circuit layout.

[0046] The present invention also provides a chip of an image recognition model, comprising a memory and at least one processor, wherein instructions are stored in the memory;

[0047] The processor calls the instructions in the memory so that the processor executes the method for generating the image recognition model as described above.

[0048] The present invention also provides a memory storing instructions for implementing the method for generating the image recognition model as described above.

[0049] Compared with the prior art, the present invention has the following beneficial effects: the method first obtains high-definition circuit images of various sample chips, and uses image processing technology to separate key circuit components and background, obtains circuit component images and backgrounds of each chip, and then performs in-depth feature extraction on these key circuit component images, identifies key information of component shape, size and connection mode, converts them into graphic symbols, establishes a feature symbol set containing various component features, creates mapping relationships corresponding to key circuit components, and designs a basic framework for simulating chip circuit structures, inputs the feature symbol set, and arranges and combines the symbols appropriately to simulate a specific circuit layout; the simulated The circuit layout is synthesized with the background image to generate a new circuit structure image, and these images are used as training data to train the basic processing model to form an image recognition model that can recognize circuit images. This solution significantly reduces the data volume of the processing model by optimizing the separation of key circuit components and the background, and effectively extracts and symbolizes component features in the structural feature mapping stage, thereby improving the processing speed. At the same time, by converting complex circuit images into simplified graphic symbols, the complexity of the model training and recognition process is greatly reduced, the processing speed of chip image recognition is accelerated, and the recognition process is simplified, providing a more efficient, simplified and low-cost solution for chip circuit image recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0051] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0052] Figure 1 This is one of the flowcharts of the method for generating the image recognition model;

[0053] Figure 2 This is the second flowchart of the method for generating the image recognition model;

[0054] Figure 3 This is the third flowchart of the method for generating the image recognition model. DETAILED DESCRIPTION

[0055] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] In the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0057] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0058] Embodiment 1:

[0059] Combination Figures 1 to 3 As shown, an embodiment of the present invention provides a method for generating an image recognition model, comprising:

[0060] S1, obtaining high-definition circuit images of multiple sample chips, and separating key circuit components from background areas in the collected high-definition circuit images of each chip through image processing technology to obtain key circuit component images and corresponding background images;

[0061] Advanced image processing technology is used to separate key circuit components from the background from the collected high-definition images of diverse chip circuits. The accuracy of image separation determines whether the model can correctly identify and analyze circuit components, which is the basis for building an efficient and accurate image recognition model. Through this step, it can be ensured that the obtained images of key circuit components are of high quality.

[0062] S2, extracting features from the separated key circuit component images to obtain key information on the shapes, dimensions and connection methods of the key circuit components, and converting the key information into graphic symbols to form a feature symbol set;

[0063] Extracting key information from the separated circuit component images and converting this information into graphic symbols to form a feature symbol set is crucial to improving the efficiency and accuracy of the entire system. By converting to graphic symbols, not only is the representation of circuit components simplified, but it also provides a more efficient data form for machine learning models. This conversion process helps reduce the computing resources required for model training and improves the speed and accuracy of the recognition process. The depth and breadth of feature extraction directly affect the final performance of the image recognition model.

[0064] S3, establishing a mapping relationship between graphic symbols and key circuit components based on the characteristic symbol set;

[0065] Establishing the mapping relationship between graphic symbols and actual circuit components is a step to connect abstract graphic symbols with specific circuit component properties to ensure that the subsequent model can correctly interpret the meaning of each symbol. The accuracy of the mapping relationship is directly related to the effect of model recognition, ensuring that the model can not only recognize graphic symbols, but also understand the specific circuit components they represent.

[0066] S4, designing a basic framework for simulating chip circuit structure, inputting a characteristic symbol set into the basic framework, and arranging and combining corresponding graphic symbols to simulate the circuit layout of each chip;

[0067] By designing a basic framework that simulates the circuit structure of a chip, inputting a set of characteristic symbols, and arranging and combining the symbols, this process simulates the circuit layout of each chip. The core of this step is to convert abstract symbols into specific circuit layout diagrams, which is not only crucial for understanding the function and structure of the circuit, but also a key step in generating high-quality training data; the design of the basic framework needs to be flexible enough to adapt to different types of circuit designs, and also needs to be accurate enough to ensure that the generated circuit layout diagram is close to the actual situation.

[0068] S5, synthesizing the simulated circuit layout with the corresponding background image to generate multiple sets of new circuit structure images, and inputting the new circuit structure images as training data into the basic processing model for training to obtain an image recognition model.

[0069] The simulated circuit layout is synthesized with the background image to generate multiple sets of new circuit structure images, and these images are used as training data to input into the basic processing model, and finally the image recognition model is obtained. This step is the key link to transform the results of the previous steps into an image recognition model that can be used for practical applications. Through model training, the model can learn to recognize circuit components and layouts in different backgrounds, which enhances the generalization ability of the model in practical applications.

[0070] The working principle of the present invention is as follows: the method first obtains high-definition circuit images of various sample chips, and uses image processing technology to separate key circuit components and background, obtains circuit component images and their backgrounds of each chip, and then performs in-depth feature extraction on these key circuit component images, identifies key information of component shape, size and connection mode, converts them into graphic symbols, establishes a feature symbol set containing various component features, creates mapping relationships corresponding to key circuit components, and designs a basic framework for simulating chip circuit structures, inputs the feature symbol set, and arranges and combines the symbols appropriately to simulate a specific circuit layout; synthesizes the simulated circuit layout with the background image, Generate new circuit structure images, and use these images as training data to train the basic processing model to form an image recognition model that can recognize circuit images; compared with the recognition technology in the prior art, this solution significantly reduces the data volume of the processing model by optimizing the separation of key circuit components and the background, and effectively extracting and symbolizing component features in the structural feature mapping stage, thereby improving the processing speed; at the same time, by converting complex circuit images into simplified graphic symbols, the complexity of the model training and recognition process is greatly reduced, the processing speed of chip image recognition is accelerated, and the recognition process is simplified, providing a more efficient, simplified and low-cost solution for chip circuit image recognition.

[0071] In this embodiment, it is specifically explained that step S1 specifically includes:

[0072] S11, collecting high-definition circuit images from a plurality of sample chips; wherein the high-definition circuit images include multiple viewing angles and layers of the chip;

[0073] High-definition images of circuits are collected from different sample chips, covering multiple perspectives and levels of the chip to ensure that the details of the circuit components are fully captured. High-definition and all-round images can ensure that the extracted circuit component features are accurate and comprehensive enough; multi-angle and multi-level image acquisition helps to improve the comprehensiveness and accuracy of the model's recognition of circuit components, and is the basis and starting point for the entire image recognition model generation process.

[0074] S12, preprocessing the collected circuit high-definition image; the preprocessing includes denoising, brightness adjustment and contrast enhancement;

[0075] The collected circuit high-definition images are preprocessed, including denoising, brightness adjustment, and contrast enhancement. This directly affects the distinction between circuit components and background in the image, and thus affects the subsequent edge detection and component separation. Preprocessing improves image quality and provides a clearer visual basis for feature extraction and circuit component identification. Denoising can reduce misidentification, and brightness and contrast adjustment make the outline of circuit components more obvious, laying the foundation for edge detection.

[0076] S13, identifying contour information of key circuit components in the circuit high-definition image through an edge detection algorithm, and defining the area outside the contour of each key circuit component as a background area;

[0077] Use edge detection algorithms, such as Canny edge detection, to identify the contour information of key circuit components in the circuit HD image; this step is the key to separating key circuit components from the background, because correct contour information is the prerequisite for accurate segmentation. The accuracy of edge detection directly determines the quality of the separated circuit component image. By identifying clear contours, it can not only ensure the effective separation of circuit components from the background, but also retain the integrity of the components and the accuracy of identification to a certain extent.

[0078] S14, applying the image segmentation technology of the region growing algorithm to separate the key circuit component from the background region according to the contour information, and obtaining the key circuit component image and the background image;

[0079] Apply image segmentation techniques, such as region growing algorithms, to accurately separate key circuit components from the background based on the contour information obtained in the previous step. Accurate image segmentation ensures that each circuit component is fully extracted while minimizing interference with component shape and size, providing accurate input data for subsequent feature extraction and symbolization.

[0080] S15, the obtained background image is post-processed, and the background image includes filling and smoothing edge processing.

[0081] Post-processing of the separated background image, including filling and smoothing edges, can further improve the image quality, especially the irregular edges generated when segmenting the elements can be improved by smoothing. In addition, the filling of the background helps maintain the overall consistency of the image and create a cleaner and more unified background environment for subsequent image synthesis and model training.

[0082] In this embodiment, it is specifically described that step S2 specifically includes:

[0083] S21, detecting contour curves and corner points of each separated key circuit component image, calculating geometric features of the key circuit component image, and identifying and obtaining a shape;

[0084] The geometric features of each key circuit component image are identified through contour curve and corner point detection technology, so as to accurately obtain its shape; the precise detection of contour curves and corner points can not only help to accurately identify the type of component, but also provide a clear and unique identification for each circuit component in the subsequent graphic symbol conversion process, which is fundamental work for building an efficient and accurate image recognition model.

[0085] S22, measuring the size of the key circuit component image, converting the size measurement result into an actual size through a pixel ratio, and calibrating the actual size based on the resolution of the image and a preset reference size to obtain a size value;

[0086] The process of measuring the dimensions of key circuit component images and converting these measurement results into actual dimensions involves consideration of image resolution and calibration of preset reference dimensions. Dimensions are another important dimension in describing the characteristics of circuit components, which not only affects the physical layout of components, but also the performance of circuits. Accurate dimension measurement and calibration can ensure that the subsequent simulated circuit layout is closer to the actual situation, providing accurate basic data for circuit design and analysis.

[0087] S23, analyzing the wires and connection points in the circuit high-definition image, using a path tracing algorithm to identify the wire connection path and its starting and ending points, so as to analyze and obtain the connection mode between each key circuit element;

[0088] By analyzing the wires and connection points in the high-definition images of the circuit, and using the path tracing algorithm to identify the connection path of the wire and its starting and ending points, the connection method between each key circuit component can be analyzed. This step is crucial to understanding the function and logic of the circuit. The connection method between components not only determines the working method of the circuit, but also affects the performance and stability of the circuit; accurately identifying the connection method is crucial for subsequent applications such as simulating the working principle of the circuit and performing fault diagnosis.

[0089] S24, constructing a feature vector for each key circuit element according to the obtained information of shape, size value and connection mode.

[0090] Based on the information of shape, size and connection mode obtained in the previous step, the process of constructing feature vectors for each key circuit component is a highly abstract and compressed version of the circuit component properties, which converts the key information of the circuit component into a format that can be effectively processed by a computer. This step is a bridge between component identification and subsequent circuit simulation and image recognition model training, ensuring that the characteristics of circuit components can be accurately identified and utilized by subsequent processes in a standardized and simplified manner; the quality of feature vector construction directly affects the training effect and recognition accuracy of the image recognition model.

[0091] In this embodiment, it is further explained that step S2 also includes:

[0092] S25, design a set of graphic symbols based on the characteristic vectors of key circuit components, and integrate the functional attributes of key circuit components into the graphic symbols;

[0093] The characteristic vectors of key circuit components are used to design graphic symbols, and the functional properties of the components are integrated into these symbols; circuit components are represented not only by shape and size, but also by the functional properties of the components, so that the symbols are not just a visual representation, but contain information about the performance and function of the components. This design method improves the information density of the symbols, so that the symbols themselves can provide more contextual information about the components, providing a richer foundation for subsequent circuit analysis, simulation and teaching.

[0094] S26, determining the association between different key circuit components, dividing them into associated component groups and unassociated component groups, and setting connection marks between graphic symbols of the associated component groups to establish visual links;

[0095] Determine the associations between different key circuit components, and visually represent these relationships through connection marks, dividing the components into associated component groups and unassociated component groups; the advantage of this step is that it intuitively shows the interactions and connections between circuit components through visual links, which not only enhances the readability of the circuit diagram, but also provides direct help for understanding the function and logic of the circuit. In this way, complex circuit component interactions can be directly represented in the circuit diagram without adding additional text descriptions, simplifying the circuit design and analysis process and improving work efficiency.

[0096] S27, summarize all graphic symbols to form a feature symbol set. The necessary input data is prepared for circuit simulation and image recognition model training. The establishment of the feature symbol set not only facilitates the use of circuit designers, but also provides an efficient and standardized data format for machine learning algorithms. Through such a symbol set, the complexity of data processing can be greatly reduced while ensuring the richness of information, and the execution efficiency and accuracy of subsequent steps can be improved.

[0097] In this embodiment, it is specifically explained that step S4 specifically includes:

[0098] S41, designing a basic framework for simulating chip circuit structure according to the specifications of each chip, and inputting a characteristic symbol set into the basic framework;

[0099] It is important to design a suitable basic framework, which needs to be flexible enough to adapt to different types of chip circuits and be able to accurately accommodate the input feature symbol set. The design of the basic framework is not only related to the accuracy of the simulation process, but also affects the practicality and visualization of the final circuit layout.

[0100] S42, based on the key circuit component images separated from the circuit high-definition image of each chip, and combined with the mapping relationship between the key circuit components and the graphic symbols, select the corresponding type of graphic symbols from the feature symbol set, set the number of each graphic symbol; at the same time, the unselected graphic symbols are discarded.

[0101] Based on the key circuit component images separated from the high-definition circuit images of each chip, and using the mapping relationship between components and graphic symbols, the corresponding types of graphic symbols are selected from the feature symbol set, and the quantity of each graphic symbol is set; this step is a bridge connecting the preliminary preparation work with the circuit simulation work, ensuring that the symbols used in the simulation not only correspond to the actual components, but also match the quantity. Through such selection and setting, it can be ensured that the simulated circuit layout is as close as possible to the real circuit design in terms of both vision and function.

[0102] S43, using an automatic layout algorithm to arrange and combine the selected graphic symbols in a basic framework to simulate the circuit layout of each chip;

[0103] It should be noted that the automatic layout algorithm is preferably a force-directed algorithm, which is suitable for maintaining the relative positions between components and optimizing the length of connections, and is often used in circuit board layout and network diagram visualization.

[0104] By using an automatic layout algorithm to arrange and combine selected graphic symbols in a basic framework, the circuit layout of each chip is simulated. The use of an automatic layout algorithm is the key to improving the efficiency and accuracy of circuit simulation. It can intelligently arrange the position and connection of components according to preset rules and parameters to generate a high-quality circuit layout diagram; this step not only greatly reduces the time and effort required for manual layout, but also achieves a more efficient and reasonable circuit layout through algorithm optimization, which helps to improve the performance and reliability of the circuit.

[0105] S44, using an optimization mechanism to set the shortest connection path of the circuit layout and the optimal layout of components to obtain an optimized circuit layout.

[0106] The circuit layout is optimized through the optimization mechanism to set the shortest connection path and the optimal layout of components; the purpose of this step is to improve the automatic layout results through the optimization algorithm and reduce unnecessary connections in the circuit.

[0107] In this embodiment, it is specifically described that step S5 specifically includes:

[0108] S51, using an image synthesis algorithm to fuse the simulated circuit layout into the corresponding background image, generating multiple sets of new circuit structure images, and marking key circuit components in the new circuit structure images;

[0109] Among them, the image synthesis algorithm is Poisson fusion, which is a technology widely used in image editing. It uses the Poisson equation to smoothly blend the foreground object into the background image.

[0110] The simulated circuit layout is integrated into the corresponding background image using an image synthesis algorithm to generate multiple sets of new circuit structure images with a sense of real scenes, and the key circuit components in these images are annotated; this not only increases the diversity of circuit images, but also improves the generalization ability of the model in practical applications by displaying the circuit layout under different backgrounds. The accurate annotation of circuit components ensures the quality of the training data set, laying the foundation for training high-performance image recognition models.

[0111] S52, selecting a convolutional neural network as a basic processing model, inputting multiple sets of new circuit structure images into the basic processing model in sequence for model training, and using the trained basic processing model as an image recognition model.

[0112] Convolutional neural network (CNN) is selected as the basic processing model, and multiple sets of new circuit structure images are generated for model training, aiming to obtain an image recognition model that can efficiently identify circuit components and layouts; CNN's capabilities in feature extraction and pattern recognition make it an ideal choice. The successful execution of this step depends on sufficient and diverse training data sets, as well as effective training strategies, including appropriate loss functions, optimizer selection, and hyperparameter adjustment, to ensure the optimal performance of the image recognition model.

[0113] In this embodiment, it is further explained that after step S5, the following steps are further included:

[0114] S6, providing a high-definition circuit image of the chip of the verification set as input into the image recognition model, evaluating the recognition performance of the image recognition model, and adjusting the parameters of the image recognition model according to the performance evaluation results to obtain an optimized image recognition model.

[0115] Use the validation set to evaluate the performance of the image recognition model, and make necessary parameter adjustments to the model based on the evaluation results to obtain an optimized image recognition model. Performance evaluation usually involves indicators such as accuracy, recall, and F1 score, which can fully reflect the recognition ability of the model. The model is further optimized based on parameter adjustments based on the evaluation results, which includes adjusting the network structure, learning rate, regularization strategy, etc. The iterative process of this step is a routine part of model development, which aims to continuously improve the performance of the model until it meets the needs of actual applications.

[0116] Embodiment 2:

[0117] The present invention also provides a system for generating an image recognition model, which is used to implement the method for generating an image recognition model as described in the first embodiment. The generation system includes:

[0118] An image acquisition unit, used to obtain high-definition circuit images of various sample chips;

[0119] The image processing module includes a separation unit and a feature extraction unit. The separation unit is used to separate the key circuit components from the background area in the circuit high-definition image collected for each chip to obtain the key circuit component image and the corresponding background image; the feature extraction unit is used to extract features from the separated key circuit component image to obtain key information on the shape, size value and connection mode of the key circuit component;

[0120] The symbolization module is used to convert key information into graphic symbols to form a characteristic symbol set;

[0121] The circuit simulation unit is used to input the characteristic symbol set in the basic framework, and arrange and combine the corresponding graphic symbols to simulate the circuit layout of each chip;

[0122] An image synthesis unit, used to synthesize the simulated circuit layout with the corresponding background image to generate multiple sets of new circuit structure images;

[0123] A basic processing model for generating an image recognition model based on multiple sets of new circuit structure images as training data;

[0124] The display unit is used to display the simulated circuit layout.

[0125] Embodiment three:

[0126] The present invention also provides a chip of an image recognition model, comprising a memory and at least one processor, wherein the memory stores instructions;

[0127] The processor calls the instructions in the memory so that the processor executes the method for generating the image recognition model as described in the first embodiment.

[0128] Embodiment 4:

[0129] The present invention also provides a memory storing instructions for implementing the method for generating an image recognition model as described in the first embodiment.

[0130] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating an image recognition model, It is characterized in that include: Obtain circuit high-definition images of multiple sample chips, and separate key circuit components from background areas in the collected circuit high-definition images of each chip through image processing technology to obtain key circuit component images and corresponding background images; Extracting features from the separated key circuit component images to obtain key information on the shapes, dimensions and connection modes of the key circuit components, and converting the key information into graphic symbols to form a feature symbol set; Based on the characteristic symbol set, establishing a mapping relationship between graphic symbols and key circuit elements; Design a basic framework for simulating chip circuit structure, input the characteristic symbol set into the basic framework, and arrange and combine corresponding graphic symbols to simulate the circuit layout of each chip; The simulated circuit layout is synthesized with the corresponding background image to generate multiple sets of new circuit structure images, and the new circuit structure images are input into the basic processing model as training data for training to obtain an image recognition model.

2. The method for generating an image recognition model according to claim 1, It is characterized in that The method of obtaining high-definition circuit images of multiple sample chips, separating key circuit components from background areas in the high-definition circuit images of each chip collected by image processing technology, and obtaining key circuit component images and corresponding background images, specifically includes: Collecting high-definition circuit images from a variety of sample chips; wherein the high-definition circuit images include multiple viewing angles and layers of the chip; Preprocessing the collected high-definition circuit images; the preprocessing includes denoising, brightness adjustment and contrast enhancement; Using an edge detection algorithm, identifying the contour information of key circuit components in the circuit high-definition image, and defining the area outside the contour of each key circuit component as a background area; Applying the image segmentation technology of the region growing algorithm, the key circuit element is separated from the background area according to the contour information to obtain the key circuit element image and the background image; The obtained background image is post-processed, and the post-processing includes filling and smoothing edge processing.

3. The method for generating an image recognition model according to claim 1, It is characterized in that Feature extraction is performed on the separated key circuit component images to obtain key information on the shape, size and connection mode of the key circuit components; specifically including: By detecting the contour curve and corner points of each separated key circuit component image, the geometric features of the key circuit component image are calculated to identify the shape; Measure the size of the key circuit component image, convert the size measurement result into an actual size by pixel ratio, and calibrate the actual size based on the resolution of the image and a preset reference size to obtain a size value; Analyze the wires and connection points in the circuit high-definition image, and use a path tracing algorithm to identify the wire connection path and its starting and ending points, so as to analyze and obtain the connection mode between each of the key circuit elements; Based on the obtained information of shape, size value and connection mode, a feature vector is constructed for each key circuit element.

4. The method for generating an image recognition model according to claim 3, It is characterized in that and converting the key information into graphic symbols to form a characteristic symbol set; Specifically include: Designing a set of graphic symbols based on the characteristic vectors of the key circuit elements, and incorporating functional attributes of the key circuit elements into the graphic symbols; Determine the association between different key circuit components, divide them into associated component groups and unassociated component groups, and set connection marks between the graphic symbols of the associated component groups to establish visual links; All of the graphic symbols are summarized to form a characteristic symbol set.

5. The method for generating an image recognition model according to claim 4, It is characterized in that The design of a basic framework for simulating chip circuit structure, inputting the characteristic symbol set into the basic framework, and arranging and combining corresponding graphic symbols to simulate the circuit layout of each chip; specifically includes: Designing a basic framework for simulating chip circuit structure according to the specifications of each chip, and inputting the characteristic symbol set into the basic framework; Based on the key circuit component images separated from the circuit high-definition image of each chip, and in combination with the mapping relationship between the key circuit components and the graphic symbols, the corresponding type of graphic symbols are selected from the characteristic symbol set, and the quantity of each graphic symbol is set; Using an automatic layout algorithm to arrange and combine the selected graphic symbols in the basic framework, simulating the circuit layout of each chip; The shortest connection path and the optimal layout of components of the circuit layout are set by using an optimization mechanism to obtain an optimized circuit layout.

6. The method for generating an image recognition model according to claim 1, It is characterized in that The step of synthesizing the simulated circuit layout with the corresponding background image to generate multiple sets of new circuit structure images, and inputting the new circuit structure images as training data into the basic processing model for training to obtain an image recognition model, specifically includes: Using an image synthesis algorithm to fuse the simulated circuit layout into the corresponding background image, generating multiple sets of new circuit structure images, and marking key circuit components in the new circuit structure images; A convolutional neural network is selected as a basic processing model, and multiple groups of new circuit structure images are sequentially input into the basic processing model for model training, and the trained basic processing model is used as an image recognition model.

7. The method for generating an image recognition model according to claim 1, It is characterized in that The step of obtaining the image recognition model further comprises: A high-definition circuit image of a chip in a verification set is input into the image recognition model, the recognition performance of the image recognition model is evaluated, and parameters of the image recognition model are adjusted according to the performance evaluation results to obtain an optimized image recognition model.

8. A system for generating an image recognition model, It is characterized in that A method for generating an image recognition model according to any one of claims 1 to 7, wherein the generating system comprises: An image acquisition unit, used to obtain high-definition circuit images of various sample chips; The image processing module includes a separation unit and a feature extraction unit, wherein the separation unit is used to separate the key circuit components from the background area in the collected circuit high-definition image of each chip to obtain a key circuit component image and a corresponding background image; the feature extraction unit is used to perform feature extraction on the separated key circuit component image to obtain key information on the shape, size value and connection mode of the key circuit component; A symbolization module, used for converting the key information into graphic symbols to form a characteristic symbol set; A circuit simulation unit, used to input the characteristic symbol set in the basic framework, and arrange and combine the corresponding graphic symbols to simulate the circuit layout of each chip; An image synthesis unit, used for synthesizing the simulated circuit layout with the corresponding background image to generate multiple sets of new circuit structure images; A basic processing model for generating an image recognition model based on multiple sets of new circuit structure images as training data; The display unit is used to display the simulated circuit layout.

9. A chip for an image recognition model, It is characterized in that The method comprises a memory and at least one processor, wherein the memory stores instructions; The processor calls the instruction in the memory so that the processor executes the method for generating an image recognition model as described in any one of claims 1 to 7.

10. A memory, It is characterized in that The memory stores instructions for implementing the method for generating an image recognition model as claimed in any one of claims 1 to 7.

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