Processor Based on Chiplet Technology, Its Operating Method, Electronic Device, and Medium

Abstract

The present application relates to a processor based on chiplet technology, its operating method, an electronic device, and a medium, including: a chiplet module, including a plurality of first chiplet units, at least one first chiplet unit for supporting a first instruction set architecture, and at least one first chiplet unit for supporting a second instruction set architecture; wherein, the first instruction set architecture is different from the second instruction set architecture. By using chiplet technology to implement at least two chiplet units supporting different instruction set architectures within the same processor, on the one hand, the integration degree of the processor can be improved, which helps to reduce the overall size and manufacturing cost of the device and improve the performance of the processor. On the other hand, the first chiplet units can be combined according to different application scenarios, so that when the processor faces different application scenarios, it can flexibly adapt to different instruction set requirements, improve the application flexibility of the processor, and ensure the compatibility of the processor with different software and application ecosystems.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and particularly to a processor based on chiplet technology, a running method thereof, an electronic device, and a medium. Background Art

[0002] When a processor product selects a specific instruction set architecture scheme during architecture design, the processor cannot directly run software and application ecosystems designed for other instruction set architectures, resulting in the processor being unable to meet the requirements of multiple application scenarios and having poor application flexibility. Summary of the Invention

[0003] Based on this, it is necessary to provide a processor based on chiplet technology, a running method thereof, an electronic device, and a medium for the problem that processors supporting specific instruction set architectures in the prior art cannot directly run software and application ecosystems designed for other instruction set architectures and have poor application flexibility.

[0004] To achieve the above object, the present application provides a processor based on chiplet technology, including:

[0005] A chiplet module, including a plurality of first chiplet units, at least one of the first chiplet units being configured to support a first instruction set architecture, and at least one of the first chiplet units being configured to support a second instruction set architecture;

[0006] Wherein, the first instruction set architecture is different from the second instruction set architecture.

[0007] In one embodiment, each of the first chiplet units is configured with a first interface, and the chiplet module further includes:

[0008] A second chiplet unit, configured with a plurality of second interfaces, the plurality of second interfaces being respectively connected to the first interfaces of the plurality of first chiplet units in a corresponding manner;

[0009] Wherein, any two first chiplet units are connected to each other through the second chiplet unit.

[0010] In one embodiment, each of the first chiplet units is configured with a first interface, and any two first chiplet units are connected to each other through the first interface.

[0011] In one embodiment, it further includes:

[0012] A control module, connected to the chiplet module, for scheduling the tasks of the processor to the target chiplet unit corresponding to the tasks;

[0013] Wherein, the tasks correspond to the target instruction set architecture, and the target chiplet unit is at least one of the plurality of first chiplet units.

[0014] In one embodiment, the control module is further configured to turn off the remaining first die units except the target die unit when the processor runs a task corresponding to the target instruction set architecture.

[0015] In one embodiment, the instruction set architecture includes, but is not limited to, at least one of ARM instruction set architecture, X86 instruction set architecture, RISC-V instruction set architecture, MIPS instruction set architecture, and LoongArch instruction set architecture.

[0016] In one embodiment, an electronic device is provided, including the processor as described above.

[0017] In one embodiment, a method for operating a processor based on die technology is provided, including:

[0018] Providing a processor based on die technology, the processor including a die module, the die module including a plurality of first die units, at least one first die unit being configured to support a first instruction set architecture, and at least one first die unit being configured to support a second instruction set architecture, the first instruction set architecture being different from the second instruction set architecture;

[0019] Scheduling a task of the processor to a target die unit corresponding to the task;

[0020] wherein the task corresponds to a target instruction set architecture, and the target die unit is at least one of the plurality of first die units.

[0021] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0022] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0023] The above-mentioned processor based on chiplet technology, its operating method, electronic device, and medium set a chiplet module in the processor. The chiplet module includes multiple first chiplet units, and there is at least one first instruction set architecture supported by the first chiplet unit that is different from the second instruction set architecture supported by at least one first chiplet unit. Implementing at least two chiplet units supporting different instruction set architectures in the same processor by using chiplet technology can, on the one hand, improve the integration of the processor, help reduce the overall size and manufacturing cost of the device, and improve the performance of the processor. On the other hand, the first chiplet units can be combined according to different application scenarios, enabling the processor to flexibly adapt to different instruction set requirements when facing different application scenarios, improving the application flexibility of the processor, and ensuring the compatibility of the processor with different software and application ecosystems. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0025] Figure 1 FIG. 1 is one of the schematic structural diagrams of the processor provided in an embodiment;

[0026] Figure 2 FIG. 2 is another schematic structural diagram of the processor provided in an embodiment;

[0027] Figure 3 FIG. 3 is yet another schematic structural diagram of the processor provided in an embodiment;

[0028] Figure 4 FIG. 4 is a schematic flowchart of the method for operating the processor provided in an embodiment.

[0029] DESCRIPTION OF THE REFERENCE NUMERALS:

[0030] Processor: 10; First chiplet unit: 110; Second chiplet unit: 120. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0033] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0034] In one embodiment, referring to Figure 1 , a processor 10 based on chiplet technology is provided, including a chiplet module.

[0035] The chiplet module includes a plurality of first chiplet units 110. At least one first chiplet unit 110 is used to support a first instruction set architecture, and at least one first chiplet unit 110 is used to support a second instruction set architecture. Among them, the first instruction set architecture is different from the second instruction set architecture.

[0036] Among them, the processor 10 is also called a Central Processing Unit (CPU), which is one of the core components in a computer system. Its main functions include executing instructions in a computer program, performing arithmetic and logical operations, controlling and coordinating the work of various hardware components within the system, and managing data streams. In short, the processor 10 is the brain of the computer, responsible for processing and executing various tasks.

[0037] The Instruction Set Architecture (ISA), as a part of the computer architecture, is one of the most important technical solutions for the processor 10. It defines the set of instructions that the computer processor 10 can understand and execute, as well as the formats and operation methods of these instructions. For example, the instruction set architecture defines the specific instructions that the processor 10 can execute, and each instruction corresponds to a basic operation, such as addition, multiplication, loading data, etc. The instruction set architecture specifies the set of registers inside the processor 10, and these registers are used to store instructions and data. The instruction set architecture stipulates the number, uses, and operations between registers, and stipulates the supported data types, such as integers, floating-point numbers, etc. Each data type has corresponding instructions for operating on these data. The instruction set architecture determines how the processor 10 accesses data in memory, including direct addressing, indirect addressing, relative addressing, etc., and stipulates the binary representation form of each instruction, including opcode, register address, immediate number, etc. The programs written by software developers are converted into machine codes of the corresponding instruction set by the compiler, and the processor 10 executes these machine codes according to the instruction set. Therefore, different instruction set architectures have different application scenarios and software ecosystems. For example, the X86 architecture originated from the personal computer application scenario, and its corresponding software ecosystem is the Windows operating system. The ARM architecture dominates in mobile application scenarios such as mobile devices (such as smartphones and tablets), and its corresponding software ecosystem is the Android operating system. Therefore, different instruction set architectures and software ecosystems have specific characteristics in design and optimization to meet the needs of specific application scenarios.

[0038] Since the design of the processor 10 needs to conform to specific instruction set architecture specifications to ensure compatibility with the corresponding software and operating systems, in related technologies, the processor 10 product needs to select an ISA solution during architecture design. Once a certain ISA is selected, then it can be compatible with software and application ecosystems that support this ISA very well. At the same time, the processor 10 cannot support software and application ecosystems of other ISAs. For example, a processor 10 that only supports the X86 architecture cannot directly run software and application ecosystems designed for the ARM architecture.

[0039] With the development of artificial intelligence, upper-layer applications show a trend of integration and collaboration. For example, the seamless switching and integration between PCs and mobile phones, and the collaboration between cloud computing and edge computing. There are application requirements in the same application field to support multiple ISAs. For example, in the PC application field, it is necessary to support both X86 and ARM ISAs at the same time. In the data center field, it is necessary to support both X86 and ARM ISAs at the same time. In the field of artificial intelligence and the Internet of Things (AIoT), it is necessary to support ISAs such as ARM and RISC-V at the same time. Therefore, this embodiment provides a processor 10 to meet the requirements of different application scenarios for multiple instruction set architectures.

[0040] Among them, this embodiment uses the Chiplet technology to support at least two instruction set architectures in one processor 10 at the same time. The Chiplet technology is a method of designing and manufacturing integrated circuits, in which a chip is split into smaller independent units, and each unit usually contains a specific function or component. These small units (Chiplets) can be interconnected through the interconnection structure on the chip to form a complete integrated circuit. Therefore, each first Chiplet unit 110 in the Chiplet module is an independent processing unit, and at least one first Chiplet unit 110 is designed to support the first instruction set architecture, while at least one first Chiplet unit 110 is designed to support the second instruction set architecture. The first instruction set architecture and the second instruction set architecture are different. On the one hand, it is possible to integrate multiple different instruction set architectures in the same processor 10, and then flexibly combine them into different processor chip products according to different application scenarios, so as to be compatible with the software and application ecosystems corresponding to different application scenarios, and provide better performance, power consumption efficiency or adaptability. On the other hand, the Chiplet technology allows designers to more easily combine Chiplet units that support different instruction set architectures to adapt to different application scenarios, and the Chiplet units designed using the Chiplet technology can reduce the manufacturing cost of the entire processor chip, and make it more convenient to perform local upgrades without changing the overall chip structure, which is beneficial to technology upgrade and maintenance. Compared with the prior art solution that uses processor micro-architecture design technology to support multiple instruction set architectures, there are problems such as large area cost, complex implementation, high cost, and complex and inflexible applications. This embodiment uses the Chiplet technology to design multiple first Chiplet units 110 to support at least two different instruction set architectures, which can not only avoid the increase in chip area, but also improve chip performance, reduce power consumption and manufacturing costs.

[0041] It should be noted that the types of instruction set architectures supported by multiple first die units 110 are at least two. Among them, the same instruction set architecture can be jointly implemented by at least two first die units 110, and the same instruction set architecture can also be directly implemented by a single first die unit 110. At least two first die units 110 can also be designed to support the same instruction set architecture respectively to provide alternative dies in case of failure. In this embodiment, at least two first die units 110 that support different instruction set architectures need to be designed. When facing application scenarios with different instruction set architectures, the corresponding first die unit 110 can be flexibly called according to the type of the instruction set architecture, so as to run the software and application ecosystem designed for the instruction set architecture corresponding to the current application scenario.

[0042] Optionally, the types of instruction set architectures supported by the first die unit 110 can be at least one of the ARM instruction set architecture, the X86 instruction set architecture, the RISC-V instruction set architecture, the MIPS instruction set architecture, and the LoongArch instruction set architecture.

[0043] In the above embodiment, a die module is arranged in the processor 10. The die module includes multiple first die units 110. There is at least one first instruction set architecture supported by at least one first die unit 110 that is different from the second instruction set architecture supported by at least one first die unit 110. By using die technology, at least two first die units 110 that support different instruction set architectures are arranged in the same processor 10. On the one hand, the integration degree of the processor 10 can be improved, which helps to reduce the overall size and manufacturing cost of the device and improve the performance of the processor 10. On the other hand, the first die units 110 can be combined according to different application scenarios, so that when the processor 10 faces different application scenarios, it can flexibly adapt to different instruction set requirements, improve the application flexibility of the processor 10, and ensure the compatibility of the processor 10 with different software and application ecosystems.

[0044] In one embodiment, as Figure 2 shown, each of the first die units 110 is configured with a first interface. The die module further includes: a second die unit 120.

[0045] The second die unit 120 is configured with multiple second interfaces, and the multiple second interfaces are respectively connected to the first interfaces of the multiple first die units 110 correspondingly. Among them, any two first die units 110 are connected to each other through the second die unit 120.

[0046] Among them, the second die unit 120 serves as an input / output (I / O) die, which has a plurality of second interfaces, and each second interface is correspondingly connected to a first interface of a first die unit 110. On the one hand, the second die unit 120 acts as an intermediary between a plurality of first die units 110. The first die units 110 can communicate with external devices or other system components through the second die unit 120, and direct communication can also be carried out between the plurality of first die units 110, which helps to achieve more flexible data exchange and collaborative work. On the other hand, by designing the second die unit 120 to connect a plurality of first die units 110, more interfaces can be implemented in the second die unit 120 to be compatible with connecting more first die units 110 implementing specific instruction set architectures, so as to flexibly cope with more complex application scenarios.

[0047] In one embodiment, as Figure 3 shown, each of the first die units 110 is configured with a first interface, and any two first die units 110 are connected to each other through the first interface. It can be understood that each first die unit 110 is designed with a first interface to establish a connection between different first die units 110, which can make the chip architecture simpler and have a lower cost for specific application scenarios.

[0048] In one embodiment, the processor further includes: a control module.

[0049] The control module is connected to the die module, and the control module is used to schedule the tasks of the processor to the target die unit corresponding to the task. Among them, the task corresponds to the target instruction set architecture, and the target die unit is at least one of the plurality of first die units.

[0050] Among them, the processor has different tasks in the face of different application scenarios, that is, the tasks of the processor are related to the type of instruction set architecture. The control module is responsible for scheduling the tasks of the processor to the target die unit corresponding to the task, so as to effectively manage the execution of the tasks to ensure that the tasks of the processor are effectively allocated to the target die units that meet the requirements of their instruction set architecture.

[0051] In one embodiment, the control module is further used to turn off the remaining first die units except the target die unit when the processor runs a task corresponding to the target instruction set architecture. Among them, the control module flexibly manages the states of other first die units during task execution, and can turn off the remaining first die units except the target die unit. When the processor executes a task corresponding to the target instruction set architecture, the other unused first die units will be turned off to reduce power consumption and improve system efficiency.

[0052] In one embodiment, the instruction set architecture includes, but is not limited to, at least one of the ARM instruction set architecture, the X86 instruction set architecture, the RISC-V instruction set architecture, the MIPS instruction set architecture, and the LoongArch instruction set architecture. Among them, ARM (Advanced RISC Machines) is a reduced instruction set computer (RISC) architecture designed for low-power and high-performance embedded systems and mobile devices, and is widely used in smartphones, tablets, Internet of Things devices, and embedded systems. X86 is a complex instruction set computer (CISC) architecture that originated in the personal computer field. It includes a rich instruction set and complex instruction formats and is mainly used in desktop and server computers, including processors from Intel and AMD. RISC-V is an open RISC architecture with a simple and clear instruction set that supports scalability and flexibility and is widely used in open-source projects, embedded systems, Internet of Things devices, and some high-performance computing fields. MIPS (Microprocessor without Interlocked Pipeline Stages) is a RISC architecture known for its simple and efficient design. These instruction set architectures play important roles in different application fields and markets, each with its unique characteristics and advantages, suitable for different computing requirements. The processor of the present application can flexibly combine first die units that support different instruction set architectures to be compatible with different instruction set architectures required by different application scenarios.

[0053] In one embodiment, an electronic device is provided, including the processor provided in the above embodiment. It can be understood that since the electronic device uses the processor provided in the above embodiment, when the performance of the processor is higher than that of a traditional processor, the working performance of the corresponding electronic device also improves accordingly.

[0054] In one embodiment, as Figure 4 shown, a method for operating a processor based on die technology is provided, including step S102 to step S104.

[0055] Step S102: Provide a processor based on die technology, where the processor includes a die module, the die module includes a plurality of first die units, at least one first die unit is used to support a first instruction set architecture, and at least one first die unit is used to support a second instruction set architecture, and the first instruction set architecture is different from the second instruction set architecture.

[0056] Please refer to the relevant descriptions in the above embodiment for step S102, and details will not be elaborated here.

[0057] Step S104: Schedule the tasks of the processor to the target die units corresponding to the tasks. Among them, the tasks correspond to the target instruction set architecture, and the target die units are at least one of the multiple first die units.

[0058] For the description of step S104, please refer to the relevant description in the above embodiments and will not be elaborated here.

[0059] The processor operation method provided in this embodiment sets a die module in the processor. The die module includes multiple first die units. There is at least one first die unit that supports a first instruction set architecture different from the second instruction set architecture supported by at least one first die unit, and schedules the tasks of the processor to the target die units corresponding to the tasks. By using die technology, die units that can support at least two instruction set architectures are set within the same processor. On the one hand, it can improve the integration of the processor, help reduce the overall size and manufacturing cost of the device, and improve the performance of the processor. On the other hand, the first die units can be combined according to different application scenarios, so that when the processor faces different application scenarios, it can flexibly adapt to different instruction set requirements, improve the application flexibility of the processor, and ensure the compatibility of the processor with different software and application ecosystems.

[0060] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0061] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the method provided in the above embodiment are implemented.

[0062] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0063] Any reference to memory, storage, database, or other media used in this application may include non-volatile and / or volatile memory. Suitable non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which serves as an external cache. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

[0064] It should be understood that although the steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless specifically stated herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowchart may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0065] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0066] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0067] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A processor based on chiplet technology, characterized in that, Comprising: A die module, including a plurality of first die units, at least one first die unit for supporting a first instruction set architecture, and at least one first die unit for supporting a second instruction set architecture; Wherein, the first instruction set architecture is different from the second instruction set architecture; Each of the first die units is configured with a first interface, and any two of the first die units are connected to each other through the first interface; The die module further includes: A second die unit, configured with a plurality of second interfaces, and the plurality of second interfaces are respectively connected to the first interfaces of the plurality of first die units in a corresponding manner; Wherein, any two first die units are connected to each other through the second die unit, the second die unit acts as a mediator between the plurality of first die units, the first die unit can communicate with external devices or other system components through the second die unit, and direct communication can also be carried out between the plurality of first die units. By designing the second die unit to connect the plurality of first die units, more interfaces are implemented in the second die unit; Further comprising: A control module, connected to the die module, for scheduling the tasks of the processor to the target die unit corresponding to the task; Wherein, the task corresponds to a target instruction set architecture, and the target die unit is at least one of the plurality of first die units; The control module is further configured to turn off the remaining first die units except the target die unit when the processor runs a task corresponding to the target instruction set architecture.

2. The processor according to claim 1, wherein The instruction set architecture includes but is not limited to at least one of the ARM instruction set architecture, the X86 instruction set architecture, the RISC-V instruction set architecture, the MIPS instruction set architecture, and the LoongArch instruction set architecture.

3. An electronic device, characterized in that, Including the processor according to any one of claims 1 to 2.

4. A method for operating a processor based on chiplet technology, characterized in that, Comprising: Providing a processor based on die technology, the processor including a die module, the die module including a plurality of first die units, at least one first die unit for supporting a first instruction set architecture, and at least one first die unit for supporting a second instruction set architecture, the first instruction set architecture being different from the second instruction set architecture, each of the first die units being configured with a first interface, and any two of the first die units being connected to each other through the first interface; The die module further includes: A second die unit, configured with a plurality of second interfaces, and the plurality of second interfaces are respectively connected to the first interfaces of the plurality of first die units in a corresponding manner; Wherein, any two first die units are connected to each other through the second die unit, the second die unit acts as a mediator between the plurality of first die units, the first die unit can communicate with external devices or other system components through the second die unit, and direct communication can also be carried out between the plurality of first die units. By designing the second die unit to connect the plurality of first die units, more interfaces are implemented in the second die unit; Scheduling the tasks of the processor to the target die unit corresponding to the task; Wherein, the task corresponds to the target instruction set architecture, and the target die unit is at least one of the plurality of first die units; The method further includes: When the processor runs a task corresponding to the target instruction set architecture, turning off the remaining first die units except the target die unit.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to claim 4 are implemented.

6. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method according to claim 4 are implemented.

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