Semiconductor structure preparation method, semiconductor structure, device and equipment

Abstract

The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus, the method comprising: forming an active structure on a substrate; forming a front device layer of a front transistor based on the front active structure; performing a back process on the front device layer to form a front interconnection layer; electrically connecting any two interconnection layers among a first front interconnection layer, a second front interconnection layer and a third front interconnection layer; flipping the wafer and removing the substrate; forming a back device layer of a back transistor based on the back active structure; performing a back process on the back device layer to form a back interconnection layer; electrically connecting any two interconnection layers among a first back interconnection layer, a second back interconnection layer and a third back interconnection layer. Through the present application, the space utilization rate of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] In an integrated circuit, a standard cell is composed of several transistors and is a basic unit with specific logical functions. The interconnection between multiple standard cells plays an important role in realizing more complex circuit functions. At present, the interconnection between multiple standard cells is realized through single-sided routing, that is, the interconnection metal wires are arranged on the front side of the transistor. This has the disadvantages of less routing space, greater design difficulty, and more space waste when the density of transistors is increasing and gradually shifting towards three-dimensional stacking. Summary of the invention

[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to improve the space utilization rate of the semiconductor structure.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure includes a front transistor and a back transistor arranged back to back, the front transistor and the back transistor are self-aligned in a direction perpendicular to the active area, the front transistor includes a first front transistor, a second front transistor and a third front transistor, and the back transistor includes a first back transistor, a second back transistor and a third back transistor; wherein the first front transistor is adjacent to the second front transistor along a first direction, the first front transistor is adjacent to the third front transistor along a second direction, the first direction is perpendicular to the second direction, the first back transistor is adjacent to the second back transistor along the first direction, and the first back transistor is adjacent to the third back transistor along the second direction; the above method includes: forming an active structure on a substrate; the active structure includes a front active structure and a back active structure; based on the front active structure, forming a front device layer of the front transistor; the front device layer includes a front source-drain structure, a front gate junction structure, a front interlayer dielectric layer and a front source-drain metal; performing a back-end process on the front device layer to form a front interconnection layer; the front interconnection layer includes a first front interconnection layer corresponding to the first front transistor, a second front interconnection layer corresponding to the second front transistor and a third front interconnection layer corresponding to the third front transistor, and any two of the first front interconnection layer, the second front interconnection layer and the third front interconnection layer are electrically connected; flipping the wafer and removing the substrate; forming a back device layer of the back transistor based on the back active structure; the back device layer includes a back source-drain structure, a back gate structure, a back interlayer dielectric layer and a back source-drain metal; performing a back-end process on the back device layer to form a back interconnection layer; the back interconnection layer includes a first back interconnection layer corresponding to the first back transistor, a second back interconnection layer corresponding to the second back transistor and a third back interconnection layer corresponding to the third back transistor, and any two of the first back interconnection layer, the second back interconnection layer and the third back interconnection layer are electrically connected.

[0005] In some possible embodiments, when the first front interconnection layer and the third front interconnection layer are electrically connected, the front interconnection layer includes a front gate interconnection metal, a front source-drain interconnection metal, a front first metal (metal 0, M0), and a front second metal (metal 1, M1); a back-end process is performed on the front device layer to form a front interconnection layer, including: depositing an insulating material on the front device layer to form a first front dielectric layer; forming a front gate interconnection metal and a front source-drain interconnection metal in the first front dielectric layer; the gate interconnection metal connects the front gate structure, and the source-drain interconnection metal connects the front source-drain metal; depositing an insulating material on the first front dielectric layer to form a second front dielectric layer; forming a front M0 in the second front dielectric layer; the front M0 is used to connect the front device layer and the front interconnection layer; depositing an insulating material on the second front dielectric layer to form a third front dielectric layer; forming a front M1 in the third front dielectric layer; wherein the first front interconnection layer and the third front interconnection layer are electrically connected via the front M1 or the front M0.

[0006] In some possible embodiments, a front gate interconnection metal and a front source-drain interconnection metal are formed in a first front dielectric layer, including: performing photolithography on the first front dielectric layer to form a front gate interconnection groove and a front source-drain interconnection groove; filling the front gate interconnection groove and the front source-drain interconnection groove with metal material to form a front gate interconnection metal and a front source-drain interconnection metal.

[0007] In some possible implementations, forming the front M0 in the second front dielectric layer includes: performing photolithography on the second front dielectric layer to form a front M0 groove; and filling a metal material in the front M0 groove to form the front M0.

[0008] In some possible implementations, forming the front side M1 in the third front side dielectric layer includes: performing photolithography on the third front side dielectric layer to form a front side M1 groove; and filling a metal material in the front side M1 groove to form the front side M1.

[0009] In some possible embodiments, when the first back interconnection layer and the second back interconnection layer are electrically connected, the back interconnection layer includes a back gate interconnection metal, a back source-drain interconnection metal, a back M0, and a back M1; a back-end process is performed on the back device layer to form a back interconnection layer, including: depositing an insulating material on the back device layer to form a first back dielectric layer; forming a back gate interconnection metal and a back source-drain interconnection metal in the first back dielectric layer; the back gate interconnection metal connects the back gate structure, and the back source-drain interconnection metal connects the back source-drain metal; depositing an insulating material on the first back dielectric layer to form a second back dielectric layer; forming a back M0 in the second back dielectric layer; the back M0 is used to connect the back device layer and the back interconnection layer; depositing an insulating material on the second back dielectric layer to form a third back dielectric layer; forming a back M1 in the third back dielectric layer; wherein the first back interconnection layer and the second back interconnection layer are electrically connected via the back M0 or the back M1.

[0010] In some possible embodiments, a back gate interconnection metal and a back source-drain interconnection metal are formed in the first back dielectric layer, including: performing photolithography on the first back dielectric layer to form a back gate interconnection groove and a back source-drain interconnection groove; filling the back gate interconnection groove and the back source-drain interconnection groove with metal material to form a back gate interconnection metal and a back source-drain interconnection metal.

[0011] In some possible implementations, forming a back side M0 in the second back side dielectric layer includes: performing photolithography on the second back side dielectric layer to form a back side M0 groove; and filling a metal material in the back side M0 groove to form the back side M0.

[0012] In some possible implementations, forming the back side M1 in the third back side dielectric layer includes: performing photolithography on the third back side dielectric layer to form a back side M1 groove; and filling a metal material in the back side M1 groove to form the back side M1.

[0013] In some possible embodiments, the front device layer also includes a front source and drain metal via; based on the front active structure, a front device layer of the front transistor is formed, including: depositing insulating material on the active structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the active structure; removing a portion of the shallow trench isolation structure that wraps the front active structure to expose the front active structure; based on the front active structure, a front source and drain structure is formed; depositing semiconductor material on the front active structure and the front source and drain structure to form a front interlayer dielectric layer; forming a front source and drain metal on the front source and drain structure; etching a first portion of the front interlayer dielectric layer to form a front source and drain metal via; the front source and drain metal via is located on the side of the front source and drain metal and extends in the direction toward the back active structure.

[0014] In some possible embodiments, the back device layer also includes a back source and drain metal via; based on the back active structure, a back device layer of the back transistor is formed, including: removing a portion of the shallow trench isolation structure that wraps the back active structure to expose the back active structure; based on the back active structure, a back source and drain structure is formed; semiconductor material is deposited on the back active structure and the back source and drain structure to form a back interlayer dielectric layer; a back source and drain metal is formed on the back source and drain structure; a second portion of the back interlayer dielectric layer and a third portion of the front interlayer dielectric layer are etched to form a back source and drain metal via; the back source and drain metal via is located on the side of the back source and drain metal and extends in a direction toward the front source and drain metal via; the projections of the first portion, the second portion, and the third portion on the front interconnect layer overlap, and the front source and drain metal via is connected to the back source and drain metal via.

[0015] In some possible embodiments, etching a first portion of the front interlayer dielectric layer to form a front source / drain metal via includes: forming a first groove by etching the first portion of the front interlayer dielectric layer; filling the first groove with a metal material to form a front source / drain metal via; etching a second portion of the back interlayer dielectric layer and a third portion of the front interlayer dielectric layer to form a back source / drain metal via, including: forming a second groove and exposing a surface of the front source / drain metal via close to the back active structure by etching the second portion of the back interlayer dielectric layer and the third portion of the front interlayer dielectric layer; filling the second groove with a metal material to form a back source / drain metal via.

[0016] In a second aspect, an embodiment of the present application provides a semiconductor structure, the semiconductor structure comprising: a front transistor; the front transistor comprises a first front transistor, a second front transistor and a third front transistor; a back transistor; the back transistor comprises a first back transistor, a second back transistor and a third back transistor; the front transistor and the back transistor are self-aligned in a direction perpendicular to the active area; wherein any two interconnection layers of the first front interconnection layer of the first front transistor, the second front interconnection layer of the second front transistor and the third front interconnection layer of the third front transistor are electrically connected; any two interconnection layers of the first back interconnection layer of the first back transistor, the second back interconnection layer of the second back transistor and the third back interconnection layer of the third back transistor are electrically connected.

[0017] In some possible embodiments, when the first front interconnection layer is electrically connected to the third front interconnection layer, the first front interconnection layer is electrically connected to the third front interconnection layer through the front second metal M1 or the front first metal M0; when the first back interconnection layer is electrically connected to the second back interconnection layer, the first back interconnection layer is electrically connected to the second back interconnection layer through the back M0 or the back M1.

[0018] In some possible embodiments, the front transistor includes a front source and drain metal and a front source and drain metal through-hole connected to the front source and drain metal; the front source and drain metal through-hole is arranged on the side of the front source and drain metal; the back transistor includes a back source and drain metal and a back source and drain metal through-hole connected to the back source and drain metal; the back source and drain metal through-hole is arranged on the side of the back source and drain metal; wherein, the front source and drain metal through-hole extends in the direction toward the back transistor, the back source and drain metal through-hole extends in the direction toward the front transistor, and the front source and drain metal through-hole is connected to the back source and drain metal through-hole.

[0019] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0020] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0021] In the present application, in the front transistor, any two of the first front interconnection layer, the second front interconnection layer and the third front interconnection layer are electrically connected, and in the back transistor, any two of the first back interconnection layer, the second back interconnection layer and the third back interconnection layer are electrically connected; in this way, interconnection between adjacent units can be achieved in the semiconductor structure, thereby improving the space utilization of the semiconductor structure.

[0022] Furthermore, since the front source-drain metal vias and the back source-drain metal vias in the semiconductor structure are connected, and the front source-drain metal vias are connected to the front source-drain metal, and the back source-drain metal vias are connected to the back source-drain metal, the source-drain interconnection between the front transistor and the back transistor can be achieved.

[0023] Furthermore, on the basis of the source-drain interconnection between the front transistor and the back transistor, through the interconnection of the front interconnection layer of the front transistor (that is, any two of the first front interconnection layer, the second front interconnection layer and the third front interconnection layer are electrically connected) and the interconnection of the back interconnection layer of the back transistor (that is, any two of the first back interconnection layer, the second back interconnection layer and the third back interconnection layer are electrically connected), the output signal can be brought out on the front and back sides of the semiconductor structure, and electrical interconnection between standard units can be achieved by double-sided routing, further improving space utilization and reducing wiring difficulty.

[0024] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0026] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0027] Figure 2A and Figure 2B A schematic diagram of a semiconductor structure in an embodiment of the present application;

[0028] FIG. 3A to FIG. 3E A schematic diagram of a preparation process of a semiconductor structure in an embodiment of the present application;

[0029] The above pictures:

[0030] 10. semiconductor structure; 11. front transistor; 111. first front transistor; 112. second front transistor; 113. third front transistor; 1111. first front interconnection layer; 1131. third front interconnection layer; 12. back transistor; 121. first back transistor; 122. second back transistor; 123. third back transistor; 1211. first back interconnection layer; 1221. second back interconnection layer; 13. insulating layer; 14. wafer carrier; 21. substrate; 22. fin structure; 23. shallow trench isolation structure; 231. shallow trench isolation layer; 241. front adjacent device isolation layer; 242. back adjacent device isolation layer; 31. front active structure; 32. front source and drain structure; 33. front interlayer dielectric layer; 34. front spacer; 35. front gate structure; 36. front source and drain Metal; 37, front source and drain metal vias; 41, back active structure; 42, back source and drain structure; 43, back interlayer dielectric layer; 44, back spacer; 45, back gate structure; 46, back source and drain metal; 47, back source and drain metal vias; 51, first front dielectric layer; 52, second front dielectric layer; 53, third front dielectric layer; 54, fourth front dielectric layer; 511, front gate interconnection metal; 512, front source and drain interconnection metal; 521, front M0; 531, front M1; 541, front interconnection metal; 61, first back dielectric layer; 62, second back dielectric layer; 63, third back dielectric layer; 64, fourth back dielectric layer; 611, back gate interconnection metal; 612, back source and drain interconnection metal; 621, back M0; 631, back M1; 641, back interconnection metal. DETAILED DESCRIPTION

[0031] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0032] As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0033] In an integrated circuit, a standard cell is composed of several transistors and is a basic unit with specific logical functions. The interconnection between multiple standard cells plays an important role in realizing more complex circuit functions. At present, the interconnection between multiple standard cells is realized through single-sided routing, that is, the interconnection metal wires are arranged on the front side of the transistor. This has the disadvantages of less routing space, greater design difficulty, and more space waste when the density of transistors is increasing and gradually shifting towards three-dimensional stacking.

[0034] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to improve the space utilization rate of the semiconductor structure.

[0035] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0036] In the embodiment of the present application, the front transistor and the back transistor in the semiconductor structure can be transistors of the same type, such as any of the following: a fin field effect transistor, a nanosheet field effect transistor, a planar transistor, and a vertical field effect transistor.

[0037] In an embodiment of the present application, the semiconductor structure includes a front transistor and a back transistor arranged back to back, the front transistor and the back transistor are self-aligned in a direction perpendicular to the active area, the front transistor includes a first front transistor, a second front transistor and a third front transistor, and the back transistor includes a first back transistor, a second back transistor and a third back transistor; wherein the first front transistor and the second front transistor are arranged adjacent to each other along a first direction, the first front transistor and the third front transistor are arranged adjacent to each other along a second direction, the first direction is perpendicular to the second direction, the first back transistor and the second back transistor are arranged adjacent to each other along the first direction, and the first back transistor and the third back transistor are arranged adjacent to each other along the second direction. Figure 2A and Figure 2BThe semiconductor structure composed of fin field effect transistors is combined below Figure 2A and Figure 2B The semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application, see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0039] S101, forming an active structure on a substrate.

[0040] The active structure includes a front active structure and a back active structure.

[0041] It can be understood that, according to the division of the upper region and the lower region, the semiconductor structure includes a front transistor and a back transistor, and the front active structure in the front transistor and the back active structure in the back transistor are formed by the same process, so the active area of ​​the front transistor and the active area of ​​the back transistor are self-aligned. The self-alignment of the active area further enables the front transistor and the back transistor to be self-aligned in a direction perpendicular to the active area.

[0042] In the embodiment of the present application, the active region is a collective name for the source region, the drain region and the channel region.

[0043] In some embodiments, when the front transistor and the back transistor in the semiconductor structure are fin field effect transistors or planar transistors, the substrate is a single-layer structure. For example, the substrate may be a single-layer silicon (Si) material.

[0044] In other embodiments, when the front transistor and the back transistor in the semiconductor structure are nanosheet field effect transistors, the substrate is a stacked structure. For example, the substrate may be a stacked layer formed by alternately depositing silicon and silicon germanium (SiGe).

[0045] In some embodiments, when the front transistor and the back transistor in the semiconductor structure are fin-type field effect transistors, the active structure is a fin structure; when the front transistor and the back transistor in the semiconductor structure are nanosheet field effect transistors, the active structure is a nanosheet structure; when the front transistor and the back transistor in the semiconductor structure are planar transistors, the active structure is a block structure.

[0046] In the embodiment of the present application, since the semiconductor structure includes a front transistor and a back transistor, and the front active structure of the front transistor and the back active structure of the back transistor are formed by the same etching process, a larger etching depth can be used when etching the substrate. For example, the height of the fin structure (which may also be a columnar structure or a block structure) obtained by etching can be greater than 100nm. It should be noted that the height of the fin structure can be set according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0047] S102, forming a front device layer of the front transistor based on the front active structure.

[0048] Among them, the front device layer includes a front source and drain structure, a front gate structure, a front interlayer dielectric layer and a front source and drain metal.

[0049] It can be understood that in the process of preparing the semiconductor structure, the front transistor is first prepared based on the upper part of the active structure (i.e., the front active structure). After the front transistor is prepared, the front transistor is flipped so that the lower part of the active structure (i.e., the back active structure) is placed upward, and then the back transistor is prepared based on the lower part of the active structure.

[0050] In some embodiments, the front transistor is composed of a front device layer and a front interconnection layer; during the preparation process, a front-end process can be performed first to form the front device layer; then a back-end process can be performed on the front device layer to form a front interconnection layer.

[0051] S103, performing a back-end process on the front device layer to form a front interconnection layer.

[0052] Among them, the front interconnection layer includes a first front interconnection layer corresponding to the first front transistor, a second front interconnection layer corresponding to the second front transistor and a third front interconnection layer corresponding to the third front transistor, and any two of the first front interconnection layer, the second front interconnection layer and the third front interconnection layer are electrically connected.

[0053] It can be understood that, corresponding to the first front transistor, the second front transistor and the third front transistor, the front interconnection layer includes the first front interconnection layer, the second front interconnection layer and the third front interconnection layer. The front interconnection layer includes dielectric layers stacked in sequence, metal wires are buried in the dielectric layers, and any two interconnection layers among the first front interconnection layer, the second front interconnection layer and the third front interconnection layer can be electrically connected through the metal wires. For example, the first front interconnection layer and the second front interconnection layer are electrically connected, or the first front interconnection layer and the third front interconnection layer are electrically connected, or the second front interconnection layer and the third front interconnection layer are electrically connected.

[0054] S104, flipping the wafer and removing the substrate.

[0055] It can be understood that after the front transistor is prepared, the front transistor can be flipped and the substrate can be removed so that the back active structure is exposed, which is convenient for the subsequent preparation of the back transistor.

[0056] In some embodiments, before the above S104, the above method may further include: depositing an insulating material (such as silicon oxide) on the front interconnect layer to form an insulating layer, and bonding the insulating layer to the carrier wafer.

[0057] In the embodiment of the present application, the carrier wafer can provide physical support for the front transistor after being flipped over, thereby effectively preventing the front transistor from being broken by external force during the process of preparing the back transistor.

[0058] S105 , forming a back device layer of the back transistor based on the back active structure.

[0059] The back device layer includes a back source-drain structure, a back gate structure, a back interlayer dielectric layer and a back source-drain metal.

[0060] It can be understood that after the back active structure is exposed, a back transistor can be manufactured based on the back active structure according to standard steps for manufacturing transistors.

[0061] S106, performing a back-end process on the back device layer to form a back interconnection layer.

[0062] Among them, the back side interconnection layer includes a first back side interconnection layer corresponding to the first back side transistor, a second back side interconnection layer corresponding to the second back side transistor and a third back side interconnection layer corresponding to the third back side transistor, and any two of the first back side interconnection layer, the second back side interconnection layer and the third back side interconnection layer are electrically connected.

[0063] It can be understood that, corresponding to the first back side transistor, the second back side transistor and the third back side transistor, the back side interconnection layer includes the first back side interconnection layer, the second back side interconnection layer and the third back side interconnection layer. The back side interconnection layer includes dielectric layers stacked in sequence, metal wires are buried in the dielectric layers, and any two of the first back side interconnection layer, the second back side interconnection layer and the third back side interconnection layer can be electrically connected through the metal wires. For example, the first back side interconnection layer and the second back side interconnection layer are electrically connected, or the first back side interconnection layer and the third back side interconnection layer are electrically connected, or the second back side interconnection layer and the third back side interconnection layer are electrically connected.

[0064] In some possible embodiments, taking the electrical connection between the first front interconnection layer and the third front interconnection layer as an example, the front interconnection layer includes a front gate interconnection metal, a front source-drain interconnection metal, a front first metal, and a front second metal; the above S103 may include: depositing an insulating material on the front device layer to form a first front dielectric layer; forming a front gate interconnection metal and a front source-drain interconnection metal in the first front dielectric layer; the gate interconnection metal connects the front gate structure, and the front source-drain interconnection metal connects the front source-drain metal; depositing an insulating material on the first front dielectric layer to form a second front dielectric layer; forming a front M0 in the second front dielectric layer; the front M0 is used to connect the front device layer and the front interconnection layer; depositing an insulating material on the second front dielectric layer to form a third front dielectric layer; forming a front M1 in the third front dielectric layer; wherein the first front interconnection layer and the third front interconnection layer are electrically connected via the front M1 or the front M0.

[0065] It can be understood that the front interconnection layer is composed of a plurality of stacked dielectric layers (i.e., the first front dielectric layer, the second front dielectric layer, and the third front dielectric layer), and metal wires are buried in each dielectric layer. The metal wires are used for conduction between the various devices inside the front transistor, and can also be used for conduction between adjacent front transistors. Among them, the metal wires buried in the first front dielectric layer are the front gate interconnection metal and the front source-drain interconnection metal. The front gate interconnection metal is used to electrically connect the front gate structure, and the front source-drain interconnection metal is used to electrically connect the front source-drain metal; the metal wire buried in the second front dielectric layer is the front M0, and the front M0 is used to connect the front device layer and the front interconnection layer; the metal wire buried in the third front dielectric layer is the front M1. The first front interconnection layer and the third front interconnection layer can be electrically connected through the front M0 in the second front dielectric layer, and can also be electrically connected through the front M1 in the third front dielectric layer.

[0066] In the embodiment of the present application, since the front source-drain interconnection metal is electrically connected to the front source-drain metal, and the front source-drain metal is connected to the front source-drain structure, the front source-drain interconnection metal can be connected to the front source-drain structure.

[0067] In some possible embodiments, the formation of the front gate interconnection metal and the front source-drain interconnection metal in the first front dielectric layer may include: performing photolithography on the first front dielectric layer to form a front gate interconnection groove and a front source-drain interconnection groove; filling the front gate interconnection groove and the front source-drain interconnection groove with metal material to form a front gate interconnection metal and a front source-drain interconnection metal.

[0068] It can be understood that the method of burying the metal wire in the first front dielectric layer is: coating a photoresist on the first front dielectric layer, and after the photoresist is developed and a photolithography pattern is formed, a groove (i.e., a front gate interconnection groove and a front source-drain interconnection groove) is etched in the first front dielectric layer by photolithography; then, a metal material is deposited in the front gate interconnection groove and the front source-drain interconnection groove to form a front gate interconnection metal and a front source-drain interconnection metal.

[0069] In some possible implementations, the forming of the front side M0 in the second front side dielectric layer may include: performing photolithography on the second front side dielectric layer to form a front side M0 groove; and filling a metal material in the front side M0 groove to form the front side M0.

[0070] It can be understood that the method of burying the metal wire in the second front dielectric layer is: coating photoresist on the second front dielectric layer, and after the photoresist is developed and a photolithography pattern is formed, a groove (i.e., the front M0 groove) is etched in the second front dielectric layer by photolithography; then, a metal material is deposited in the front M0 groove to form the front M0.

[0071] In some possible implementations, forming the front side M1 in the third front side dielectric layer may include: performing photolithography on the third front side dielectric layer to form a front side M1 groove; and filling a metal material in the front side M1 groove to form the front side M1.

[0072] It can be understood that the method of burying the metal wire in the third front dielectric layer is: coating the third front dielectric layer with photoresist, and after the photoresist is developed and a photolithography pattern is formed, etching a groove (i.e., the front M1 groove) in the third front dielectric layer by photolithography; then, forming the front M1 by depositing metal material in the front M1 groove.

[0073] In some embodiments, a dielectric layer (i.e., a fourth front dielectric layer) may be further disposed between the second front dielectric layer and the third front dielectric layer. The metal wire buried in the fourth front dielectric layer is a front interconnect metal, which is used to electrically connect the front M0 and the front M1.

[0074] In some possible embodiments, taking the electrical connection between the first back interconnection layer and the second back interconnection layer as an example, the back interconnection layer may include a back gate interconnection metal, a back source-drain interconnection metal, a back M0, and a back M1; the above S106 may include: depositing an insulating material on the back device layer to form a first back dielectric layer; forming a back gate interconnection metal and a back source-drain interconnection metal in the first back dielectric layer; the back gate interconnection metal connects the back gate structure, and the back source-drain interconnection metal connects the back source-drain metal; depositing an insulating material on the first back dielectric layer to form a second back dielectric layer; forming a back M0 in the second back dielectric layer; the back M0 is used to connect the back device layer and the back interconnection layer; depositing an insulating material on the second back dielectric layer to form a third back dielectric layer; forming a back M1 in the third back dielectric layer; wherein the first back interconnection layer and the second back interconnection layer are electrically connected via the back M0 or the back M1.

[0075] It can be understood that the back interconnection layer is composed of multiple stacked dielectric layers (i.e., the first back dielectric layer, the second back dielectric layer, and the third back dielectric layer), and metal wires are buried in each dielectric layer. The metal wires are used for conduction between the various devices inside the back transistor, and can also be used for conduction between adjacent back transistors. Among them, the metal wires buried in the first back dielectric layer are the back gate interconnection metal and the back source-drain interconnection metal. The back gate interconnection metal is used to electrically connect the back gate structure, and the back source-drain interconnection metal is used to electrically connect the back source-drain metal; the metal wire buried in the second back dielectric layer is the back M0, and the back M0 is used to connect the back device layer and the back interconnection layer; the metal wire buried in the third back dielectric layer is the back M1. The first back interconnection layer and the second back interconnection layer can be electrically connected through the back M0 in the second back dielectric layer, and can also be electrically connected through the back M1 in the third back dielectric layer.

[0076] In the embodiment of the present application, since the back source-drain interconnection metal is electrically connected to the back source-drain metal, and the back source-drain metal is connected to the back source-drain structure, the back source-drain interconnection metal can be connected to the back source-drain structure.

[0077] In some possible embodiments, the formation of a back gate interconnection metal and a back source-drain interconnection metal in the first back dielectric layer may include: performing photolithography on the first back dielectric layer to form a back gate interconnection groove and a back source-drain interconnection groove; filling the back gate interconnection groove and the back source-drain interconnection groove with metal material to form a back gate interconnection metal and a back source-drain interconnection metal.

[0078] It can be understood that the method of burying the metal wire in the first back dielectric layer is: coating a photoresist on the first back dielectric layer, and after the photoresist is developed and a photolithography pattern is formed, a groove (i.e., a back gate interconnection groove and a back source-drain interconnection groove) is etched in the first back dielectric layer by photolithography; then, a back gate interconnection metal and a back source-drain interconnection metal are formed by depositing a metal material in the back gate interconnection groove and the back source-drain interconnection groove.

[0079] In some possible implementations, forming the back side M0 in the second back side dielectric layer may include: performing photolithography on the second back side dielectric layer to form a back side M0 groove; and filling a metal material in the back side M0 groove to form the back side M0.

[0080] It can be understood that the method of burying the metal wire in the second back side dielectric layer is: coating the second back side dielectric layer with photoresist, and after the photoresist is developed and a photolithography pattern is formed, etching a groove (i.e., the back side M0 groove) in the second back side dielectric layer by photolithography; then, depositing metal material in the back side M0 groove to form the back side M0.

[0081] In some possible implementations, forming the back side M1 in the third back side dielectric layer may include: performing photolithography on the third back side dielectric layer to form a back side M1 groove; and filling a metal material in the back side M1 groove to form the back side M1.

[0082] It can be understood that the method of burying the metal wire in the third back side dielectric layer is: coating the third back side dielectric layer with photoresist, and after the photoresist is developed and a photolithography pattern is formed, etching a groove (i.e., the back side M1 groove) in the third back side dielectric layer by photolithography; then, forming the back side M1 by depositing metal material in the back side M1 groove.

[0083] In some embodiments, a dielectric layer (i.e., a fourth back dielectric layer) may be further disposed between the second back dielectric layer and the third back dielectric layer. The metal wire buried in the fourth back dielectric layer is a back interconnect metal, which is used to electrically connect the back M0 and the back M1.

[0084] In the embodiment of the present application, the above-mentioned front gate interconnection metal, front source and drain interconnection metal, front M0, front M1, front interconnection metal, back gate interconnection metal, back source and drain interconnection metal, back M0, back M1, and back interconnection metal can be made of any of the following metal materials: copper, silver, aluminum, tungsten and gold, etc.; other metal materials can also be selected according to actual needs, and the embodiment of the present application does not make specific limitations on this.

[0085] In an embodiment of the present application, the insulating material forming the first front dielectric layer and the first back dielectric layer may be a dielectric material (such as silicon nitride), and the insulating material forming the second front dielectric layer, the third front dielectric layer, the fourth front dielectric layer, the second back dielectric layer, the third back dielectric layer, and the fourth back dielectric layer may be a low-K material.

[0086] In some possible embodiments, the front device layer may also include front source and drain metal vias; the above S102 may include: depositing insulating material on the active structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the active structure; removing a portion of the shallow trench isolation structure that wraps the front active structure to expose the front active structure; forming a front source and drain structure based on the front active structure; depositing semiconductor material on the front active structure and the front source and drain structure to form a front interlayer dielectric layer; forming a front source and drain metal on the front source and drain structure; etching the first portion of the front interlayer dielectric layer to form a front source and drain metal via; the front source and drain metal via is located on the side of the front source and drain metal and extends in the direction toward the back active structure.

[0087] In the embodiment of the present application, the insulating material forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc.

[0088] In some embodiments, after forming the shallow trench isolation structure, the method may further include: performing a chemical-mechanical planarization (CMP) process on the shallow trench isolation structure.

[0089] In an embodiment of the present application, chemical mechanical planarization is performed on the shallow trench isolation structure, so that when the shallow trench isolation structure is subsequently etched, the corresponding corrosion depths of the shallow trench isolation structure in different areas are the same, thereby making the top heights of the exposed active structures the same.

[0090] In the embodiment of the present application, a portion of the shallow trench isolation structure that wraps the front active structure can be removed by etching, and the solvent used for etching the shallow trench isolation structure can be: DHF solution or BOE solution. The solvent used in the etching process in the embodiment of the present application can be selected according to actual conditions and is not limited to the above-mentioned DHF solution or BOE solution.

[0091] In some embodiments, the formation of the front source-drain structure based on the front active structure may include: removing a portion of the front active structure by etching to provide a front source-drain groove of the front transistor. Using the spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the front source-drain groove by selective epitaxial growth to fill the front source-drain groove of the front transistor, and then forming the front source-drain structure on the strained material by a heavy doping process.

[0092] In some embodiments, the forming of the front source-drain metal on the front source-drain structure may include: etching a portion of the front interlayer dielectric layer located above the front source-drain structure until the upper surface of the front source-drain structure is exposed to form a front source-drain metal groove. The front source-drain metal may be obtained by depositing a metal material in the front source-drain metal groove.

[0093] In some possible embodiments, the above-mentioned etching of the first portion of the front interlayer dielectric layer to form the front source and drain metal through-holes may include: forming a first groove by etching the first portion of the front interlayer dielectric layer; and filling the first groove with metal material to form the front source and drain metal through-holes.

[0094] It can be understood that by etching the portion of the front interlayer dielectric layer located on the side of the front source and drain groove (i.e., the first portion of the front interlayer dielectric layer), the etching depth can be lower than the epitaxy of the front source and drain structure to form a slot-shaped hole (i.e., the first groove), and depositing the same metal material as the front source and drain metal in the first groove to obtain a front source and drain metal through hole. In the horizontal direction, the upper surface of the front source and drain metal through hole is at the same height as the upper surface of the front interlayer dielectric layer; the lower surface of the front source and drain metal through hole extends in the direction toward the back active structure, and the height of the front source and drain metal through hole is less than the height of the front interlayer dielectric layer, that is, the front source and drain metal through hole will not extend out of the front interlayer dielectric layer.

[0095] In some embodiments, after forming the shallow trench isolation structure, the above method may further include: opening the front gate region of the front transistor through photolithography processing, and depositing insulating material in the front gate region to form a front dummy gate structure; forming a spacer in the front transistor on the side wall of the front dummy gate structure; removing the front dummy gate structure, and depositing metal material in the front gate region to form a front gate structure.

[0096] In some embodiments, before preparing the front gate structure, the above method may also include: depositing a semiconductor material on the surface of the front active structure to form a front gate dielectric layer of the front transistor, and the front gate dielectric layer is used to isolate the front active structure and the front gate structure.

[0097] In some possible embodiments, the back device layer may also include a back source and drain metal through-hole; the above S105 may include: removing a portion of the back active structure wrapped in the shallow trench isolation structure to expose the back active structure; forming a back source and drain structure based on the back active structure; depositing semiconductor material on the back active structure and the back source and drain structure to form a back interlayer dielectric layer; forming a back source and drain metal on the back source and drain structure; etching the second part of the back interlayer dielectric layer and the third part of the front interlayer dielectric layer to form a back source and drain metal through-hole; the back source and drain metal through-hole is located on the side of the back source and drain metal and extends in the direction toward the front source and drain metal through-hole; the projections of the first part, the second part and the third part on the front interconnection layer coincide, and the front source and drain metal through-hole is connected to the back source and drain metal through-hole.

[0098] In some embodiments, the formation of the back source-drain structure based on the back active structure may include: removing a portion of the back active structure by etching to provide a back source-drain groove of the back transistor. Using the spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the back source-drain groove by selective epitaxial growth to fill the back source-drain groove of the back transistor, and then forming the back source-drain structure on the strained material by a heavy doping process.

[0099] In some embodiments, the forming of the back source and drain metal on the back source and drain structure may include: etching a portion of the back interlayer dielectric layer located above the back source and drain structure until the upper surface of the front source and drain structure is exposed to form a front source and drain metal groove. A metal material is deposited in the front source and drain metal groove to obtain the front source and drain metal.

[0100] In some possible embodiments, the above-mentioned etching of the second portion of the back interlayer dielectric layer and the third portion of the front interlayer dielectric layer to form a back source and drain metal via may include: forming a second groove and exposing the surface of the front source and drain metal via close to the back active structure by etching the second portion of the back interlayer dielectric layer and the third portion of the front interlayer dielectric layer; filling metal material in the second groove to form a back source and drain metal via.

[0101] It can be understood that the projection of the front source and drain metal vias on the back interlayer dielectric layer is aligned, and the portion of the back interlayer dielectric layer located on the side of the back source and drain groove (i.e., the second portion of the back interlayer dielectric layer) is etched, and the etching stops in the front interlayer dielectric layer until the surface of the front source and drain metal vias facing the back active structure is exposed to form a slot-shaped hole (i.e., the second groove), and the same metal material as the back source and drain metal is deposited in the second groove to obtain the back source and drain metal vias. In the horizontal direction, the upper surface of the back source and drain metal vias is at the same height as the upper surface of the back interlayer dielectric layer; the lower surface of the back source and drain metal vias extends in the direction toward the front active structure, and the back source and drain metal vias extend until they contact the front source and drain metal vias.

[0102] In the embodiment of the present application, the sum of the heights of the front source-drain metal vias and the back source-drain metal vias is equal to the sum of the heights of the front interlayer dielectric layer, the shallow trench isolation layer and the back interlayer dielectric layer.

[0103] It should be noted that, for ease of explanation, the front source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the front source structure and / or the front drain structure. In addition, the back source-drain structure, the front source-drain metal, the back source-drain metal, the front source-drain metal through hole, the back source-drain metal through hole, etc. are similar to the front source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0104] In some embodiments, after flipping the wafer, the above method may further include: opening the back gate region of the back transistor through photolithography processing, and depositing insulating material in the back gate region to form a back dummy gate structure; forming a spacer in the back transistor on the side wall of the back dummy gate structure; removing the back dummy gate structure, and depositing metal material in the back gate region to form a back gate structure.

[0105] In an embodiment of the present application, the metal material used to form the front gate structure and the back gate structure may be any one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The metal material of the front gate structure and the back gate structure may be selected according to actual conditions and is not limited to the metal materials listed above.

[0106] In the embodiment of the present application, the materials of the front gate structure and the back gate structure can be made of the same or different metal materials according to actual conditions, and the embodiment of the present application does not make any specific limitation on this.

[0107] In some embodiments, before preparing the back gate structure, the above method may also include: depositing a semiconductor material on the surface of the back active structure to form a back gate dielectric layer of the back transistor, and the back gate dielectric layer is used to isolate the back active structure and the back gate structure.

[0108] It should be noted that the materials used to prepare the front gate dielectric layer and the back gate dielectric layer may be the same or different, and the embodiments of the present application do not specifically limit this.

[0109] In some embodiments, when a portion of the shallow trench isolation structure that wraps the back active structure is removed to expose the back active structure, a shallow trench isolation structure of a certain thickness is retained, and the retained shallow trench isolation structure is a shallow trench isolation layer; the shallow trench isolation layer is arranged between the front interlayer dielectric layer and the back interlayer dielectric layer, and is also arranged between the front gate structure and the back gate structure.

[0110] In the embodiment of the present application, the shallow trench isolation layer can be used to electrically isolate the front gate structure and the back gate structure, and further electrically isolate the front transistor and the back transistor.

[0111] In some embodiments, the interconnected front source-drain metal vias and back source-drain metal vias may be located on one side of the active structure; or, located on both sides of the active structure; or, located in the middle of the active structure.

[0112] It can be understood that for fin field effect transistors, the active structure is a plurality of fin structures, and the interconnected front source and drain metal vias and the back source and drain metal vias can be located on one side of the plurality of fin structures; or they can be located on both sides of the plurality of fin structures; when the intervals between the plurality of fin structures are large and the source and drain epitaxy is not fused together, the interconnected front source and drain metal vias and the back source and drain metal vias can be located between adjacent sources and drains (it can also be understood that the interconnected front source and drain metal vias and the back source and drain metal vias can be located between the left fin structure and the right fin structure). For all-around gate transistors, the active structure is an interval-arranged nanosheet structure, and the interconnected front source and drain metal vias and the back source and drain metal vias can be located on one side of the nanosheet structure; or they can be located on both sides of the nanosheet structure. For planar transistors, the active structure is a block structure, and the interconnected front source and drain metal vias and the back source and drain metal vias can be located on one side of the block structure; or they can be located on both sides of the block structure.

[0113] In the embodiment of the present application, the interconnected front source-drain metal vias and back source-drain metal vias can realize the interconnection between the front source-drain structure and the back source-drain structure.

[0114] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the front transistor and the back transistor as fin field effect transistors as an example. Figure 2A and Figure 2B This is a schematic diagram of a semiconductor structure in an embodiment of the present application. Figure 2A (a) is the design layout of the device layer of the semiconductor structure. Figure 2A (b) is the design layout of the front interconnection layer of the front transistor in the semiconductor structure. Figure 2A (c) is a design layout of a back-side interconnection layer of a back-side transistor in a semiconductor structure. Figure 2B (a) is a cross-sectional view of the semiconductor structure along the AA' direction in the design layout. Figure 2B (b) is a cross-sectional view of the semiconductor structure along the BB' direction in the design layout. Figure 2B (c) is a cross-sectional view of the semiconductor structure along the CC' direction in the design layout.

[0115] See also Figure 2A and Figure 2B As shown, the semiconductor structure 10 includes a front transistor 11 and a back transistor 12. The front transistor 11 includes a first front transistor 111, a second front transistor 112 and a third front transistor 113; the back transistor 12 includes a first back transistor 121, a second back transistor 122 and a third back transistor 123. The first front transistor 111 and the first back transistor 121 are stacked, the second front transistor 112 and the second back transistor 122 are stacked, and the third front transistor 113 and the third back transistor 123 are stacked.

[0116] See also Figure 2A and Figure 2B As shown, the first front interconnection layer of the first front transistor 111 and the third front interconnection layer of the third front transistor 113 are connected through the front side M1; the first back interconnection layer of the first back transistor 121 and the second back interconnection layer of the second back transistor 122 are connected through the back side M0.

[0117] It should be noted that in Figure 2A In the figure, the back side M0 in the back side design layout and the front side M0 in the front side design layout are both schematic; that is, the position of the back side M0 in the back side design layout represents the preset position range in which the back side M0 can be set, and does not represent the actual size and actual position of M0. The actual position of the back side M0 in the back side interconnection layer can be set according to actual conditions (set within the above-mentioned preset position range), and the size of the back side M0 can also be set according to actual conditions; similarly, the front side M0 in the front side design layout represents the preset position range in which the front side M0 can be set.

[0118] In combination with the above preparation method, Figure 2A and Figure 2B The preparation process of the semiconductor structure shown is described. Figure 2A and Figure 2B The semiconductor structure shown can be FIG. 3A to FIG. 3E The process shown is prepared FIG. 3A to FIG. 3E It is a schematic diagram of a preparation process of a semiconductor structure in an embodiment of the present application.

[0119] In an example, taking the front transistor 11 and the back transistor 12 as fin field effect transistors as an example, a preparation process of the semiconductor structure 10 may include the following steps:

[0120] Step 1: Provide a substrate 21 (such as a Si substrate) (see Figure 3A ).

[0121] Step 2: Etching the substrate 21 to form a plurality of fin structures 22, and performing fincut processing on the plurality of fin structures 22. (See Figure 3B ).

[0122] Step 3: deposit insulating material on the substrate 21 and the fin structure 22 to form a shallow trench isolation structure 23; remove the portion of the shallow trench isolation structure 23 that wraps the front active structure 31 by etching to expose the front active structure 31; based on the front active structure 31, form a front source and drain structure 32, a front interlayer dielectric layer 33, a front spacer 34, a front gate structure 35 and a front source and drain metal 36; form a front source and drain metal through hole 37 on the side of the front source and drain metal 36; then, in a direction parallel to BB' in the design layout, photoetch grooves on the side of the first front transistor 111, the second front transistor 112 and the third front transistor 113, the depth of the groove is consistent with the height of the front transistor 11, and the width of the groove can be designed according to actual conditions; fill the groove with insulating material to form a front adjacent device isolation layer 241 (see Figure 3C ).

[0123] The front adjacent device isolation layer 241 is used to isolate adjacent transistors (such as the first front transistor 111 and the second front transistor 112).

[0124] Step 4: depositing insulating material on the front interlayer dielectric layer 33 to form a first front dielectric layer 51; photolithography a front gate interconnection groove and a front source-drain interconnection groove in the first front dielectric layer 51; depositing metal material in the front gate interconnection groove and the front source-drain interconnection groove to form a front gate interconnection metal 511 and a front source-drain interconnection metal 512; depositing insulating material on the first front dielectric layer 51 to form a second front dielectric layer 52; photolithography a front M0 groove in the second front dielectric layer 52; depositing metal material in the front M0 groove to form a front M0 521; depositing insulating material on the second front dielectric layer 52 to form a fourth front dielectric layer 54; photolithography a front interconnection groove in the fourth front dielectric layer 54; depositing metal material in the front interconnection groove to form a front interconnection metal 541; depositing insulating material on the fourth front dielectric layer 54 to form a third front dielectric layer 53; photolithography a front M1 groove in the third front dielectric layer 53; depositing metal material in the front M1 groove to form a front M1 531 (See Figure 3D ).

[0125] The front side M1 531 is located above both the device layer of the first front side transistor 111 and the device layer of the third front side transistor 113 , that is, the front side M1 531 realizes the electrical interconnection between the first front side interconnection layer 1111 and the third front side interconnection layer 1131 .

[0126] Among them, after the fourth step and before the fifth step, the above-mentioned preparation method also includes: depositing oxide above the front interconnection layer to form an insulating layer 13; bonding the insulating layer 13 to the carrier wafer 14; flipping the front transistor 11 of the bonded carrier wafer 14, and removing the substrate 21 to expose the shallow trench isolation structure 23.

[0127] Step 5: Remove the portion of the shallow trench isolation structure 23 that wraps the back active structure 41 by etching to expose the back active structure 41, and retain the shallow trench isolation structure 23 of a preset thickness, which is recorded as a shallow trench isolation layer 231; based on the back active structure 41, form a back source and drain structure 42, a back interlayer dielectric layer 43, a back spacer 44, a back gate structure 45 and a back source and drain metal 46; form a back source and drain metal through hole 47 on the side of the back source and drain metal 46, and the back source and drain metal through hole 47 is connected to the front source and drain metal through hole 37. Next, in a direction parallel to BB' in the design layout, photoetch grooves are formed on the side of the first back transistor 121, the second back transistor 122 and the third back transistor 123. The depth of the groove is equal to the sum of the heights of the back transistor 12 and the shallow trench isolation layer 231, and the width of the groove can be designed according to actual conditions; fill the groove with insulating material to form a back adjacent device isolation layer 242 (see Figure 3E ).

[0128] The back adjacent device isolation layer 242 is used to isolate adjacent transistors (such as the first back transistor 121 and the second back transistor 122 ).

[0129] Step 6: depositing insulating material on the back interlayer dielectric layer 43 to form a first back dielectric layer 61; photolithography a back gate interconnection groove and a back source-drain interconnection groove in the first back dielectric layer 61; depositing metal material in the back gate interconnection groove and the back source-drain interconnection groove to form a back gate interconnection metal 611 and a back source-drain interconnection metal 612; depositing insulating material on the first back dielectric layer 61 to form a second back dielectric layer 62; photolithography a back M0 groove in the second back dielectric layer 62; depositing metal material in the back M0 groove to form a back M0 621; depositing insulating material on the second back dielectric layer 62 to form a fourth back dielectric layer 64; photolithography a back interconnection groove in the fourth back dielectric layer 64; depositing metal material in the back interconnection groove to form a back interconnection metal 641; depositing insulating material on the fourth back dielectric layer 64 to form a third back dielectric layer 63; photolithography a back M1 groove in the third back dielectric layer 63; depositing metal material in the back M1 groove to form a back M1 631 (the semiconductor structure 10 finally formed can be seen in Figure 2B ).

[0130] The back side M0 621 is located above both the device layer of the first back side transistor 121 and the device layer of the second back side transistor 122 , that is, the back side M0 621 realizes electrical interconnection between the first back side interconnection layer 1211 and the second back side interconnection layer 1221 .

[0131] At this point, the semiconductor structure 10 in which the front transistor 11 and the back transistor 12 are fin field effect transistors, the first front interconnection layer 1111 and the third front interconnection layer 1131 in the front transistor 11 are electrically connected, and the first back interconnection layer 1211 and the second back interconnection layer 1221 in the back transistor 12 are electrically connected is completed.

[0132] It should be noted that the electrical connection between the first front interconnection layer and the third front interconnection layer is only one example of the present application. The embodiment of the present application can also electrically connect the first front interconnection layer and the second front interconnection layer, or, electrically connect the second front interconnection layer and the third front interconnection layer; in addition, the way in which the first front interconnection layer and the second front interconnection layer are electrically connected and the way in which the second front interconnection layer and the third front interconnection layer are electrically connected are the same as the way in which the first front interconnection layer and the third front interconnection layer are electrically connected, and the embodiment of the present application will not elaborate on this. Correspondingly, the electrical connection between the first back interconnection layer and the second back interconnection layer is only one example of the present application. The embodiment of the present application can also electrically connect the first back interconnection layer and the third back interconnection layer, or, electrically connect the second back interconnection layer and the third back interconnection layer; in addition, the way in which the first back interconnection layer and the third back interconnection layer are electrically connected and the way in which the second back interconnection layer and the third back interconnection layer are electrically connected are the same as the way in which the first back interconnection layer and the second back interconnection layer are electrically connected, and the embodiment of the present application will not elaborate on this.

[0133] It should also be noted that the connection between the first front interconnection layer and the third front interconnection layer through the front M1 is only one example of the present application; the interconnection between the front interconnection layers can also be achieved through the metal in the front M0 or other interconnection layers, and the present application embodiment does not specifically limit this. Correspondingly, the connection between the first back interconnection layer and the second back interconnection layer through the back M0 is only one example of the present application; the interconnection between the back interconnection layers can also be achieved through the metal in the back M1 or other interconnection layers, and the present application embodiment does not specifically limit this.

[0134] In an embodiment of the present application, when the front transistor and the back transistor are planar transistors or nanosheet field effect transistors, except that the active structure is different from the active structure of the semiconductor structure composed of the above-mentioned fin-type field effect transistor, the other structures are the same as the semiconductor structure composed of the above-mentioned fin-type field effect transistor; accordingly, except that the preparation process of the active structure is different, the preparation process of the remaining structures is the same as the preparation process shown in the above-mentioned example, and the embodiment of the present application will not elaborate on this.

[0135] In an embodiment of the present application, in a front transistor, any two of the first front interconnection layer, the second front interconnection layer and the third front interconnection layer are electrically connected, and in a back transistor, any two of the first back interconnection layer, the second back interconnection layer and the third back interconnection layer are electrically connected; in this way, interconnection between adjacent units can be achieved in the semiconductor structure, thereby improving the space utilization of the semiconductor structure.

[0136] Furthermore, since the front source-drain metal vias and the back source-drain metal vias in the semiconductor structure are connected, and the front source-drain metal vias are connected to the front source-drain metal, and the back source-drain metal vias are connected to the back source-drain metal, the source-drain interconnection between the front transistor and the back transistor can be achieved.

[0137] Furthermore, on the basis of the source-drain interconnection between the front transistor and the back transistor, through the interconnection of the front interconnection layer of the front transistor (i.e., any two of the first front interconnection layer, the second front interconnection layer and the third front interconnection layer are electrically connected) and the interconnection of the back interconnection layer of the back transistor (i.e., any two of the first back interconnection layer, the second back interconnection layer and the third back interconnection layer are electrically connected), it is possible to lead out the output signal on both sides of the semiconductor structure, and realize electrical interconnection between standard units by double-sided routing, thereby further improving space utilization and reducing wiring difficulty.

[0138] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing to detect the front source and drain metal vias and the back source and drain metal vias.

[0139] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 2A and Figure 2B The semiconductor structure shown will not be described in detail here.

[0140] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 2A and Figure 2B The semiconductor structure shown will not be described in detail here.

[0141] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0142] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure comprises a front transistor and a back transistor arranged in back-to-back relation, the front transistor and the back transistor are self-aligned in a direction perpendicular to the active region, the front transistor comprises a first front transistor, a second front transistor and a third front transistor, and the back transistor comprises a first back transistor, a second back transistor and a third back transistor; wherein the first front transistor is arranged adjacent to the second front transistor along a first direction, the first front transistor is arranged adjacent to the third front transistor along a second direction, the first direction is perpendicular to the second direction, the first back transistor is arranged adjacent to the second back transistor along the first direction, and the first back transistor is arranged adjacent to the third back transistor along the second direction; The method comprises: An active structure is formed on a substrate; the active structure includes a front active structure and a back active structure; Based on the front active structure, a front device layer of the front transistor is formed; the front device layer includes a front source-drain structure, a front gate structure, a front interlayer dielectric layer and a front source-drain metal; Performing a back-end process on the front device layer to form a front interconnection layer; the front interconnection layer includes a first front interconnection layer corresponding to the first front transistor, a second front interconnection layer corresponding to the second front transistor, and a third front interconnection layer corresponding to the third front transistor, and any two of the first front interconnection layer, the second front interconnection layer and the third front interconnection layer are electrically connected; flipping the wafer and removing the substrate; Based on the back active structure, a back device layer of the back transistor is formed; the back device layer includes a back source and drain structure, a back gate structure, a back interlayer dielectric layer and a back source and drain metal; A back-end process is performed on the back device layer to form a back interconnection layer; the back interconnection layer includes a first back interconnection layer corresponding to the first back transistor, a second back interconnection layer corresponding to the second back transistor, and a third back interconnection layer corresponding to the third back transistor, and any two of the first back interconnection layer, the second back interconnection layer and the third back interconnection layer are electrically connected.

2. The method according to claim 1, characterized in that In the case where the first front interconnection layer and the third front interconnection layer are electrically connected, the front interconnection layer includes a front gate interconnection metal, a front source-drain interconnection metal, a front first metal, and a front second metal; The back-end process is performed on the front device layer to form a front interconnection layer, including: Depositing an insulating material on the front device layer to form a first front dielectric layer; The front gate interconnection metal and the front source-drain interconnection metal are formed in the first front dielectric layer; the gate interconnection metal is connected to the front gate structure, and the source-drain interconnection metal is connected to the front source-drain metal; Depositing an insulating material on the first front dielectric layer to form a second front dielectric layer; forming the front first metal in the second front dielectric layer; the front first metal is used to connect the front device layer and the front interconnection layer; Depositing an insulating material on the second front dielectric layer to form a third front dielectric layer; forming the front second metal in the third front dielectric layer; The first front-side interconnection layer and the third front-side interconnection layer are electrically connected via the second front-side metal or the first front-side metal.

3. The method according to claim 2, characterized in that The forming of the front gate interconnection metal and the front source-drain interconnection metal in the first front dielectric layer comprises: Performing photolithography on the first front dielectric layer to form a front gate interconnection groove and a front source-drain interconnection groove; Metal material is filled in the front gate interconnection groove and the front source-drain interconnection groove to form the front gate interconnection metal and the front source-drain interconnection metal.

4. The method according to claim 2, characterized in that: The forming of the front first metal in the second front dielectric layer comprises: Performing photolithography on the second front dielectric layer to form a first front metal groove; A metal material is filled in the front first metal groove to form the front first metal.

5. The method according to claim 2, characterized in that: The forming of the front second metal in the third front dielectric layer comprises: Performing photolithography on the third front dielectric layer to form a second front metal groove; The front second metal groove is filled with metal material to form the front second metal.

6. The method according to claim 1, characterized in that In the case where the first backside interconnection layer and the second backside interconnection layer are electrically connected, the backside interconnection layer comprises a backside gate interconnection metal, a backside source-drain interconnection metal, a backside first metal, and a backside second metal; The back-end process is performed on the back device layer to form a back interconnection layer, including: Depositing an insulating material on the back device layer to form a first back dielectric layer; The back gate interconnection metal and the back source-drain interconnection metal are formed in the first back dielectric layer; the back gate interconnection metal is connected to the back gate structure, and the back source-drain interconnection metal is connected to the back source-drain metal; Depositing an insulating material on the first back dielectric layer to form a second back dielectric layer; forming the back first metal in the second back dielectric layer; the back first metal is used to connect the back device layer and the back interconnection layer; Depositing an insulating material on the second back dielectric layer to form a third back dielectric layer; forming the back side second metal in the third back side dielectric layer; The first back-side interconnection layer and the second back-side interconnection layer are electrically connected via the first back-side metal or the second back-side metal.

7. The method according to claim 6, characterized in that The forming of the back gate interconnection metal and the back source-drain interconnection metal in the first back dielectric layer comprises: Performing photolithography on the first back dielectric layer to form a back gate interconnection groove and a back source-drain interconnection groove; Metal material is filled in the back gate interconnection groove and the back source-drain interconnection groove to form the back gate interconnection metal and the back source-drain interconnection metal.

8. The method according to claim 6, characterized in that The forming of the back first metal in the second back dielectric layer comprises: Performing photolithography on the second back dielectric layer to form a first back metal groove; A metal material is filled in the back first metal groove to form the back first metal.

9. The method according to claim 6, characterized in that The forming of the back side second metal in the third back side dielectric layer comprises: Performing photolithography on the third back dielectric layer to form a second back metal groove; The back second metal groove is filled with metal material to form the back second metal.

10. The method according to claim 1, characterized in that The front device layer also includes front source and drain metal vias; The forming of a front device layer of a front transistor based on the front active structure comprises: Depositing insulating material on the active structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the active structure; Removing a portion of the shallow trench isolation structure that wraps the front active structure to expose the front active structure; Based on the front active structure, forming the front source-drain structure; Depositing a semiconductor material on the front active structure and the front source-drain structure to form a front interlayer dielectric layer; forming the front source-drain metal on the front source-drain structure; The first portion of the front interlayer dielectric layer is etched to form a front source-drain metal through hole; the front source-drain metal through hole is located on the side of the front source-drain metal and extends in a direction toward the back active structure.

11. The method according to claim 10, characterized in that The back device layer also includes back source and drain metal vias; The forming of a back device layer of a back transistor based on the back active structure comprises: Removing a portion of the shallow trench isolation structure that wraps the back active structure to expose the back active structure; Based on the back active structure, forming the back source and drain structure; Depositing a semiconductor material on the back active structure and the back source / drain structure to form a back interlayer dielectric layer; forming the back side source and drain metal on the back side source and drain structure; The second portion of the back interlayer dielectric layer and the third portion of the front interlayer dielectric layer are etched to form a back source-drain metal via; the back source-drain metal via is located on the side of the back source-drain metal and extends in the direction toward the front source-drain metal via; the projections of the first portion, the second portion and the third portion on the front interconnect layer overlap, and the front source-drain metal via is connected to the back source-drain metal via.

12. The method according to claim 11, characterized in that The etching of the first portion of the front interlayer dielectric layer to form the front source-drain metal through hole comprises: forming a first groove by etching the first portion of the front interlayer dielectric layer; and filling the first groove with a metal material to form the front source-drain metal through hole; The etching of the second portion of the back interlayer dielectric layer and the third portion of the front interlayer dielectric layer to form a back source-drain metal through hole includes: forming a second groove and exposing the surface of the front source-drain metal through hole close to the back active structure by etching the second portion of the back interlayer dielectric layer and the third portion of the front interlayer dielectric layer; and filling a metal material in the second groove to form the back source-drain metal through hole.

13. A semiconductor structure, characterized in that: Prepared by the method according to any one of claims 1 to 12, the semiconductor structure comprises: Front-side transistors; the front-side transistors include a first front-side transistor, a second front-side transistor and a third front-side transistor; Back side transistors; the back side transistors include a first back side transistor, a second back side transistor and a third back side transistor; the front side transistors and the back side transistors are self-aligned in a direction perpendicular to the active region; Wherein, any two interconnection layers among the first front interconnection layer of the first front transistor, the second front interconnection layer of the second front transistor and the third front interconnection layer of the third front transistor are electrically connected; any two interconnection layers among the first back interconnection layer of the first back transistor, the second back interconnection layer of the second back transistor and the third back interconnection layer of the third back transistor are electrically connected; The front transistor comprises a front source-drain metal and a front source-drain metal through hole connected to the front source-drain metal; the front source-drain metal through hole is arranged on a side of the front source-drain metal; The back transistor includes a back source and drain metal and a back source and drain metal through-hole connected to the back source and drain metal; the back source and drain metal through-hole is arranged on the side of the back source and drain metal; wherein, the front source and drain metal through-hole extends in the direction toward the back transistor, the back source and drain metal through-hole extends in the direction toward the front transistor, and the front source and drain metal through-hole is connected to the back source and drain metal through-hole.

14. The semiconductor structure according to claim 13, characterized in that: In the case where the first front interconnection layer is electrically connected to the third front interconnection layer, the first front interconnection layer is electrically connected to the third front interconnection layer via the second front metal or the first front metal; In the case where the first back-side interconnection layer is electrically connected to the second back-side interconnection layer, the first back-side interconnection layer is electrically connected to the second back-side interconnection layer through a back-side first metal or a back-side second metal.

15. A semiconductor device, characterized in that: include: The semiconductor structure of claim 13.

16. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 15, wherein the semiconductor device is arranged on the circuit board.

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