Heterogeneous integration structure, its preparation method, and semiconductor device

Abstract

Embodiments of the present application disclose a heterogeneous integration structure, a preparation method thereof, and a semiconductor device. The preparation method includes: forming a first chip, the first chip including a first semiconductor substrate, a first functional layer located on the first semiconductor substrate, and a first interconnect layer, the first interconnect layer including a first dielectric layer and a plurality of first conductive posts located in the first dielectric layer. Forming a first wafer, the first wafer including a second semiconductor substrate, a second functional layer located on the second semiconductor substrate, and a second interconnect layer, the second interconnect layer including a second dielectric layer and a plurality of second conductive posts located in the second dielectric layer. The first semiconductor substrate is different from the second semiconductor substrate. Bonding the first interconnect layer of the first chip to the second interconnect layer of the first wafer to obtain a bonded structure; the first chip and the first wafer are electrically connected through the first conductive posts and the second conductive posts. Cutting the bonded structure to form a heterogeneous integration structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a heterogeneous integrated structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] In the related art, some active chips, such as lasers, amplifiers, and detectors, are made of III-V materials, while some passive chips, such as passive optical waveguides, are made of silicon-based materials. These active chips and passive chips are usually electrically connected by conductive wire welding or conductive micro-bump bonding technology. However, conductive wires (e.g., gold wires) are expensive and not conducive to widespread application; and transmitting electrical signals through conductive wires not only has a slow signal transmission speed, but also has the problem of signal loss. Conductive micro-bumps can cause poor electrical connection performance due to poor alignment accuracy or voids generated during the annealing process. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a heterogeneous integrated structure and a preparation method thereof, as well as a semiconductor device to solve at least one problem existing in the background technology, which can improve the good bonding and electrical connection performance of the heterogeneous integrated chip.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] On the one hand, an embodiment of the present application provides a method for preparing a heterogeneous integrated structure. The preparation method includes: forming a first chip, the first chip including a first semiconductor substrate and a first functional layer and a first interconnection layer located on the first semiconductor substrate, the first interconnection layer including a first dielectric layer and a plurality of first conductive pillars located in the first dielectric layer. Forming a first wafer, the first wafer including a second semiconductor substrate and a second functional layer and a second interconnection layer located on the second semiconductor substrate, the second interconnection layer including a second dielectric layer and a plurality of second conductive pillars located in the second dielectric layer; the first semiconductor substrate is different from the second semiconductor substrate. Bonding the first interconnection layer of the first chip to the second interconnection layer of the first wafer to obtain a bonding structure; the first chip and the first wafer are electrically connected through the first conductive pillars and the second conductive pillars. Cutting the bonding structure to form a heterogeneous integrated structure.

[0006] In some examples, the method further includes forming a second chip, the second chip including a third semiconductor substrate and a third functional layer and a third interconnect layer located on the third semiconductor substrate. The third interconnect layer includes a third dielectric layer and a plurality of third conductive pillars located in the third dielectric layer. The third semiconductor substrate is different from both the first and second semiconductor substrates.

[0007] Bond the first interconnect layer of the first chip to the second interconnect layer of the first wafer to obtain a bonded structure, including: bond the first interconnect layer of the first chip, the third interconnect layer of the second chip to the second interconnect layer of the first wafer to obtain the bonded structure. The second chip and the first wafer are electrically connected through the third conductive pillar and the second conductive pillar.

[0008] In some examples, forming the first chip includes: providing a second initial wafer. Forming the first functional layer on the second initial wafer. Forming the first dielectric layer on the first functional layer. Forming a plurality of first vias in the first dielectric layer. Forming the first conductive pillars in the first vias to obtain the first chip; one end face of the first conductive pillar contacts the first functional layer, and the opposite end face is flush with the plane where the opening of the first via is located.

[0009] And, forming the second chip includes: providing a third initial wafer. Forming the third functional layer on the third initial wafer. Forming the third dielectric layer on the third functional layer. Forming a plurality of third vias in the third dielectric layer. Forming the third conductive pillars in the third vias to obtain the second chip; one end face of the third conductive pillar contacts the third functional layer, and the opposite end face is flush with the plane where the opening of the third via is located.

[0010] In some examples, after forming the first conductive pillars in the first vias, it further includes: thinning the side of the second initial wafer away from the first interconnect layer to form a second wafer; cutting the second wafer along the thickness direction of the second wafer to obtain a plurality of the first chips.

[0011] And, after forming the third conductive pillars in the third vias, it further includes: thinning the side of the third initial wafer away from the third interconnect layer to form a third wafer; cutting the third wafer along the thickness direction of the third wafer to obtain a plurality of the second chips.

[0012] In some examples, forming the first wafer includes: providing a first initial wafer. Forming the second functional layer on the first initial wafer. Forming the second dielectric layer on the second functional layer. Forming a plurality of second vias in the second dielectric layer. Forming the second conductive pillars in the second vias to obtain the first wafer; one end face of the second conductive pillar contacts the second functional layer, and the opposite end face of the second conductive pillar is flush with the plane where the opening of the second via is located.

[0013] In some examples, after obtaining the bonded structure, the manufacturing method further includes: forming a filling layer in the gaps between the chips on the first wafer.

[0014] Slicing the bonding structure includes: slicing the filling layer and the first wafer along the thickness direction of the first wafer to obtain a plurality of the heterogeneous integration structures; wherein, the first wafer is divided into a plurality of base chips.

[0015] In some examples, the size of the first chip is different from the size of the second chip.

[0016] In some examples, the materials of the first semiconductor substrate and the third semiconductor substrate include non-silicon materials; the material of the second semiconductor substrate includes silicon.

[0017] In some examples, the first conductive pillar, the second conductive pillar, and the third conductive pillar each include a first portion extending in a direction perpendicular to the plane of the second dielectric layer and a second portion extending in a direction parallel to the plane of the second dielectric layer.

[0018] Bonding the first interconnect layer of the plurality of first chips, the third interconnect layer of the plurality of second chips, and the second interconnect layer of the first wafer to obtain the bonding structure includes: bonding the second portions of the first conductive pillars of the plurality of first chips, the second portions of the third conductive pillars of the plurality of second chips, and the second portion of the second conductive pillar of the first wafer, and bonding the first dielectric layer of the plurality of first chips, the third dielectric layer of the plurality of second chips, and the second dielectric layer of the first wafer to obtain the bonding structure.

[0019] In the preparation method of the above heterogeneous integration structure, since the material of the first semiconductor substrate in the prepared first chip is different from the material of the second semiconductor substrate of the first wafer, after separately preparing the structures of the first chip and the first wafer, the two structures are electrically connected by bonding the chip and the wafer to perform heterogeneous integration. In this way, it can be ensured that the structures of the first chip and the first wafer can each adapt to different process conditions. Among them, when bonding, the first interconnect layer of the first chip is bonded to the second interconnect layer of the first wafer, so that the first chip and the first wafer are electrically connected through the first conductive pillar and the second conductive pillar to obtain a heterogeneous integration structure with good electrical connection performance. It can be understood that the bonding is generally performed on the entire plane of the first interconnect layer and the second interconnect layer, which can avoid problems such as voids caused by height differences on the surface of similar bump welding, and the cross-sectional area of the conductive pillar is large, the transmission impedance is small, and the transmission signal loss is also better improved than that of conductive wires.

[0020] On the other hand, an embodiment of the present application further provides a heterogeneous integration structure. The heterogeneous integration structure includes: a first chip and a substrate chip. The first chip includes a first semiconductor substrate, a first functional layer, and a first interconnect layer located on the first semiconductor substrate. The first interconnect layer includes a first dielectric layer and a plurality of first conductive posts located in the first dielectric layer. The substrate chip includes a second semiconductor substrate, a second functional layer, and a second interconnect layer located on the second semiconductor substrate. The second interconnect layer includes a second dielectric layer and a plurality of second conductive posts located in the second dielectric layer. Wherein, the first semiconductor substrate is different from the second semiconductor substrate; an end face of the first conductive post away from the first semiconductor substrate is in contact with an end face of the second conductive post away from the second semiconductor substrate.

[0021] In some examples, the heterogeneous integration structure further includes: a second chip. The second chip includes a third semiconductor substrate, a third functional layer, and a third interconnect layer located on the third semiconductor substrate. The third interconnect layer includes a third dielectric layer and a plurality of third conductive posts located in the third dielectric layer. The third semiconductor substrate is different from both the first semiconductor substrate and the second semiconductor substrate. An end face of the third conductive post away from the third semiconductor substrate is in contact with an end face of the second conductive post away from the second semiconductor substrate; the second chip and the first chip are spaced apart and disposed on the substrate chip.

[0022] In some examples, the size of the first chip is different from the size of the second chip.

[0023] In some examples, the materials of the first semiconductor substrate and the third semiconductor substrate include non-silicon materials; the material of the second semiconductor substrate includes silicon.

[0024] In some examples, the first interconnect layer is disposed on a side of the first functional layer away from the first semiconductor substrate; an end face of the plurality of first conductive posts away from the first functional layer is flush with a side surface of the first dielectric layer away from the first functional layer. The third interconnect layer is disposed on a side of the third functional layer away from the third semiconductor substrate; an end face of the plurality of third conductive posts away from the third functional layer is flush with a side surface of the third dielectric layer away from the third functional layer. And, the second interconnect layer is disposed on a side of the second functional layer away from the second semiconductor substrate; an end face of the plurality of second conductive posts away from the second functional layer is flush with a side surface of the second dielectric layer away from the second functional layer.

[0025] In some examples, the area of the end face of the first conductive pillar away from the first functional layer is larger than the area of the end face of the first conductive pillar close to the first functional layer; and / or, the area of the end face of the second conductive pillar away from the second functional layer is larger than the area of the end face of the second conductive pillar close to the second functional layer; and / or, the area of the end face of the third conductive pillar away from the third functional layer is larger than the area of the end face of the third conductive pillar close to the third functional layer. Wherein, the end face areas of the contact positions between the first conductive pillar and the second conductive pillar are the same; the end face areas of the contact positions between the third conductive pillar and the second conductive pillar are the same.

[0026] In some examples, the first conductive pillar, the second conductive pillar and the third conductive pillar each include a first portion extending in a direction perpendicular to the plane of the second dielectric layer, and a second portion extending in a direction parallel to the plane of the second dielectric layer; the orthographic projection area of the second portion on the second dielectric layer is larger than the orthographic projection area of the first portion on the second dielectric layer. The second portions of the first conductive pillars of the plurality of first chips, the second portions of the third conductive pillars of the plurality of second chips are in contact with the second portion of the second conductive pillar of the base chip, and the first dielectric layers of the plurality of first chips, the third dielectric layers of the plurality of second chips are in contact with the second dielectric layer of the base chip.

[0027] The beneficial effects of the heterogeneous integration structure provided by the embodiments of the present application are the same as those of the preparation method of the heterogeneous integration structure provided in any of the above examples, and will not be elaborated here.

[0028] In another aspect, the embodiments of the present application provide a semiconductor device. The semiconductor device includes the heterogeneous integration structure provided in any of the above examples.

[0029] The beneficial effects of the semiconductor device provided by the present application are the same as those of the heterogeneous integration structure provided in any of the above examples, and will not be elaborated here.

[0030] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. Description of the Drawings

[0031] Figure 1 Schematic diagram of the bonding structure between different chips in the related art Figure 1 ;

[0032] Figure 2 Schematic diagram of the bonding structure between different chips in the related art Figure 2 ;

[0033] Figure 3A schematic structural diagram of a heterogeneous integration structure provided by an embodiment of the present application;

[0034] Figure 4 Another schematic structural diagram of a heterogeneous integration structure provided by an embodiment of the present application;

[0035] Figure 5 Yet another schematic structural diagram of a heterogeneous integration structure provided by an embodiment of the present application;

[0036] Figure 6 A schematic flowchart of a preparation method for a heterogeneous integration structure provided by an embodiment of the present application;

[0037] Figure 7 Another schematic flowchart of a preparation method for a heterogeneous integration structure provided by an embodiment of the present application;

[0038] Figure 8 A schematic structural diagram of a preparation method for the first chip of a heterogeneous integration structure provided by an embodiment of the present application;

[0039] Figure 9 A schematic structural diagram of a preparation method for the second chip of a heterogeneous integration structure provided by an embodiment of the present application;

[0040] Figure 10 A schematic structural diagram of a preparation method for the first wafer of a heterogeneous integration structure provided by an embodiment of the present application;

[0041] Figure 11 A schematic structural diagram of a heterogeneous integration method for the first chip and the second chip with the first wafer provided by an embodiment of the present application. Detailed implementation manners

[0042] Hereinafter, the exemplary embodiments disclosed in the present application will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0043] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known to the art are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0044] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. Throughout the drawings, like reference numerals indicate like elements.

[0045] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0046] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present application.

[0047] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0049] To thoroughly understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this application. The preferred embodiments of this application are described in detail below. However, in addition to these detailed descriptions, this application may also have other implementation manners.

[0050] With the continuous pursuit of performance such as multi-functional integration, high-density integration, small volume and weight, low power consumption, large bandwidth, and low latency in electronic information systems, the technology of heterogeneous integration of functional devices or chips of various compound semiconductor material systems (such as GaN, InP, SiC, etc.) with chips of CMOS integrated circuits is just beginning. Among them, the technology of silicon-based heterogeneous integration in microelectronics and optoelectronics is an important research direction.

[0051] In related technologies, as Figure 1 and Figure 2 shown, active chips such as lasers, amplifiers, and detectors are mainly made of III-V materials, and passive chips such as passive optical waveguides are generally made of silicon-based materials. Active chips and passive chips are usually electrically connected through wire bonding or metal micro-bump bonding technology. However, as Figure 1 shown, conductive wires (such as gold wires) are expensive and not conducive to wide application; and transmitting electrical signals through conductive wires not only has a slow electrical signal transmission speed but also has problems of signal loss. As Figure 2 shown, conductive micro-bumps may have problems of poor electrical connection performance due to poor alignment accuracy or voids generated in the annealing process.

[0052] Therefore, the embodiments of this application provide a heterogeneous integration structure, its preparation method, and a semiconductor device, which can improve the electrical connection performance between chips in heterogeneous integration, and the preparation method is conducive to wide application under different preparation process conditions.

[0053] On the one hand, as Figures 3 to 5 shown, the embodiments of this application provide a heterogeneous integration structure 100. The heterogeneous integration structure 100 includes a first chip 110 and a substrate chip 120.

[0054] It should be noted that the heterogeneous integration structure 100 provided by this application may specifically be a heterogeneous composite chip, the semiconductor substrates of the first chip 110 included therein are different from those of the substrate chip 120, and the heterogeneity exactly refers to the difference in the semiconductor substrates of the two. The heterogeneous composite chip may include the integration of one or more chips such as radio frequency device chips, power device chips, or silicon optical chips. For example, the substrate chip 120 is a silicon optical chip; the first chip 110 is a laser chip, and the first chip 110 may also be a chip with other functions. The embodiments of this application do not limit the specific chip types.

[0055] As shown Figure 3 in FIG. 1, the first chip 110 includes a first semiconductor substrate 111, a first functional layer 112 and a first interconnect layer 113 located on the first semiconductor substrate 111. The first interconnect layer 113 includes a first dielectric layer 1131 and a plurality of first conductive vias 1132 located in the first dielectric layer 1131.

[0056] In some embodiments, the material of the first semiconductor substrate 111 includes a non-silicon material, specifically, a compound semiconductor material. Exemplarily, the material of the first semiconductor substrate 111 includes one or more of silicon, gallium nitride (GaN), silicon carbide (SiC), and indium phosphide (InP).

[0057] The first functional layer 112 includes a single layer or a stack of multiple functional layers forming semiconductor devices. For example, the multiple functional layers of the first functional layer 112 include one or more functional layers such as a first electrode layer, a piezoelectric layer, a second electrode layer, and a waveguide layer sequentially stacked on the first semiconductor substrate 111, for forming functional devices such as lasers, amplifiers, or resonators, etc. The embodiments of the present application do not limit this.

[0058] The first interconnect layer 113 is disposed on a side of the first functional layer 112 away from the first semiconductor substrate 111. Exemplarily, the first dielectric layer 1131 of the first interconnect layer 113 provides an interface for hybrid bonding in a subsequent chip-wafer bonding process, so as to facilitate electrical connection between different chips through the first conductive vias 1132.

[0059] Continuing to refer Figure 3 to FIG. 1, the base chip 120 includes a second semiconductor substrate 121, a second functional layer 122 and a second interconnect layer 123 located on the second semiconductor substrate 121. The second interconnect layer 123 includes a second dielectric layer 1231 and a plurality of second conductive vias 1232 located in the second dielectric layer 1231.

[0060] In some embodiments, the second semiconductor substrate 121 is used to provide a supporting function for the second functional layer 122 and the second interconnect layer 123. For example, the second semiconductor substrate 121 is silicon.

[0061] The second functional layer 122 includes a single layer or a stack of multiple functional layers forming semiconductor devices. For example, the multiple functional layers of the second functional layer 122 include a CMOS circuit layer sequentially stacked on the second semiconductor substrate 121, for forming a silicon-based CMOS, etc. The embodiments of the present application do not limit this.

[0062] The second interconnection layer 123 is disposed on a side of the second functional layer 122 away from the second semiconductor substrate 121. For example, the second dielectric layer 1231 of the second interconnection layer 123 provides an interface for hybrid bonding in a subsequent chip-wafer bonding process, so as to facilitate electrical connection between different chips through the second conductive posts 1232 (for example, electrical connection is achieved through the first conductive post 1132 and the second conductive post 1232).

[0063] The above-mentioned first semiconductor substrate 111 is different from the second semiconductor substrate 121. An end face of the first conductive post 1132 away from the first semiconductor substrate 111 contacts an end face of the second conductive post 1232 away from the second semiconductor substrate 121.

[0064] That is to say, in the above heterogeneous integration structure 100, for example, the material of the first semiconductor substrate 111 may include one or more of GaN, SiC, and indium phosphide InP, and the second semiconductor substrate 121 is silicon. Since the materials of the first semiconductor substrate 111 in the first chip 110 and the second semiconductor substrate 121 of the base chip 120 are different, it is impossible to fabricate these two chip structures in one step by a synchronous process. It is necessary to separately prepare the structures of the first chip 110 and the base chip 120. In this way, it can be ensured that the structures of the first chip and the first wafer can each adapt to different application scenarios or process conditions for realizing different functions. And, after obtaining the first chip 110 and the base chip 120, the first interconnection layer 113 of the first chip 110 is bonded to the second interconnection layer 123 of the base chip 120 by means of chip-wafer bonding, so that the first chip 110 and the base chip 120 are electrically connected through the first conductive post 1132 and the second conductive post 1232, and a heterogeneous integration structure with good electrical connection performance is obtained. Moreover, through this preparation method, the electrical connection performance of heterogeneous chips can be improved. It can be understood that the bonding is generally performed on the entire plane of the first interconnection layer 113 and the second interconnection layer 123, which can avoid problems such as voids caused by height differences on the surface of similar bump welding, and the cross-sectional area of the conductive post is large, the transmission impedance is small, and the transmission signal loss is also better improved than that of conductive wires.

[0065] In some examples, as Figure 4 shown, the heterogeneous integration structure 100 further includes: a second chip 130.

[0066] The second chip 130 includes a third semiconductor substrate 131, a third functional layer 132 located on the third semiconductor substrate 131, and a third interconnection layer 133. The third interconnection layer 133 includes a third dielectric layer 1331 and a plurality of third conductive posts 1332 located in the third dielectric layer 1331.

[0067] The third semiconductor substrate 131 is different from both the first semiconductor substrate 111 and the second semiconductor substrate 121. The end face of the third conductive pillar 1332 away from the third semiconductor substrate 131 contacts the end face of the second conductive pillar 1232 away from the second semiconductor substrate 121; the second chip 130 and the first chip 110 are spaced apart along the direction X perpendicular to the thickness of the second dielectric layer 1231 on the base chip 120.

[0068] In some other examples, the first chip 110 and the second chip 130 may also be chips with the same semiconductor substrate but different functional layers. That is, the third semiconductor substrate 131 is different from the second semiconductor substrate 121, the third semiconductor substrate 131 is the same as the first semiconductor substrate 111, and the third functional layer 132 is different from the first functional layer 112.

[0069] The third dielectric layer 1331 of the third interconnect layer 133 provides an interface for hybrid bonding in the subsequent chip-wafer bonding process, so as to facilitate electrical connection between different chips through the third conductive pillar 1332.

[0070] The above-mentioned third semiconductor substrate 131 is different from both the first semiconductor substrate 111 and the second semiconductor substrate 121. For example, the materials of the first semiconductor substrate 111 and the third semiconductor substrate 131 include non-silicon materials; the material of the second semiconductor substrate 121 includes silicon.

[0071] For example, the material of the first semiconductor substrate 111 includes SiC, the material of the third semiconductor substrate 131 includes GaN, and the second semiconductor substrate 121 includes silicon.

[0072] In some examples, the size of the first chip 110 is different from the size of the second chip 130. For example, the size of the first chip 110 can be 6 inches, and the size of the second chip 130 can be 8 inches. In this way, based on the structure of the conductive pillars on the base chip 120 that can meet the electrical connection requirements of chips of different sizes, bonding the first chip 110 and the second chip 130 with different sizes and different substrates on the base chip 120 can obtain a heterogeneous integration structure 100 with multiple functions. It can be understood that the sizes of the first chip 110 and the second chip 130 meet the size requirements of functions and process conditions, and are not specifically limited.

[0073] It should be explained that the first chip 110 and the second chip 130 provided in the examples of this application are mainly illustrated by the differences between the first semiconductor substrate 111 and the third semiconductor substrate 131, and the differences in the sizes of the first chip 110 and the second chip 130, and do not specifically limit whether the functions of the first chip 110 and the second chip 130 are the same.

[0074] It should be noted that in the embodiments of the present application, in addition to the integration of the foregoing first chip 110 and the base chip 120; the integration of the first chip 110, the second chip 130 and the base chip 120, it may also include the integration of more heterogeneous chips. For example, it may also be the integration of the first chip 110, the second chip 130, a third chip (not shown in the figure) and the base chip 120; or it may be the integration of the first chip 110, the second chip 130, a third chip (not shown in the figure), a fourth chip (not shown in the figure) and the base chip 120; of course, it may also be the integration of more chips and the base chip 120. It can be understood that in different integration scenarios, the size of the base chip 120 will change to adapt to the changes in the number and size of the integrated chips. Among them, the sizes of the third chip and the fourth chip are different from those of the first chip 110 and the second chip 130, and / or the materials of the substrates of the third chip and the fourth chip are different from those of the first chip 110 and the second chip 130. For the specific structure, reference may be made to the structures of the first chip 110 and the second chip 130, and the examples of the present application will not elaborate on this any further.

[0075] In this way, both the first chip 110 and the second chip 130 are heterogeneous chips compared to the base chip 120. After the structures of the first chip 110, the second chip 130 and the base chip 120 are respectively fabricated, the second chip 130 and the first chip 110 are spaced apart and arranged on the base chip 120. Among them, the end face of the first conductive pillar 1132 away from the first semiconductor substrate 111 contacts the end face of the second conductive pillar 1232 away from the second semiconductor substrate 121. The end face of the third conductive pillar 1332 away from the third semiconductor substrate 131 contacts the end face of the second conductive pillar ၁၂၃၂ away from the second semiconductor substrate ၁၂၁.

[0076] In some examples, as Figure 3 shown, the first interconnect layer 113 is disposed on the side of the first functional layer 112 away from the first semiconductor substrate 111; the end faces of the plurality of first conductive pillars 1132 away from the first functional layer 112 are flush with the surface of the first dielectric layer 113 on the side away from the first functional layer 112.

[0077] As Figure 4 shown, the third interconnect layer 133 is disposed on the side of the third functional layer 132 away from the third semiconductor substrate 131. The end faces of the plurality of third conductive pillars 1332 away from the third functional layer 132 are flush with the surface of the third dielectric layer 1331 on the side away from the third functional layer 132.

[0078] And, as Figure 3 and Figure 4As shown, the second interconnection layer 123 is disposed on a side of the second functional layer 122 away from the second semiconductor substrate 121. One end surfaces of a plurality of second conductive posts 1232 away from the second functional layer 122 are flush with a surface of a second dielectric layer 1231 on a side away from the second functional layer 122.

[0079] In this way, when the first chip 110 and the base chip 120, and the second chip 130 and the base chip 120 are bonded, the end surfaces where the first conductive post 1132 contacts the second conductive post 1232 are flat, and the end surfaces where the third conductive post 1332 contacts the second conductive post 1232 are flat. This is beneficial to improving the tightness of the fit between the first chip 110 and the base chip 120, and between the second chip 130 and the base chip 120, avoiding defects such as voids, and can improve the electrical connection performance between the first chip 110 and the second chip 130 and the base chip 120 respectively.

[0080] In some examples, as Figure 3 and Figure 4 shown, the area of one end surface of the first conductive post 1132 away from the first functional layer 112 is larger than the area of one end surface of the first conductive post 1132 close to the first functional layer 112; and / or, as Figure 3 and Figure 4 shown, the area of one end surface of the second conductive post 1232 away from the second functional layer 122 is larger than the area of one end surface of the second conductive post 1232 close to the second functional layer 122; and / or, as Figure 4 shown, the area of one end surface of the third conductive post 1332 away from the third functional layer 132 is larger than the area of one end surface of the third conductive post 1332 close to the third functional layer 132; wherein, the end surface areas at the contact of the first conductive post 1132 and the second conductive post 1232 are the same; the end surface areas at the contact of the third conductive post 1332 and the second conductive post 1232 are the same.

[0081] Exemplarily, as Figure 3 and Figure 4 shown, the first conductive post 1132, the second conductive post 1232 and the third conductive post 1332 all include a first portion G1 extending in a direction perpendicular to the plane where the second dielectric layer 1231 is located, and a second portion G2 extending in a direction parallel to the plane where the second dielectric layer 1231 is located.

[0082] The orthographic projection area of the second portion G2 on the second dielectric layer 1231 is larger than the orthographic projection area of the first portion G1 on the second dielectric layer 1231.

[0083] The second portions G2 of the first conductive posts 1132 of the plurality of first chips 110, the second portions G2 of the third conductive posts 1332 of the plurality of second chips 130 are in contact with the second portions G2 of the second conductive posts 1232 of the base chip 120, and the first dielectric layers 1131 of the plurality of first chips 110 and the third dielectric layers 1331 of the plurality of second chips 130 are in contact with the second dielectric layer 1231 of the base chip 120.

[0084] In this way, the end face areas of the first conductive post 1132 / second conductive post 1232 / third conductive post 1332 for contacting other chips are relatively large, which can increase the probability of contact between the conductive posts and is beneficial to improving the electrical connection performance. Moreover, the end face areas at the contact between the first conductive post 1132 and the second conductive post 1232 are the same, reducing the probability of leakage and improving the precision of the electrical connection between the first chip 110 and the base chip 120. Also, the end face areas at the contact between the third conductive post 1332 and the second conductive post 1232 are the same, reducing the probability of leakage and improving the precision of the electrical connection between the second chip 130 and the base chip 120.

[0085] In some examples, as Figure 5 shown, the heterogeneous integration structure 100 further includes a portion of the material 130' of the filling layer after the filling material is cured. It is used to fix the first chip 110 and / or the second chip 130 on the base chip 120.

[0086] Exemplarily, the filling material can be the same as the materials of the first semiconductor substrate 111 and the second semiconductor substrate 121. For example, the filling material includes an insulating material.

[0087] On the other hand, the embodiments of the present application provide a semiconductor device. The semiconductor device includes the heterogeneous integration structure 100 provided in any of the above examples. Exemplarily, the functions of the semiconductor device include that the chips such as the first chip 110 and the second chip 130 integrated on the base chip 120 within the heterogeneous integration structure 100 can achieve functions, and different functions can be achieved based on the differences in the preparation materials (especially the materials of the substrates) and structures of the first chip 110, the base chip 120, and the second chip 130.

[0088] Exemplarily, the substrate of the first chip 110 is made of group III nitride, and the substrate of the base chip 120 is made of silicon-based material. For example, a substrate with hetero-integration of group III nitride (such as GaN) and silicon can be used to implement an integrated light-emitting diode. Among them, a light-emitting diode (LED) is a semiconductor light-emitting device made using the electro-luminescence principle of a semiconductor P-N junction. Gallium nitride (GaN)-based compounds are direct-bandgap wide-bandgap semiconductors, whose bandgap can be continuously adjusted from 1.8 eV to 6.2 eV and have a very high breakdown voltage, so they are widely used in high-brightness blue-green light-emitting diodes and blue-violet laser diodes (LD).

[0089] Also for example, a substrate with hetero-integration of group III nitride (such as GaN) and silicon can also be used to implement an integrated ultraviolet sensor and an application specific integrated circuit (ASIC). Among them, ASIC is considered in the integrated circuit field as an integrated circuit designed for a specific purpose. An ultraviolet sensor (i.e., UV sensor) is a sensor that can convert ultraviolet signals into measurable electrical signals using photosensitive elements through photovoltaic mode and photoconductive mode. And for GaN-based ultraviolet sensors, their accuracy is much higher than that of single-crystalline silicon, making them the most commonly used ultraviolet sensor materials.

[0090] On the other hand, as Figures 6 to 11 shown, the embodiment of the present application provides a method for preparing a hetero-integration structure 100. The preparation method includes: S100 to S400 and S600.

[0091] S100: As Figure 6 and Figure 7 shown, form the first chip 110. The first chip 110 includes a first semiconductor substrate 111, a first functional layer 112 and a first interconnect layer 113 located on the first semiconductor substrate 111. The first interconnect layer 113 includes a first dielectric layer 1131 and a plurality of first conductive posts 1132 located in the first dielectric layer 1131.

[0092] Exemplarily, as Figure 8 in (a) to Figure 8 in (f) shown, S100 includes: S110 to S160.

[0093] S110: As Figure 8 in (a) shown, provide a second initial wafer 111'.

[0094] Exemplarily, the size of the second initial wafer 111' is a 6-inch or 8-inch circular semiconductor material film layer.

[0095] S120: As shown in (a) of Figure 8 , form a first functional layer 112 on the second initial wafer 111'. By way of example, the first functional layer 112 includes one or more stacked functional layers. For example, the multiple functional layers may include film layers such as a first electrode, a second electrode, and a waveguide layer disposed on the second initial wafer 111', and the present application places no limitation thereon. By way of example, a deposition process may be used to form the multiple functional layers.

[0096] S130: As shown in (b) of Figure 8 , form a first dielectric layer 1131 on the first functional layer 112.

[0097] By way of example, using a deposition process, form the first dielectric layer 1131 on a side of the first functional layer 112 away from the second initial wafer 111'. For example, use a chemical vapor deposition process to form the first dielectric layer 1131. Also, a chemical mechanical polishing process may be used to polish the surface of the first dielectric layer 1131 to improve the surface flatness of the first dielectric layer 1131, so as to improve the bonding tightness during the subsequent hybrid bonding with other chip structures (such as the first wafer 200 before the base chip 120 is diced) through the first dielectric layer 1131 and the first conductive pillar 1132.

[0098] S140: As shown in (c) of Figure 8 , form a plurality of first through holes 10 in the first dielectric layer 1131.

[0099] By way of example, perform a photolithography and etching process on the first dielectric layer 1131 to form a plurality of first through holes 10. The cross-section of the first through hole 10 along the thickness direction Y of the first dielectric layer 1131 may be an inverted "T" shape.

[0100] S150: As shown in (d) of Figure 8 , form a first conductive pillar 1132 in the first through hole 10. One end surface of the first conductive pillar 1132 is in contact with the first functional layer 112, and the opposite end surface is flush with the plane where the opening of the first through hole 10 is located.

[0101] By way of example, use a sputtering and electroplating process to fill the first through hole 10 with a conductive material. Polish the surface of the conductive material through a chemical polishing process to form the first conductive pillar 1132, so that the surface of the first conductive pillar 1132 for contacting other chips is flat, which is beneficial to improving the electrical connection performance.

[0102] S160: As shown in (d) of Figure 8 and Figure 8As shown in (f) in [description], the side of the second initial wafer 111' away from the first interconnection layer 113 is thinned to form the second wafer 210; the second wafer 210 is cut along the thickness direction Y of the second wafer 210 to obtain a plurality of first chips 110.

[0103] Exemplarily, along the thickness direction Y of the second initial wafer 111', the film thickness of the thinned first semiconductor substrate 111 is greater than or equal to the film thickness of the first dielectric layer 1131.

[0104] It can be understood that thinning the second initial wafer 111' does not affect the function of the first chip 110, and due to the added first dielectric layer 1131, by thinning the second initial wafer 111', the thickness of the first chip 110 is reduced, thereby reducing the size of the heterogeneous integration structure 100 in the thickness direction Y.

[0105] Moreover, the second wafer 210 is cut using a laser cutting process to obtain a plurality of first chips 110 arranged in an orderly manner. Among them, the size and quantity of the first chips 110 can be set according to requirements.

[0106] It should be noted that considering the materials and thicknesses of the various layers within the second wafer 210, using a laser to cut the second wafer 210 can improve the structural size accuracy and yield of the obtained first chips 110, thereby improving the performance of the heterogeneous integration structure 100 after subsequently bonding the first chips 110 and the first wafer 200. If higher requirements are placed on the chip cutting profile, a lithography + plasma cutting process can be considered to obtain high-quality chips with a smoother profile and fewer defects.

[0107] It can be understood that the second wafer 210 before being cut into the first chips 110 has significant differences in size and material formation process from the first wafer 200 mentioned in subsequent examples. For example, the size of the second wafer 210 is 6 inches or 8 inches, while the size of the first wafer 200 is 12 inches; and the material and thickness of the wafer-level chips (first chips 110) that meet the requirements cannot be directly fabricated on the material surface of the first wafer 200 using an epitaxial growth process, that is, under the same process conditions and based on the formation principle of material growth, the material and thickness of the second wafer 210 (the first chips 110 obtained after cutting) that meet the requirements cannot be formed on the first wafer 200.

[0108] Therefore, after bonding the first chips 110 obtained by cutting the second wafer 210 to the first wafer 200 respectively and then performing cutting, not only can good functional realization of the first chips 110 and the base chips 120 (the first wafer 200 before cutting) be achieved, but also it is beneficial to improve the reliability of the electrical connection between the first chips 110 and the base chips 120 and improve the yield of the heterogeneous integration structure 100.

[0109] In some examples, such as Figure 7 shown, the preparation method further includes S500: forming the second chip 130. As Figure 4 shown, the second chip 130 includes a third semiconductor substrate 131, a third functional layer 132 and a third interconnect layer 133 located on the third semiconductor substrate 131. The third interconnect layer 133 includes a third dielectric layer 1331 and a plurality of third conductive pillars 1332 located in the third dielectric layer 1331.

[0110] The third semiconductor substrate 131 is different from both the first semiconductor substrate 111 and the second semiconductor substrate 121.

[0111] Exemplarily, as Figure 9 shown in (a) to Figure 9 shown in (f) of, S500 includes S510 to S560.

[0112] S510: As Figure 9 shown in (a) of, provide a third initial wafer 131'.

[0113] S520: As Figure 9 shown in (a) of, form the third functional layer 132 on the third initial wafer 131'.

[0114] S530: As Figure 9 shown in (b) of, form the third dielectric layer 1331 on the third functional layer 132.

[0115] S540: As Figure 9 shown in (c) of, form a plurality of third through-holes 30 in the third dielectric layer 1331.

[0116] S550: As Figure 9 shown in (d) of, form the third conductive pillars 1332 in the third through-holes 30. One end surface of the third conductive pillar 1332 is in contact with the third functional layer 132, and the opposite end surface is flush with the plane where the opening of the third through-hole 30 is located.

[0117] S560: As Figure 9 shown in (e) of, thin the side of the third initial wafer 131' away from the third interconnect layer 133 to form a third wafer 220; cut the third wafer 220 along the thickness direction Y of the third wafer 220 to obtain a plurality of second chips 130.

[0118] The preparation method of the above-mentioned second chip 130 may be the same as that of the first chip 110 (refer to the processes of S110 to S160 above, which will not be elaborated here), or different. According to the specific film layer materials and the function settings of the second chip 130, the present application does not limit this.

[0119] It should be noted that the first chip 110 and the second chip 130 provided in the examples of this application are mainly illustrated by the differences between the first semiconductor substrate 111 and the third semiconductor substrate 131, and the differences in the sizes of the first chip 110 and the second chip 130, without specifically restricting whether the functions of the first chip 110 and the second chip 130 are the same. In addition, the heterogeneous integration structure 100 may further include a third chip, a fourth chip, etc. that are different in size from both the first chip 110 and the second chip 130, and / or different in the material of the substrates from both the first chip 110 and the second chip 130. For the specific structure, reference can be made to the structures of the first chip 110 and the second chip 130, and the examples of this application will not elaborate on this.

[0120] S200: As Figure 6 and Figure 7 shown, a first wafer 200 is formed. The first wafer 200 includes a second semiconductor substrate 121, and a second functional layer 122 and a second interconnect layer 123 located on the second semiconductor substrate 121. The second interconnect layer 123 includes a second dielectric layer 1231 and a plurality of second conductive posts 1232 located in the second dielectric layer 1231.

[0121] The first semiconductor substrate 111 is different from the second semiconductor substrate 121.

[0122] Exemplarily, as Figure 10 shown in (a) to Figure 10 shown in (d) of

[0123] S210: As Figure 10 shown in (a) of

[0124] Exemplarily, the size of the first initial wafer 121' is a 12-inch circular semiconductor material film layer.

[0125] S220: As Figure 10 shown in (a) of

[0126] Exemplarily, the second functional layer 122 can be formed by a deposition process.

[0127] S230: As Figure 10 shown in (b) of

[0128] Exemplarily, a second dielectric layer 1231 is formed on a side of the second functional layer 122 away from the first initial wafer 121' by a deposition process. For example, the second dielectric layer 1231 is formed by a chemical vapor deposition process. Also, a chemical mechanical polishing process can be used to polish the surface of the second dielectric layer 1231 to improve the surface flatness of the second dielectric layer 1231, so as to improve the bonding tightness in the subsequent process of hybrid bonding with other chips (such as the first chip 110) through the second dielectric layer 1231 and the second conductive posts 1232.

[0129] S240: As Figure 10 shown in (c) thereof, a plurality of second vias 20 are formed in the second dielectric layer 1231.

[0130] Exemplarily, a photolithography and etching process is performed on the second dielectric layer 1231 to form a plurality of second vias 20. The cross-section of the second via 20 in the thickness direction of the second dielectric layer 1231 can be an inverted "T" shape.

[0131] S250: As Figure 10 shown in (d) thereof, a second conductive post 1232 is formed in the second via 20 to obtain the first wafer 200. One end surface of the second conductive post 1232 is in contact with the second functional layer 122, and the opposite end surface of the second conductive post 1232 is flush with the plane where the opening of the second via 20 is located.

[0132] Exemplarily, a sputtering and electroplating process is used to fill the second via 20 with a conductive material. The surface of the conductive material is polished by a chemical polishing process to form the second conductive post 1232, so that the surface of the second conductive post 1232 for contacting other chips is flat, which is beneficial to improving the electrical connection performance.

[0133] S300: As Figure 11 shown in (a) thereof and Figure 11 shown in (b) thereof, bond the first interconnect layer 131 of the first chip 110 with the second interconnect layer 123 of the first wafer 200 to obtain a bonded structure; the first chip 110 and the first wafer 200 are electrically connected through the first conductive posts 1132 and the second conductive posts 1232.

[0134] Exemplarily, a plurality of first chips 110 are sequentially bonded to a first wafer 200 by a chip-wafer bonding process. For example, first pick up a first chip 110 and bond it to the first wafer 200 after alignment, then pick up the second first chip 110 and bond it to the first wafer 200 after alignment, and so on, bond the first chips 110 to the areas on the first wafer 200 where the first chips 110 need to be provided in sequence. In this way, the alignment accuracy between the first chips 110 and the first wafer 200 can be improved, so as to improve the product yield of the heterogeneous integration structure 100, which is beneficial to improving the signal interaction performance of the heterogeneous integration structure 100. For example, light and electrical signals are mutually converted to achieve high-speed data transmission.

[0135] Moreover, a plurality of first chips 110 and a plurality of second chips 130 are respectively bonded to the same first wafer 200, as long as there are suitable areas on the first wafer 200 where the first chips 110 and / or the second chips 130 can be provided, so as to achieve the effect that multiple chips with various functions and structures can be provided on one first wafer 200, improve the diversity of functions that can be realized per unit area of the first wafer 200, and obtain a variety of heterogeneous integration structures 100 after subsequent cutting processes.

[0136] Among them, based on the advantages of hybrid bonding technology allowing solderless bonding, such as reducing the interconnect pitch and the thickness of the bonding interface, bonding the prepared first chips 110 to the first wafer 200 can simplify the process flow for preparing the heterogeneous integration structure 100, and at the same time improve the alignment accuracy and coupling efficiency between the first conductive posts 1132 of the first chips 110 and the second conductive posts 1232 of the first wafer 200.

[0137] Based on the situation that the preparation method further includes S500, the above S300 further includes: bonding the first interconnect layer 113 of the first chip 110, the third interconnect layer 133 of the second chip 130 to the second interconnect layer 123 of the first wafer 200 to obtain a bonded structure. The second chip 130 and the first wafer 200 are electrically connected through the third conductive posts 1332 and the second conductive posts 1232.

[0138] Exemplarily, as Figure 11 shown in (a) of

[0139] As Figure 11 shown in (b) of

[0140] In some examples, as Figure 7 and Figure 11As shown in (b) therein, the preparation method further includes S600: forming a filling layer 130 at the gaps between the chips on the first wafer 200.

[0141] Exemplarily, the filling layer 130 is formed by a spin coating process. The filling layer 130 fills the gaps between two adjacent first chips 110 (or two adjacent second chips 130, or an adjacent first chip 110 and second chip 130). The filling layer 130 can play a role in encapsulating and protecting the first chip 110 and the second chip 130, improving the stability of the first chip 110 and the second chip 130 disposed on the first wafer 200, and reducing the probability of misalignment between the first conductive posts 1132 of the first chip 110 and the second conductive posts 1232 of the first wafer 200 during subsequent processes or applications, thereby improving the performance of the heterogeneous integration structure 100 obtained after subsequent cutting.

[0142] In addition, the filling layer 130 is fabricated after bonding the first chip 110 to the first wafer 200 in this application. Compared with the process of setting a groove structure on the first wafer 200 to snap the first chip 110, the method adopted in this application is simpler, which is beneficial to improving the process efficiency of the heterogeneous integration structure 100 and the alignment accuracy between the first conductive posts 1132 and the second conductive posts 1232.

[0143] S400: As Figure 11 shown in (c) therein, cutting the bonded structure to form the heterogeneous integration structure 100.

[0144] Exemplarily, along the thickness direction Y of the first wafer 200, cutting the filling layer 130 and the first wafer 200 to obtain a plurality of heterogeneous integration structures 100. Among them, the first wafer 200 is divided into a plurality of substrate chips 120. For example, as Figure 6 shown in step S400 therein, the heterogeneous integration structure 100 includes a heterogeneous structure chip formed by the composite of the substrate chip 120 and the first chip 110. Or, as Figure 7 shown in step S400 therein, the heterogeneous integration structure 100 includes a heterogeneous structure chip formed by the composite of the substrate chip 120, the first chip 110 and the second chip 130. Or, the heterogeneous integration structure 100 includes a heterogeneous structure chip formed by the composite of various chips such as the substrate chip 120, the first chip 110 and the second chip 130 (such as a third chip, a fourth chip).

[0145] Exemplarily, a laser cutting process is adopted to cut the bonded first chip 110 and the first wafer 200. The laser cutting method can improve the flatness and yield of the edge of the formed heterogeneous integration structure 100 and reduce the probability of chipping.

[0146] It can be understood that the heterogeneous integration structure 100 may include one or more first chips 110. For example, the heterogeneous integration structure 100 includes one first chip 110. Alternatively, the heterogeneous integration structure 100 includes two first chips 110, and these two first chips 110 can be backup chips for each other. In the case where one of the first chips 110 in the prepared heterogeneous integration structure 100 fails abnormally, the other first chip 110 can operate normally, improving the yield of the heterogeneous integration structure 100. Or, the heterogeneous integration structure 100 includes one first chip 110 and one second chip 130, and the heterogeneous integration structure 100 can simultaneously possess the functions of the first chip 110 and the second chip 130.

[0147] This application does not specifically limit the number of the first chips 110 and the second chips 130 on the heterogeneous integration structure 100, and can be set according to actual needs without affecting the functions of the heterogeneous integration structure 100.

[0148] In the above preparation method of the heterogeneous integration structure 100, since the material of the first semiconductor substrate 111 in the prepared first chip 110 is different from the material of the second semiconductor substrate 121 of the first wafer 200, after separately preparing the structures of the first chip 110 and the first wafer 200, the two structures are electrically connected for heterogeneous integration. In this way, it can be ensured that the structures of the first chip 110 and the first wafer 200 can each adapt to different application scenarios or process conditions for realizing different functions. Among them, the first interconnect layer 123 of the first chip 110 is bonded to the second interconnect layer 123 of the first wafer 200, and the first chip 110 and the first wafer 200 are electrically connected through the first conductive pillar 1132 and the second conductive pillar 1231, obtaining a heterogeneous integration structure 100 with good bonding performance. Through this preparation method, the electrical connection performance of the heterogeneous chips can be improved.

[0149] It should be noted that the embodiments of the heterogeneous integration structure 100 provided in this application and the embodiments of the preparation method of the heterogeneous integration structure 100 belong to the same concept; among the technical solutions recorded in each embodiment, the technical features can be arbitrarily combined without conflict. However, it should be further noted that for the heterogeneous integration structure 100 provided in the embodiments of this application, the combination of its technical features can already solve the technical problems to be solved in this application; therefore, the heterogeneous integration structure 100 provided in the embodiments of this application may not be limited by the preparation method of the heterogeneous integration structure 100 provided in the embodiments of this application, and any heterogeneous integration structure 100 prepared by a preparation method that can form the heterogeneous integration structure 100 provided in the embodiments of this application is within the protection scope of this application.

[0150] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for preparing a heterogeneous integration structure, characterized in that Comprising: Forming a first chip, the first chip including a first semiconductor substrate and a first functional layer and a first interconnect layer located on the first semiconductor substrate, the first interconnect layer including a first dielectric layer and a plurality of first conductive pillars located in the first dielectric layer; Forming a first wafer, the first wafer including a second semiconductor substrate and a second functional layer and a second interconnect layer located on the second semiconductor substrate, the second interconnect layer including a second dielectric layer and a plurality of second conductive pillars located in the second dielectric layer; the first semiconductor substrate is different from the second semiconductor substrate; the material of the first semiconductor substrate includes non-silicon materials; the material of the second semiconductor substrate includes silicon; the size of the first chip is different from the size of the first wafer; Bonding the first interconnect layer of the first chip to the second interconnect layer of the first wafer to obtain a bonded structure; the first chip and the first wafer are electrically connected through the first conductive pillars and the second conductive pillars and bonded through the first dielectric layer and the second dielectric layer; Cutting the bonded structure to form a heterogeneous integration structure.

2. The preparation method according to claim 1, characterized in that, The method further includes: Forming a second chip, the second chip including a third semiconductor substrate and a third functional layer and a third interconnect layer located on the third semiconductor substrate, the third interconnect layer including a third dielectric layer and a plurality of third conductive pillars located in the third dielectric layer; the third semiconductor substrate is different from both the first semiconductor substrate and the second semiconductor substrate; Bonding the first interconnect layer of the first chip to the second interconnect layer of the first wafer to obtain a bonded structure, including: Bonding the first interconnect layer of the first chip, the third interconnect layer of the second chip to the second interconnect layer of the first wafer to obtain the bonded structure; the second chip and the first wafer are electrically connected through the third conductive pillars and the second conductive pillars.

3. The preparation method according to claim 2, characterized in that, The forming of the first chip includes: Providing a second initial wafer; Forming the first functional layer on the second initial wafer; Forming the first dielectric layer on the first functional layer; Forming a plurality of first through-holes in the first dielectric layer; Forming the first conductive pillars in the first through-holes to obtain the first chip; one end surface of the first conductive pillar contacts the first functional layer, and the opposite end surface is flush with the plane where the opening of the first through-hole is located; And, The forming of the second chip includes: Providing a third initial wafer; Forming the third functional layer on the third initial wafer; Forming the third dielectric layer on the third functional layer; Forming a plurality of third through-holes in the third dielectric layer; Forming the third conductive pillars in the third through-holes to obtain the second chip; one end surface of the third conductive pillar contacts the third functional layer, and the opposite end surface is flush with the plane where the opening of the third through-hole is located.

4. The preparation method according to claim 3, characterized in that, After forming the first conductive pillars in the first through-holes, it further includes: Thinning one side of the second initial wafer away from the first interconnect layer to form a second wafer; cutting the second wafer along the thickness direction of the second wafer to obtain a plurality of the first chips; And, After forming a third conductive pillar in the third through hole, the method further includes: Thinning one side of the third initial wafer away from the third interconnect layer to form a third wafer; cutting the third wafer along the thickness direction of the third wafer to obtain a plurality of the second chips.

5. The preparation method according to claim 1 or 2, characterized in that, The forming of the first wafer includes: Providing a first initial wafer; Forming the second functional layer on the first initial wafer; Forming the second dielectric layer on the second functional layer; Forming a plurality of second through holes in the second dielectric layer; Forming the second conductive pillars in the second through holes to obtain the first wafer; one end surface of the second conductive pillar is in contact with the second functional layer, and the opposite end surface of the second conductive pillar is flush with the plane where the opening of the second through hole is located.

6. The preparation method according to claim 1 or 2, characterized in that, After obtaining the bonded structure, the manufacturing method further includes: Forming a filling layer in the gap between the chips on the first wafer; The cutting of the bonded structure includes: Cutting the filling layer and the first wafer along the thickness direction of the first wafer to obtain a plurality of the heterogeneous integration structures; wherein, the first wafer is divided into a plurality of base chips.

7. The preparation method according to claim 2, wherein The size of the first chip is different from the size of the second chip.

8. The preparation method according to claim 2, characterized in that, The material of the third semiconductor substrate includes a non-silicon material.

9. The preparation method according to claim 2, wherein, The first conductive pillar, the second conductive pillar and the third conductive pillar each include a first portion extending in a direction perpendicular to the plane of the second dielectric layer and a second portion extending in a direction parallel to the plane of the second dielectric layer; The bonding of the first interconnect layer of the first chip, the third interconnect layer of the second chip and the second interconnect layer of the first wafer to obtain the bonded structure includes: Bonding the second portions of the first conductive pillars of a plurality of the first chips, the second portions of the third conductive pillars of a plurality of the second chips and the second portions of the second conductive pillars of the first wafer, and bonding the first dielectric layers of a plurality of the first chips, the third dielectric layers of a plurality of the second chips and the second dielectric layer of the first wafer to obtain the bonded structure.

10. A heterogeneous integration structure, characterized in that, Includes: A first chip, including a first semiconductor substrate and a first functional layer and a first interconnect layer located on the first semiconductor substrate, the first interconnect layer including a first dielectric layer and a plurality of first conductive pillars located in the first dielectric layer; A base chip, including a second semiconductor substrate and a second functional layer and a second interconnect layer located on the second semiconductor substrate, the second interconnect layer including a second dielectric layer and a plurality of second conductive pillars located in the second dielectric layer; Wherein, the first semiconductor substrate is different from the second semiconductor substrate; the material of the first semiconductor substrate includes a non-silicon material; the material of the second semiconductor substrate includes silicon; the end surface of the first conductive pillar away from the first semiconductor substrate is in contact with the end surface of the second conductive pillar away from the second semiconductor substrate, and the surface of the first dielectric layer away from the first semiconductor substrate is in contact with the surface of the second dielectric layer away from the first semiconductor substrate.

11. The heterogeneous integration structure according to claim 10, characterized in that, The heterogeneous integration structure further includes: The second chip includes a third semiconductor substrate, a third functional layer, and a third interconnect layer located on the third semiconductor substrate. The third interconnect layer includes a third dielectric layer and a plurality of third conductive posts located in the third dielectric layer; The third semiconductor substrate is different from the first semiconductor substrate and the second semiconductor substrate; the end face of the third conductive post away from the third semiconductor substrate contacts the end face of the second conductive post away from the second semiconductor substrate; the second chip and the first chip are spaced apart and disposed on the base chip.

12. The heterogeneous integration structure according to claim 11, wherein The size of the first chip is different from the size of the second chip.

13. The heterogeneous integration structure according to claim 11, wherein, The material of the third semiconductor substrate includes a non-silicon material.

14. The heterogeneous integration structure according to claim 11, wherein The first interconnect layer is disposed on a side of the first functional layer away from the first semiconductor substrate; one end face of the plurality of first conductive posts away from the first functional layer is flush with a side surface of the first dielectric layer away from the first functional layer; The third interconnect layer is disposed on a side of the third functional layer away from the third semiconductor substrate; one end face of the plurality of third conductive posts away from the third functional layer is flush with a side surface of the third dielectric layer away from the third functional layer; And, The second interconnect layer is disposed on a side of the second functional layer away from the second semiconductor substrate; one end face of the plurality of second conductive posts away from the second functional layer is flush with a side surface of the second dielectric layer away from the second functional layer.

15. The heterogeneous integration structure according to claim 11, wherein The area of the end face of the first conductive post away from the first functional layer is larger than the area of the end face of the first conductive post close to the first functional layer; and / or, The area of the end face of the second conductive post away from the second functional layer is larger than the area of the end face of the second conductive post close to the second functional layer; and / or, The area of the end face of the third conductive post away from the third functional layer is larger than the area of the end face of the third conductive post close to the third functional layer; Wherein, the end face areas at the contact of the first conductive post and the second conductive post are the same; the end face areas at the contact of the third conductive post and the second conductive post are the same.

16. The heterogeneous integration structure according to claim 15, wherein, The first conductive post, the second conductive post, and the third conductive post each include a first portion extending in a direction perpendicular to the plane of the second dielectric layer and a second portion extending in a direction parallel to the plane of the second dielectric layer; the orthographic projection area of the second portion on the second dielectric layer is larger than the orthographic projection area of the first portion on the second dielectric layer; The second portions of the first conductive posts of the plurality of first chips, the second portions of the third conductive posts of the plurality of second chips contact the second portions of the second conductive posts of the base chip, and the first dielectric layers of the plurality of first chips and the third dielectric layers of the plurality of second chips contact the second dielectric layer of the base chip.

17. A semiconductor device, characterized in that, Comprising the heterogeneous integration structure according to any one of claims 10 to 16.

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