Bonded wafer polishing method

Abstract

This invention provides a method for polishing bonded wafers, comprising: providing a bonded wafer including a substrate layer, a top silicon layer, and an insulating buried oxide layer; performing a grinding process on the top silicon layer, wherein the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer; providing a carrier corresponding to the obtained thickness, and placing the bonded wafer in the carrier to perform a double-sided polishing process; wherein, before providing the substrate layer and the top silicon layer, a matching process is performed based on the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer, wherein the matching is set as x for the thickness of the carrier, y for the thickness of the substrate, and z for the target thickness of the top silicon layer, and x-y+0.5≤z≤x-y+2, and the thickness of the carrier and the thickness of the substrate are obtained after matching. This invention can improve the thickness uniformity of the top silicon layer after double-sided polishing and can reduce the wear of the carrier.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for polishing bonding wafers. Background Technology

[0002] Silicon on insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. With the rapid development of new energy vehicles, automotive-grade SOI materials are becoming increasingly integrated with automotive chips. The transition from 200mm to 300mm SOI is an inevitable development trend, and high uniformity and polishing stability are particularly important.

[0003] Uneven thickness of the top silicon layer in SOI wafers can lead to device performance instability, inconsistent current density in local electron channels, uneven thermal effects, and even linewidth variations. Double-sided polishing of SOI wafers is one of the main processes in wafer manufacturing. Its primary function is to eliminate stress damage caused by shearing and thinning, improve wafer uniformity, and obtain wafers with high flatness and low roughness. The working principle of double-sided polishing is to achieve the goal of low roughness through the combined action of polishing slurry and mechanical action. During double-sided polishing, the SOI wafer is placed in a planetary wheel bushing. Driven by the inner and outer rings of the double-sided polishing machine, the planetary wheel rotates on a polishing disk with a polishing pad, thereby achieving the purpose of polishing and removing imperfections.

[0004] As a key component in the double-sided polishing process, the selection of the planetary wheel is crucial. Its mechanical properties, microstructure, and quality characteristics directly affect the uniformity of the top silicon layer thickness after polishing. Furthermore, because the wafer removal rate in a double-sided polishing machine does not change linearly with polishing time, the laser thickness measurement function of the double-sided polishing machine will fail when the top silicon layer in an SOI wafer is less than 10μm. The subsequent thickness removal time will then be calculated based on the removal rate within the laser-measurable thickness range. Therefore, selecting a suitable carrier, adjusting the disk type and pressure distribution between the polishing disks, and rationally matching the carrier and the thickness of the top silicon layer can achieve controllable thickness at the end of double-sided polishing, thereby improving the flatness of the top silicon layer. Summary of the Invention

[0005] The purpose of this invention is to provide a method for polishing bonded wafers, which improves the uniformity of the thickness of the top silicon layer after double-sided polishing and reduces the wear of the carrier.

[0006] To achieve the above objectives, the present invention provides a method for polishing bonded sheets, comprising:

[0007] The bonding wafer is provided, comprising a substrate layer, a top silicon layer, and an insulating buried oxide layer;

[0008] A polishing process is performed on the top silicon layer, and the thickness of the top silicon layer after polishing is greater than the target thickness of the top silicon layer;

[0009] A carrier corresponding to the obtained thickness is provided, and the bonding sheet is placed in the carrier to perform a double-sided polishing process;

[0010] Before providing the bonding wafer, a matching process is performed based on the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer. The matching is set as follows: the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, where x-y+0.5≤z≤x-y+2. The units of the thickness of the carrier, the thickness of the substrate, and the target thickness of the top silicon layer are μm. After matching, the thickness of the carrier and the thickness of the substrate layer are obtained.

[0011] Optionally, the thickness of the substrate layer is 750 μm to 800 μm.

[0012] Optionally, the thickness difference of the substrate layer is less than 0.15 μm.

[0013] Optionally, the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer by 8 μm to 12 μm.

[0014] Optionally, the thickness difference of the top silicon layer after grinding is 0.5 μm to 1.5 μm.

[0015] Optionally, the target thickness of the top silicon layer has been obtained before matching.

[0016] Optionally, after performing the double-sided polishing process, the thickness difference of the top silicon layer is less than 0.2 μm.

[0017] Optionally, the polishing rate of the double-sided polishing process is 0.5 μm / min to 2.5 μm / min.

[0018] Optionally, the double-sided polishing process is performed using a laser thickness gauge for segmented monitoring.

[0019] Optionally, the vehicle is a planetary wheel.

[0020] In the bonding wafer polishing method provided by the present invention, a bonding wafer is provided, comprising a substrate layer, a top silicon layer, and an insulating buried oxide layer; a grinding process is performed on the top silicon layer, and the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer; a carrier corresponding to the obtained thickness is provided, and the bonding wafer is placed in the carrier to perform a double-sided polishing process; wherein, before providing the substrate layer and the top silicon layer, a matching is performed according to the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer, the matching is set as the thickness of the carrier is x, the thickness of the substrate is y, and the target thickness of the top silicon layer is z, x-y+0.5≤z≤x-y+2, wherein the units of the thickness of the carrier, the thickness of the substrate, and the target thickness of the top silicon layer are μm, and the thickness of the carrier and the thickness of the substrate are obtained after matching. This invention obtains the thickness of the carrier and the thickness of the substrate by matching the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate. The double-sided polishing process is performed using the carrier with the matching thickness. This can effectively control the amount of polishing removal of the top silicon layer, improve the thickness uniformity of the top silicon layer after double-sided polishing, and reduce the wear of the carrier. Attached Figure Description

[0021] Figure 1 This is a flowchart of a bonding sheet polishing method provided in an embodiment of the present invention.

[0022] Figure 2 This is a graph showing the relationship between the target thickness of the top silicon layer and the polishing rate in a bonding wafer polishing method provided in an embodiment of the present invention.

[0023] Figure 3 This is a graph showing the relationship between the target thickness of the top silicon layer and the thickness difference of the top silicon layer in a bonding wafer polishing method provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0025] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, and “one end” and “the other end” generally refer to two corresponding parts. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0026] Figure 1 This is a flowchart of the bonding sheet polishing method provided in this embodiment. Please refer to it. Figure 1 This embodiment provides a method for polishing a bonding sheet, including:

[0027] Step S1: Provide a bonding wafer, comprising a substrate layer, a top silicon layer, and an insulating buried oxide layer;

[0028] Step S2: Perform a polishing process on the top silicon layer. After polishing, the thickness of the top silicon layer is greater than the target thickness of the top silicon layer.

[0029] Step S3: Provide a carrier corresponding to the obtained thickness, place the bonding sheet in the carrier and perform a double-sided polishing process;

[0030] Before providing the substrate and top silicon layer, a matching process is performed based on the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate. The matching is set as follows: the thickness of the carrier is x, the thickness of the substrate is y, and the target thickness of the top silicon layer is z, with x-y+0.5≤z≤x-y+2. The units of the thickness of the carrier, the thickness of the substrate, and the target thickness of the top silicon layer are μm. After matching, the thickness of the carrier and the thickness of the substrate are obtained.

[0031] The bonding sheet polishing method provided in this embodiment will be described in detail below.

[0032] Step S1: Provide a bonding wafer comprising a substrate layer, a top silicon layer, and an insulating buried oxide layer. The substrate layer and the top silicon layer are isolated by the insulating buried oxide layer and bonded together to form the bonding wafer (the substrate layer, the insulating buried oxide layer, and the top silicon layer are stacked sequentially from bottom to top). In this embodiment, the diameter of the substrate layer and the top silicon layer can be 200mm to 300mm, the thickness of the substrate layer can be 750μm to 800μm, and the thickness difference of the substrate layer can be less than 0.15μm. The thickness difference is the difference between the maximum thickness and the minimum thickness, but is not limited to this. After bonding, the bonding wafer is further subjected to a strengthening heat treatment and edge chamfering treatment.

[0033] Before providing the bonding wafer, the target thickness of the polished top silicon layer can be known during the design phase. This target thickness is a design requirement, and therefore, it is obtained before matching. Matching is performed based on the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate. The matching is set as follows: the thickness of the carrier is x, the thickness of the substrate is y, and the target thickness of the top silicon layer is z, where x - y + 0.5 ≤ z ≤ x - y + 2. The units for the thicknesses of the carrier, substrate, and top silicon layer are μm. After matching, the thicknesses of the carrier and substrate are obtained.

[0034] In this embodiment, the carrier is a planetary wheel with several workpiece holes. During subsequent double-sided polishing, the bonding sheet is positioned within the workpiece holes of the planetary wheel. The thickness of the planetary wheel affects the amount of polishing removal of the bonding sheet, and the thickness of the planetary wheel represents the depth of the workpiece holes. The planetary wheel includes a stainless steel bushing and a DLC (diamond-like carbon) coating. In this embodiment, the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate are related and matched. Selecting a carrier of appropriate thickness can effectively control the amount of polishing removal of the top silicon layer, improve the uniformity of the top silicon layer thickness after double-sided polishing, and reduce carrier wear. Therefore, during the design phase, it is necessary to first determine the thickness of the carrier and the thickness of the substrate by considering the matching relationship between the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate. Given that the target thickness of the top silicon layer is z, the thickness of the carrier and the thickness of the substrate should satisfy x-y+0.5≤z≤x-y+2. During the design phase, if the thickness of the substrate layer has been set, the thickness of the carrier is obtained by setting x-y+0.5≤z≤x-y+2; if the thickness of the carrier has been set, the thickness of the substrate layer is obtained by setting x-y+0.5≤z≤x-y+2, and a substrate layer with the set thickness is provided when providing the substrate layer; if neither the thickness of the carrier nor the thickness of the substrate layer has been set, the thickness of the carrier and the thickness of the substrate layer are freely set according to x-y+0.5≤z≤x-y+2 to satisfy the matching relationship.

[0035] Step S2: Perform a polishing process on the top silicon layer, so that the thickness of the top silicon layer after polishing is greater than the target thickness of the top silicon layer. In this embodiment, the thickness of the top silicon layer after polishing can be 8μm to 12μm greater than the target thickness of the top silicon layer (i.e., the thickness of the top silicon layer after polishing is 8μm to 12μm greater than the target thickness of the top silicon layer), and the thickness difference of the top silicon layer after polishing can be 0.5μm to 1.5μm, but is not limited to this.

[0036] Step S3: After matching during the design phase, the thickness of the carrier is known. A carrier with the matched thickness (this thickness is the thickness of the matched carrier) is provided, and the bonding wafer is placed in the carrier to perform a double-sided polishing process. In this embodiment, after performing the double-sided polishing process using the carrier with the matched thickness, the thickness difference of the top silicon layer can be less than 0.2 μm, improving the uniformity of the top silicon layer thickness after double-sided polishing. The polishing rate of the double-sided polishing process can be 0.5 μm / min to 2.5 μm / min, and the double-sided polishing process is performed using a laser thickness gauge for segmented monitoring.

[0037] Figure 2 This is a graph showing the relationship between the target thickness of the top silicon layer and the polishing rate in the bonding wafer polishing method provided in this embodiment. Figure 3 This diagram illustrates the relationship between the target thickness of the top silicon layer and the thickness difference of the top silicon layer in the bonding wafer polishing method provided in this embodiment. Please refer to... Figure 2 The x-axis represents the target thickness of the top silicon layer, and the y-axis represents the polishing rate. In the x-axis, x is the thickness of the carrier, and y is the thickness of the substrate. xy-0.5 to x-y+2.5 indicates an increasing target thickness of the top silicon layer. When the target thickness of the top silicon layer reaches x-y+0.5, the polishing rate begins to stabilize. Please refer to [reference needed]. Figure 3 The horizontal axis represents the target thickness of the top silicon layer, and the vertical axis represents the thickness difference of the top silicon layer. xy-0.5 to x-y+2.5 indicates an increasing target thickness of the top silicon layer. When the target thickness of the top silicon layer is less than x-y+2.5, the thickness difference of the top silicon layer is less than or equal to 0.2 μm. To ensure both the polishing rate and a small thickness difference of the top silicon layer, the preferred target thickness of the top silicon layer is greater than or equal to x-y+0.5 and less than or equal to x-y+2, i.e., the target thickness of the top silicon layer is z, and x-y+0.5≤z≤x-y+2. The units for the thickness of the carrier, the substrate, and the target thickness of the top silicon layer are μm.

[0038] The following example illustrates the bonding sheet polishing method provided in this embodiment.

[0039] A bonding wafer is provided, comprising a substrate layer, a top silicon layer, and an insulating buried oxide layer. The top silicon layer in the bonding wafer is thinned by grinding using a biaxial polishing machine, with a grinding removal amount greater than 20 μm, preferably greater than 25 μm. The thickness of the top silicon layer after grinding is greater than 10 μm, preferably greater than 13 μm, and the thickness difference of the top silicon layer after grinding is less than 1 μm. Then, the bonding wafer is cleaned individually, and the thickness of the top silicon layer is measured after cleaning using a Fourier transform infrared absorption spectrometer (FTIR) for laser thickness measurement. Taking a carrier planetary gear with a thickness of 780 μm and a substrate layer thickness of 775 μm in the bonded wafer as an example, 75 bonded wafers were provided, divided into 5 groups of 15 wafers each. Each group underwent a double-sided polishing process, which consisted of two stages: rough polishing and fine polishing. In the rough polishing stage, the polishing slurry had a pH of 10.9, a temperature controlled at 24℃, a liquid-to-water ratio of 1:25, and a polishing pressure of 650 kg. In the fine polishing stage, the polishing slurry had a pH of 9.0, a temperature controlled at 22℃, a liquid-to-water ratio of 1:30, and a polishing pressure of 400 kg. The initial thickness of the top silicon layer was measured to be 788 μm using a laser thickness gauge. After double-sided polishing, the final thicknesses of the top silicon layer were measured using a laser thickness gauge as z1 = 5 μm, z2 = 5.5 μm, z3 = 6 μm, z4 = 6.5 μm, and z5 = 7 μm (z1 to z5 are the average thicknesses of each group of bonded wafers). Since the thickness of the planetary gear on the carrier is 780 μm and the thickness of the substrate layer in the bonding wafer is 775 μm, i.e., x = 780 μm, y = 775 μm, the target thickness z of the top silicon layer should be within the range of (x-y+0.5, x-y+2), i.e. 5.5 μm ≤ z ≤ 7 μm. The thicknesses measured by z2, z3, z4, and z5 satisfy the matching relationship between the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer. This can effectively control the amount of polishing removal of the top silicon layer, improve the thickness uniformity of the top silicon layer after double-sided polishing, and reduce the wear of the carrier.

[0040] In summary, the bonding wafer polishing method provided by this invention provides a bonding wafer comprising a substrate layer, a top silicon layer, and an insulating buried oxide layer; a grinding process is performed on the top silicon layer, and the thickness of the top silicon layer after grinding is greater than the target thickness of the top silicon layer; a carrier corresponding to the obtained thickness is provided, and the bonding wafer is placed in the carrier to perform a double-sided polishing process; wherein, before providing the substrate layer and the top silicon layer, a matching is performed based on the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer, the matching is set as the thickness of the carrier being x, the thickness of the substrate being y, and the target thickness of the top silicon layer being z, x-y+0.5≤z≤x-y+2, wherein the units of the thickness of the carrier, the thickness of the substrate, and the target thickness of the top silicon layer are μm, and the thickness of the carrier and the thickness of the substrate are obtained after matching. This invention obtains the thickness of the carrier and the thickness of the substrate by matching the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate. The double-sided polishing process is performed using the carrier with the matching thickness. This can effectively control the amount of polishing removal of the top silicon layer, improve the thickness uniformity of the top silicon layer after double-sided polishing, and reduce the wear of the carrier.

[0041] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for polishing bonded sheets, characterized in that, include: The bonding wafer is provided, comprising a substrate layer, a top silicon layer, and an insulating buried oxide layer; A polishing process is performed on the top silicon layer, and the thickness of the top silicon layer after polishing is greater than the target thickness of the top silicon layer; A carrier corresponding to the obtained thickness is provided, and the bonding sheet is placed in the carrier to perform a double-sided polishing process; Before providing the bonding wafer, a matching process is performed based on the target thickness of the top silicon layer, the thickness of the carrier, and the thickness of the substrate layer. The matching is set as follows: the thickness of the carrier is x, the thickness of the substrate layer is y, and the target thickness of the top silicon layer is z, where x-y+0.5≤z≤x-y+2. The units of the thickness of the carrier, the thickness of the substrate, and the target thickness of the top silicon layer are μm. After matching, the thickness of the carrier and the thickness of the substrate layer are obtained.

2. The bonding wafer polishing method as described in claim 1, characterized in that, The thickness of the substrate layer is 750μm to 800μm.

3. The bonding wafer polishing method as described in claim 2, characterized in that, The thickness difference of the substrate layer is less than 0.15 μm.

4. The bonding wafer polishing method as described in claim 1, characterized in that, After grinding, the thickness of the top silicon layer is 8μm to 12μm greater than the target thickness of the top silicon layer.

5. The bonding wafer polishing method as described in claim 4, characterized in that, The thickness difference of the top silicon layer after grinding is 0.5μm to 1.5μm.

6. The bonding wafer polishing method as described in claim 1, characterized in that, The target thickness of the top silicon layer was obtained before matching was performed.

7. The bonding wafer polishing method as described in claim 1, characterized in that, After performing the double-sided polishing process, the thickness difference of the top silicon layer is less than 0.2 μm.

8. The bonding wafer polishing method as described in claim 1, characterized in that, The polishing rate of the double-sided polishing process is 0.5 μm / min to 2.5 μm / min.

9. The bonding wafer polishing method as described in claim 1, characterized in that, The double-sided polishing process is performed using a laser thickness gauge for segmented monitoring.

10. The bonding wafer polishing method as described in claim 1, characterized in that, The vehicle in question is a planetary wheel.

Images