A via fusion method to accelerate EDA circuit parasitic resistance extraction

Abstract

A via fusion method for accelerating parasitic resistance extraction in EDA circuits includes: merging interconnects in a circuit, performing trapezoidal processing on the merged interconnects to obtain multiple quadrilaterals and / or triangles; creating a via set with the same connection relationship and sorting the elements in the via set; establishing an R-Tree model for the via set; traversing the elements in the sorted via set and using the rtree::query(::nearest(viaBox,num),results) interface to find the nearest multiple vias; merging the found vias and the searched vias into a virtual via, and calculating the equivalent resistance of the virtual via; and deleting the found via and the searched via from a spatial index tree. The method of the present invention logically merges multiple vias in a neighboring area into an equivalent via, and defines the resistance of the equivalent via based on parallel characteristics, thereby avoiding precision loss as much as possible, thereby reducing the number of resistors, improving extraction performance, and reducing the size of the netlist.

Description

Technical Field

[0001] The present invention relates to the technical field of automated design of semiconductor integrated circuits, and in particular to a through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits. Background Art

[0002] When integrated circuit process technology is reduced to below 0.18um, signal delays caused by interconnects account for over 70% of all factors contributing to signal delay. Parasitic resistance and capacitance on interconnects are the primary culprits of signal delay, making tools for extracting parasitic parameters indispensable. The three major international EDA software vendors (Synopsys, Cadence, and Mentor) have all developed their own parasitic parameter extraction tools. Beijing HuaDa JiuTian Technology Co., Ltd. also has its own proprietary parasitic parameter extraction tool, RCExplorer.

[0003] Advanced process chips often integrate massive (hundreds of millions) of transistors, with metal wiring layers exceeding 10 and a rapidly increasing number of metal interconnects. This places immense computational pressure on parasitic parameter extraction tools, creating a sharp conflict between the sheer volume of data and the demands of fast chip design. To address this conflict, major vendors are continuously pursuing high-performance parasitic parameter extraction tools. Currently, mainstream technologies include chip slicing, parallel computing, capacitance dimensionality reduction (3D to 2.5D conversion), and other speed-up methods, including those designed to accelerate the solution of very large systems of equations.

[0004] like Figure 1 As shown, Figure 1 Figure a is a schematic diagram of single Via (through hole) connectivity. Figure 1 Figure b in the figure shows a Via Array (VIA) connection. Unlike the single VIA connections used in mature processes, advanced processes often use a matrix-distributed VIA array for intermetallic connections. The number of VIAs can increase by tens or even hundreds of times. This increase in VIAs means that extraction tools must extract more resistors, which is a major factor contributing to the strain on parasitic extraction in advanced processes and also impacts the performance of Static Timing Analysis (STA). Summary of the Invention

[0005] In order to address the shortcomings of the existing technology, the purpose of the present invention is to provide a via fusion method for accelerating the parasitic resistance extraction of EDA circuits. A via fusion algorithm is used to logically merge several vias in adjacent areas into an equivalent large via, and the resistance of the equivalent via is defined according to the parallel characteristics, thereby avoiding precision loss as much as possible. Ultimately, the method achieves the effect of reducing the number of resistors, improving extraction performance, reducing the size of the netlist, and positively affecting STA performance.

[0006] In order to achieve the above-mentioned object, the present invention provides a through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits, comprising the following steps:

[0007] Merging interconnection lines in the circuit, and performing trapezoidal processing on the merged interconnection lines to obtain a plurality of quadrilaterals and / or triangles;

[0008] Create a through-hole set with the same connection relationship and sort the elements in the through-hole set;

[0009] Establishing an R-Tree model of the through-hole set;

[0010] Traverse the elements in the sorted through-hole set and use the graph nearest target query interface of the spatial index tree to find the nearest multiple through-holes;

[0011] Merging the found through hole and the searched through hole into a virtual through hole, and calculating the equivalent resistance of the virtual through hole;

[0012] Delete the found through-holes and the through-holes that have been found from the spatial index tree.

[0013] Furthermore, the step of merging the interconnection lines in the circuit includes: removing the overlapping parts of the metal lines in the same layer, and merging the interconnection lines into a polygon.

[0014] Furthermore, in the set of through holes having the same connection relationship, the upper layer graphics connected to each through hole are the same graphics, and the lower layer graphics connected to each through hole are also the same graphics.

[0015] Furthermore, the step of sorting the elements in the through-hole set further includes: sorting the through-holes from left to right and from top to bottom according to their positions in the through-hole matrix.

[0016] Furthermore, the step of traversing the elements in the sorted via set and finding the nearest multiple vias using the graphical nearest target query interface of the spatial index tree further includes: using the rtree::query(::nearest(viaBox,num), results) interface, passing in the number of nearest vias to be found through the parameter num, viaBox is the outer boundary rectangle of the element to be found in the via set, and results is used to save the found object.

[0017] Furthermore, the parameter num=9.

[0018] Furthermore, the step of calculating the equivalent resistance of the virtual via includes: calculating the parallel resistance of all sub-vias combined into one virtual via, and the equivalent resistance of the virtual via is equal to the parallel resistance of all sub-vias.

[0019] Furthermore, the trapezoidal processing step further includes: using a set of parallel lines to divide a polygon into multiple simple shapes: taking each vertex of the polygon as a starting point, extending a line parallel to the X-axis or Y-axis into the interior of the polygon, and connecting the other end of the extension line to the polygon to form a number of quadrilaterals or triangles with parallel upper and lower bases.

[0020] To achieve the above-mentioned objectives, the present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits as described above.

[0021] To achieve the above objectives, the present invention also provides a computer-readable storage medium, which stores at least one instruction, and the instruction is loaded and executed by a processor to implement the through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits as described above.

[0022] The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits provided by the present invention has the following beneficial effects compared with the prior art:

[0023] By using through-hole fusion technology, several through-holes in adjacent areas are logically merged into an equivalent through-hole, and the resistance of the equivalent through-hole is defined according to the parallel characteristics, avoiding precision loss as much as possible. Ultimately, the number of resistors is reduced, the extraction performance is improved, the netlist size is reduced, and the STA performance is positively affected.

[0024] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 A schematic diagram of a Via array according to the matrix distribution of the present invention;

[0027] Figure 2 A flow chart of a via fusion method for accelerating parasitic resistance extraction of EDA circuits according to an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of interconnection lines according to an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of a ViasGroup created according to an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of merging a 3×3 Via array according to an embodiment of the present invention;

[0031] Figure 6 FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0033] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0034] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0035] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative and non-restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more." "Plurality" should be understood as two or more.

[0036] In an embodiment of the present invention, a via fusion method for accelerating the parasitic resistance extraction of EDA circuits is provided. In order to improve the performance of post-design parasitic parameter extraction of advanced process chips that widely use matrix-distributed Via Arrays (via arrays), while ensuring the accuracy of resistance extraction, a ViaMerge method is designed and developed. The ViaMerge method is integrated into the resistance extraction process, and multi-threading technology is used to realize parallel processing of Via Arrays in multiple partitions.

[0037] Physically, the matrix-distributed via array is designed to increase connectivity reliability (i.e., a single via disconnection does not affect overall circuit connectivity). Its resistance contribution is essentially the same as that of a single-via process. Therefore, during the extraction phase, the via array can be merged into a single via (ViaMerge technology). This approach yields minimal difference in resistance calculation compared to methods without via merging. Using ViaMerge technology for parasitic extraction in advanced process chip designs has proven to significantly improve performance with minimal impact on extraction accuracy.

[0038] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0039] Figure 2 The flowchart of the through-hole fusion method for accelerating the parasitic resistance extraction of EDA circuits according to an embodiment of the present invention will be referred to below. Figure 2 , the through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits of the present invention is described in detail.

[0040] First, in step 101, interconnect lines in a circuit are merged.

[0041] like Figure 3 As shown in a, the interconnection lines (metal1, metal2) on the same metal layer have overlapping parts. The interconnection lines are merged, the overlapping parts are removed, and the lines are merged into a polygon, as shown in Figure 3 As shown in b, the interconnected lines in the same layer are merged into the same polygon.

[0042] In step 102, the merged interconnect lines are subjected to trapezoidal processing.

[0043] In an embodiment of the present invention, the trapezoidalization process refers to a geometric simplification method that uses a set of parallel lines to cut a complex polygon into multiple simple figures. The specific method is: starting from each vertex of the polygon, make an extension line parallel to the X-axis (or Y-axis) into the interior of the polygon, and connect the other end of the extension line to the polygon, thereby forming a number of quadrilaterals (such as rectangles and parallelograms) or triangles (the uppermost or smallest part of the polygon) with parallel upper and lower bases. After the merged interconnected lines are trapezoidalized, there are only one or more quadrilaterals and triangles, and most of them are rectangles, which will bring great convenience to the subsequent computational geometry algorithm processing. Figure 3 As shown in b, before the trapezoidal processing, the interconnects are all polygonal (i.e. non-rectangular, such as metal1 is an L-shaped polygon and metal2 is an F-shaped polygon). Figure 3 As shown in c, after trapezoidal processing, the interconnection lines are only quadrilaterals.

[0044] In step 103, a Via set (through-hole set) with the same connection relationship is created. The upper layer graphics connected by each Via in the set are the same graphics, and the lower layer graphics connected by each Via are also the same graphics.

[0045] In the embodiment of the present invention, the Via set with the same connection relationship is defined as ViasGroup. Figure 4 As shown, ViasGroup1 and ViasGroup2 are created respectively, and the upper and lower layer graphics of all Via connections in ViasGroup1 and ViasGroup2 are the same graphic (metal1, metal2).

[0046] The above steps 101 to 103 can be based on the existing parasitic resistance extraction process without increasing the extraction pressure.

[0047] In step 104, the elements in the ViasGroup are sorted. The sorting rule is to sort from left to right and from bottom to top according to the position of the vias.

[0048] In step 105, an R-Tree model of ViasGroup is established.

[0049] The R-Tree model (boost::geometry::index::rtree) is a spatial index data structure that can quickly implement spatial graph search and positioning with a computational complexity of 0(logN).

[0050] In step 106, the elements in the sorted ViasGroup are traversed and the nearest target query interface of the spatial index tree (boost::gometry::indes::rtree, hereinafter abbreviated as rtree) is used to obtain a specific number of targets closest to the user-defined graph (the code is rtree::query(::nearest(viaBox,num), results). The number of the nearest vias to be searched can be passed in as the parameter num, viaBox is the outer bounding rectangle of the element to be searched in the ViasGroup, and results is used to store the found objects). According to experience, setting num = 9 usually achieves a balance between performance and accuracy. Under this rule, the 3×3 Via Array will be merged, such as Figure 5 shown.

[0051] In step 107, the found Via and the searched Via are merged into a virtual NewVia (new through hole), and the resistance of NewVia is equal to the parallel resistance of its sub-Vias (R=1 / (1 / R1+1 / R2...));

[0052] In step 108, the found Via is deleted from the rtree along with the searched Via. This prevents the Via from being found repeatedly and can also dynamically reduce the size of the rtree, indirectly improving the search performance of the rtree.

[0053] In step 109, after all elements in the ViasGroup and all ViasGroups are traversed, the entire ViaMerge process ends.

[0054] The present invention provides a through-hole fusion method for accelerating parasitic resistance extraction in EDA circuits. Targeting advanced process chips that widely adopt matrix-distributed Via Arrays, the method uses the ViaMerge method to strictly merge multiple Vias with the same connection relationship into an equivalent large Via. Verified by a large number of actual test cases, the algorithm effectively reduces the number of extracted resistors (by an average of 21%), reduces memory usage (by an average of 15% peak memory usage), improves post-simulation resistance extraction performance (by an average of more than 13% speed increase), reduces netlist size (by an average of 26%), and positively impacts STA performance (by more than 8%), thereby enhancing the competitiveness of the parasitic parameter extraction tool (RCExplorer) in both the international and domestic markets.

[0055] In an embodiment of the present invention, an electronic device is further provided. Figure 6 FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Figure 6 As shown, the electronic device of the present invention includes a processor 601 and a memory 602, wherein:

[0056] The memory 602 stores a computer program. When the computer program is read and executed by the processor 601 , the computer program executes the steps in the embodiment of the via fusion method for accelerating the parasitic resistance extraction of EDA circuits as described above.

[0057] In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of the through-hole fusion method embodiment for accelerating the extraction of parasitic resistance of EDA circuits as described above when running.

[0058] In this embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0059] Those skilled in the art will understand that the foregoing descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will be able to modify the technical solutions described in the foregoing embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits, characterized in that: The following steps are involved: Merging interconnection lines in the circuit, and performing trapezoidal processing on the merged interconnection lines to obtain a plurality of quadrilaterals and / or triangles; Create a through-hole set with the same connection relationship and sort the elements in the through-hole set; Establishing an R-Tree model of the through-hole set; Traverse the elements in the sorted through-hole set and use the graph nearest target query interface of the spatial index tree to find the nearest multiple through-holes; Merging the found through hole and the searched through hole into a virtual through hole, and calculating the equivalent resistance of the virtual through hole; Delete the found through-holes and the through-holes that have been found from the spatial index tree.

2. The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to claim 1, characterized in that: The step of merging interconnection lines in the circuit includes: removing overlapping parts of metal lines in the same layer and merging the interconnection lines into a polygon.

3. The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to claim 1, characterized in that: In the set of through holes with the same connection relationship, the upper layer graphics connected to each through hole are the same graphics, and the lower layer graphics connected to each through hole are also the same graphics.

4. The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to claim 1, characterized in that: The step of sorting the elements in the through-hole set further includes sorting the through-holes from left to right and from top to bottom according to their positions in the through-hole matrix.

5. The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to claim 1, characterized in that: The step of traversing the elements in the sorted via set and finding the nearest multiple vias using the spatial index tree's graphical nearest target query interface further includes: using the rtree::query(::nearest(viaBox,num), results) interface, passing in the number of nearest vias to be found through the parameter num, viaBox being the outer boundary rectangle of the element to be found in the via set, and results being used to save the found objects.

6. The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to claim 5, characterized in that: The parameter num=9.

7. The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to claim 1, characterized in that: The step of calculating the equivalent resistance of the virtual through-hole includes calculating the parallel resistance of all sub-through-holes combined into one virtual through-hole, and the equivalent resistance of the virtual through-hole is equal to the parallel resistance of all sub-through-holes.

8. The through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to claim 1, characterized in that: The trapezoidal processing step further includes: using a set of parallel lines to divide a polygon into multiple simple shapes: taking each vertex of the polygon as a starting point, extending a line parallel to the X-axis or Y-axis into the interior of the polygon, and connecting the other end of the extension line to the polygon to form a plurality of quadrilaterals or triangles with parallel upper and lower bases.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor is used to execute the computer program stored in the memory to implement the through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, which is loaded and executed by the processor to implement the through-hole fusion method for accelerating the extraction of parasitic resistance of EDA circuits according to any one of claims 1 to 8.

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