A manufacturing method for reducing the flash generated when V-CUT passes through PTH half hole

Abstract

The present invention discloses a manufacturing method for reducing the flash generated when a V-cut passes through a PTH half-hole, comprising the following steps: drilling a through hole intersecting a V-cut line on a production board, metalizing the hole by copper deposition and full-board electroplating to form a PTH hole; attaching a film to the production board, sequentially exposing and developing to form an outer circuit pattern, the outer circuit pattern including a hole ring pattern surrounding the PTH hole; and during exposure, the two end points corresponding to the V-cut line in the hole ring pattern are exposed, and after development, an outer layer coating area is formed at the two end points; pattern electroplating is performed on the production board; after film stripping, the PTH hole is subjected to a half-hole treatment to form a PTH half-hole; the production board is etched and then tin stripping is performed; a solder mask layer is formed on the production board, and then a V-cut is performed on the production board at the position corresponding to the V-cut line, and finally the production board is subjected to a forming process to obtain a circuit board. The method of the present invention can avoid the generation of copper spikes when the V-cut passes through the PTH half-hole, improve the quality of the V-cut passing PTH half-hole board product, and increase the product yield.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board manufacturing, and in particular to a manufacturing method for reducing flash generated when a V-CUT passes through a PTH half hole. Background Art

[0002] With the advancement of technology, circuit boards are increasingly being used in various industries. In the information age, the demand for circuit board upgrades and iterations is increasing, and the proportion of module interconnection usage is gradually increasing. To ensure the connectivity of each module, each circuit board is designed with a connection port. In the early years, product upgrades were mainly achieved by designing plug-in pins to connect other modules. As time goes by, consumers have increasingly sophisticated requirements for product size. Currently, most designs on the market use edge plating to achieve connectivity and reduce the space occupied by components. However, edge plating often leads to quality issues such as flash and incomplete hole walls. In particular, to improve board utilization and production efficiency, customers often design a panelization pattern with PTH half-holes and V-cut splitters on the edge of the board. This brings great production difficulties and quality control. The traditional production method of adding and removing flash holes cannot meet all product requirements, and other better production methods are needed to meet these needs.

[0003] Existing production method: When a V-CUT line needs to pass through a PTH half hole, positive and negative burr removal is used when the half hole diameter and the broken hole are greater than 1.0mm; when the half hole diameter is less than 1.0mm, it is produced according to the half hole first burr removal process, and a burr removal hole is added at the intersection of the two ends of the half hole before etching. The hole diameter is selected between 0.3-0.7mm, and the V-CUT edge is cut 0.05mm parallel to both ends.

[0004] Disadvantages of existing production technology: In order to ensure the quality requirements of the center line of the half-hole of the V-CUT through the edge of the board, the production process of adding the deburring hole and the positive and negative gong separately cannot achieve the effect of completely removing the flash. It is more likely to pull the copper wire during the positive and negative gong. In severe cases, the copper on the hole wall will be pulled out, leaving the PTH hole without copper, causing the product connection to be open and scrapped. Summary of the Invention

[0005] In response to the above-mentioned technical defects of the prior art, the present invention provides a manufacturing method for reducing the flash generated when the V-CUT passes through the PTH half hole, which can avoid the copper thorns generated when the V-CUT passes through the PTH half hole, improve the quality of the V-CUT through the PTH half hole board product, and increase the product yield.

[0006] In order to solve the above technical problems, the present invention provides a method for reducing the flash generated when the V-CUT passes through the PTH half hole, comprising the following steps:

[0007] S1. Drill a through hole that intersects the V-cut line on the production board, and then metalize the hole by copper deposition and full-board electroplating to form a PTH hole;

[0008] S2. Applying a film to the production board, and then sequentially performing exposure and development to form an outer circuit pattern, the outer circuit pattern including an annular ring pattern surrounding the PTH hole; and during exposure, the two end points of the annular ring pattern corresponding to the V-cut line are exposed, and after development, an outer film region is formed at the two end points, and the width of the outer film region is greater than or equal to the width of the V-cut line;

[0009] S3, performing pattern electroplating on the production board to sequentially plate a copper layer and a tin layer at the outer circuit pattern;

[0010] S4. After the film is removed, the PTH hole is subjected to a half-hole treatment to form a PTH half-hole, and the center line of the half-hole is coincident with the middle of the V-secant line;

[0011] S5. Etching the production board to remove the copper layer outside the outer circuit pattern and the copper layer in the outer coating area to form a concave copper-free area at both ends where the hole ring and the V-cut line intersect, and then tinning;

[0012] S6. A solder mask layer is made on the production board, and then a V-cut is performed at a position corresponding to a V-cut line on the production board. Finally, the production board is formed to obtain a circuit board.

[0013] Furthermore, in step S2, the distance between the two side edges of the outer coating area and the middle of the V-cut line is 12 mil.

[0014] Furthermore, in step S2, the vertical distance between the inner ring of the outer coating area and the inner ring of the hole ring pattern is ≥0.1 mm.

[0015] Furthermore, in step S2, the ring width of the hole ring pattern is ≥0.15 mm.

[0016] Furthermore, the production board is a double-sided copper-clad core board.

[0017] Furthermore, the production board is a multilayer board in which the inner layer board and the outer layer copper foil are pressed together by a semi-cured sheet. A hole ring is made around the position corresponding to the PTH hole in each inner layer circuit of the multilayer board, and a concave copper-free area is also formed at both ends where the hole ring of the inner layer intersects with the V-cut line.

[0018] Furthermore, the width of the copper-free area on each layer of the hole ring decreases by 4 mi from the outside to the inside.

[0019] Furthermore, the inner layer board is a double-sided copper clad core board or a four-layer board in which the inner layer core board and the copper foil are pressed together by a prepreg.

[0020] Furthermore, when the multilayer board is a six-layer board, the width of the copper-free area on the second outer hole ring is 4 mi l smaller than the width of the copper-free area on the outer hole ring, and the width of the copper-free area on the inner hole ring is 4 mi l smaller than the width of the copper-free area on the second outer hole ring.

[0021] Furthermore, when the multi-layer board is a four-layer board, the width of the copper-free area on the inner hole ring is 4 mi smaller than the width of the copper-free area on the outer hole ring.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] In the present invention, when making the hole ring of the PTH half hole, copper-free areas are first formed at the two end points where the hole ring and the V-cut line intersect, so as to reduce the contact with the copper layers at both ends of the hole ring during the V-cut, thereby reducing the situation of copper wire pulling at the edge of the hole ring during the V-cut, thereby avoiding the generation of copper thorns when the V-cut passes through the PTH half hole, improving the quality of the V-CUT through the PTH half hole board product, and improving the product yield.

[0024] Secondly, for multi-layer boards, corresponding copper-free zones are made on the annular rings of each inner layer circuit to avoid copper thorns generated at the annular rings of the inner and outer layers during V-cutting, improve the quality of V-CUT through PTH half-hole boards, and increase product yield; and in view of the characteristic of forming V-grooves during V-cutting, the width of the copper-free zone on each layer of annular ring decreases from the outside to the inside, that is, the opening during V-cutting is larger as it goes up, and the more copper will be cut. When the knife passes through, the copper will pull the copper wire, and the generated copper wire may scratch the board surface or pierce the dry film. If the copper wire is large, it will tear off the hole wall. Therefore, the width of the copper-free zone is set to the outer layer, so as to retain as much annular ring copper layer as possible while ensuring that no copper wire is generated at the annular ring of each layer, thereby improving the reliability of the electrical connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of annular rings formed on each circuit layer in an embodiment;

[0026] Figure 2 This is a schematic diagram of the gong after half hole in the embodiment;

[0027] Figure 3 It is a schematic diagram after V-cutting in the embodiment. DETAILED DESCRIPTION

[0028] In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further introduced and illustrated in conjunction with specific embodiments below.

[0029] Example 1

[0030] The present embodiment shows a method for manufacturing a circuit board, including a method for reducing the flash generated when the V-CUT passes through the PTH half hole, which includes the following processing steps in sequence:

[0031] (1) Cutting: Cut the core board according to the panel size of 520mm×620mm. The thickness of the core board is 0.5mm, and the thickness of the copper layer on both surfaces of the core board is 0.5oz. The position of the core board corresponding to the PTH hole to be made is the drilling position. The PTH hole intersects with the V-cut line produced later. The V-cut line is the tool path when performing V-cutting.

[0032] (2) Inner layer circuit production (negative process): Inner layer pattern transfer, use vertical coating machine to coat photosensitive film, the thickness of the photosensitive film is controlled at 8μm, use full automatic exposure machine, use 5-6 grid exposure ruler (21 grid exposure ruler) to complete the inner layer circuit exposure on the core board, after development, the inner layer circuit pattern is formed, the inner layer circuit pattern includes the inner layer hole ring pattern 1 (such as Figure 1 As shown in FIG5 , the two end points of the inner hole ring pattern corresponding to the V-cut line are not exposed during exposure, so that after development, exposed copper areas without film are formed at the two end points; inner layer etching, the exposed and developed core board is etched to form the inner layer circuit and the inner hole ring, and the copper layer at the exposed copper area is removed at the same time, so as to form a concave copper-free area 2 at both ends of the inner hole ring (as shown in FIG5 ). Figure 1 As shown), the inner layer line width is measured to be 3mil; inner layer AO I, and then the inner layer lines are checked for defects such as open and short circuits, line gaps, and line pinholes. Defective products are scrapped and non-defective products are sent to the next process.

[0033] In the above, the width of the inner hole ring is 0.15 mm.

[0034] Preferably, the vertical distance between the inner edge of the copper-free area and the inner ring of the inner layer annular ring is ≥0.1 mm, that is, the remaining ring width at the gap of the copper-free area at both ends of the annular ring is at least 0.1 mm.

[0035] In the above, the vertical distance between the two side edges of the copper-free area in the inner hole ring and the middle of the V-cut line is 8 mi l, that is, with the middle of the V-cut line as the reference, 8 mi l of copper is cut on both sides, so that the overall width of the copper-free area in the inner hole ring is 16 mi l.

[0036] (3) Lamination: The browning speed is based on the bottom copper thickness. The core board, prepreg, and outer copper foil are laminated in sequence as required. Then, appropriate lamination conditions are selected according to the Tg of the sheet material to laminate the laminate to form a four-layer inner layer board.

[0037] (4) Inner layer circuit production (negative film process): Inner layer pattern transfer, use a vertical coating machine to coat the photosensitive film, the film thickness of the photosensitive film is controlled to 8μm, and a fully automatic exposure machine is used to complete the exposure of the sub-outer layer circuit on the inner layer board with a 5-6 grid exposure ruler (21 grid exposure ruler). After development, the sub-outer layer circuit pattern is formed. The sub-outer layer circuit pattern includes a sub-outer layer hole ring pattern surrounding the drilling position. During exposure, the two end points corresponding to the V-cut line in the sub-outer layer hole ring pattern are not exposed, so that after development, a film-free copper exposed area is formed at the two end points; inner layer etching, the exposed and developed core board is etched to form the sub-outer layer circuit and the sub-outer layer hole ring, and the copper layer at the exposed copper area is removed at the same time to form a concave copper-free area at both ends of the sub-outer layer hole ring. The inner layer line width is measured to be 3mil; inner layer AO I, then check the open short circuit, line gap, line pinhole and other defects of the sub-outer layer circuit. Defective products are scrapped and the products without defects are sent to the next process.

[0038] In the above, the width of the secondary outer hole ring is 0.15 mm.

[0039] Preferably, the vertical distance between the inner edge of the copper-free area and the inner ring of the second outer hole ring is ≥0.1 mm, that is, the remaining ring width at the gap of the copper-free area at both ends of the hole ring is at least 0.1 mm.

[0040] In the above, the vertical distance between the two side edges of the copper-free area in the sub-outer hole ring and the middle of the V-cut line is 10 mi l, that is, with the middle of the V-cut line as the reference, 10 mi l of copper is cut to both sides, so that the overall width of the copper-free area in the sub-outer hole ring is 20 mi l; that is, the overall width of the sub-outer copper-free area is 4 mi l larger than the overall width of the inner copper-free area.

[0041] (5) Lamination: The browning speed is based on the bottom copper thickness. The inner layer board, prepreg, and outer copper foil are laminated in sequence as required. Then, appropriate lamination conditions are selected according to the Tg of the sheet material to laminate the laminated board to form a six-layer multilayer board.

[0042] (6) Drilling: Based on existing drilling technology, drilling is performed on the multilayer board according to design requirements to drill through holes at corresponding drilling positions.

[0043] (7) Copper plating: A thin layer of copper is deposited on the board surface and the hole wall using the chemical copper plating method. The backlight test is level 10, and the thickness of the copper plating in the hole is 0.5μm.

[0044] (8) Full board electroplating: The production board is electroplated according to the design requirements to thicken the hole copper and the board surface copper layer, metallize the through hole, and form a PTH hole.

[0045] (9) Making the outer layer circuit (positive film process): including the following steps:

[0046] a. Transfer of outer layer pattern: Using a fully automatic exposure machine and positive circuit film, the outer layer circuit exposure is completed with a 5-7 grid exposure ruler (21 grid exposure ruler). After development, the outer layer circuit pattern is formed on the multilayer board. The outer layer circuit pattern includes an annular pattern surrounding the PTH hole. During exposure, the two end points of the annular pattern corresponding to the V-sected line are exposed, so that the outer layer coating area is formed at the two end points after development.

[0047] b. Electroplating of the outer pattern, followed by copper and tin plating on the multilayer board. The electroplating parameters are set according to the required copper thickness. Copper plating is performed at a current density of 1.8ASD for 60 minutes on the entire board, while tin plating is performed at a current density of 1.2ASD for 10 minutes, with a tin thickness of 3-5μm. The outer layer coating area is protected by the coating, so pattern plating is not performed.

[0048] c. After the film is removed, the PTH hole is processed into a half-hole by using the gong set shape, that is, the general part of the PTH hole is removed to form a PTH half-hole 3 (such as Figure 2 The midline of the half-hole coincides with the middle of the V-secant line, that is, the V-secant line is located between the retained PTH half-hole and the removed half-hole;

[0049] d. Then, the outer layer of the production board is etched to remove the copper layer outside the outer layer circuit pattern, the outer layer circuit is etched out on the multilayer board, and the copper layer in the outer layer coating area is removed to form a concave copper-free area at both ends where the hole ring and the V-cut line intersect, and then the tin is withdrawn;

[0050] e. Outer layer AOI: Use the automatic optical inspection system to detect whether the outer layer circuit has defects such as open circuit, gap, incomplete etching, short circuit, etc. by comparing with the CAM data.

[0051] In the above, the width of the outer coating area is ≥ the width of the V-cut line, that is, the width of the copper-free area in the outer hole ring is ≥ the width of the V-cut line; in a specific embodiment, the width of the outer coating area is preferably greater than the width of the V-cut line to ensure that the tool will not touch the hole ring copper layer on both sides of the copper-free area during V-cutting.

[0052] In one embodiment, the distance between the two side edges of the outer coating area and the middle of the V-cut line is 12 mi l, that is, the overall width of the copper-free area after later etching is 24 mi l, which is 4 mi l larger than the overall width of the copper-free area in the sub-outer hole ring.

[0053] In the above, the width of the outer layer middle hole ring is 0.15mm.

[0054] Preferably, the vertical distance between the inner edge of the copper-free area and the inner ring of the outer hole ring is ≥0.1 mm, that is, the remaining ring width at the gap of the copper-free area at both ends of the hole ring is at least 0.1 mm.

[0055] (10) Solder mask and silk screen characters: After silk screen printing solder mask ink on the surface of the multilayer board, it is sequentially processed through pre-curing, exposure, development and heat curing to solidify the solder mask ink into a solder mask layer; specifically, the solder mask ink and the characters on the TOP surface are added with "UL mark", so that a layer is coated on the circuits and substrates that do not need to be soldered to prevent bridging between circuits during soldering, provide a permanent electrical environment and chemical corrosion resistance, and at the same time beautify the appearance.

[0056] (11) Surface treatment (nickel-gold deposition): The copper surface of the pad at the solder mask window position is chemically deposited with a nickel layer and a gold layer of a certain required thickness. The nickel layer thickness is 3-5μm; the gold layer thickness is 0.05-0.1μm.

[0057] (12) V-cut: V-cut is performed on the multilayer board at the position corresponding to the V-cut line to form a V-shaped groove 4 (such as Figure 3 As shown), it is convenient for the subsequent board separation operation.

[0058] (13) Electrical test: Test the electrical conductivity of the finished board. The test method used for this board is: flying probe test.

[0059] (14) Molding: According to the existing technology and the design requirements, the shape of the gong is made with an external tolerance of + / -0.05mm to produce a six-layer circuit board.

[0060] (15) FQC: Inspect the appearance of the circuit board according to the customer's acceptance standards and our inspection standards. If there are any defects, repair them in time to ensure that we provide customers with excellent quality control.

[0061] (16) FQA: Re-test the appearance, hole copper thickness, dielectric layer thickness, green oil thickness, inner layer copper thickness of the circuit board to see if they meet the customer's requirements.

[0062] (17) Packaging: According to the packaging method and packaging quantity required by the customer, the circuit board is sealed and packed, and desiccant and humidity card are placed before shipment.

[0063] Example 2

[0064] The manufacturing method of a circuit board shown in this embodiment is basically the same as that of Example 1, except that steps (4) and (5) are reduced, and the vertical distance between the two side edges of the copper-free area in the inner hole ring in step (2) and the middle of the V-cut line is adjusted to 10 mi l, that is, with the middle of the V-cut line as the reference, copper with a width of 10 mi l is cut on both sides, so that the overall width of the copper-free area in the inner hole ring is 20 mi l, and finally a four-layer circuit board is produced.

[0065] Example 3

[0066] The manufacturing method of a circuit board shown in this embodiment is basically the same as that of Example 1, except that steps (2) to (5) are reduced, and drilling and subsequent processes are performed directly on the core board to finally produce a double-layer circuit board.

[0067] The technical solutions provided by the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the embodiments of the present invention. The description of the above embodiments is only applicable to help understand the principles of the embodiments of the present invention. At the same time, for those skilled in the art, according to the embodiments of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A method for reducing the flash generated when a V-CUT passes through a PTH half hole, characterized in that: The following steps are involved: S1. Drill a through hole that intersects the V-cut line on the production board, and then metalize the hole by copper deposition and full-board electroplating to form a PTH hole; S2. Applying a film to the production board, and then sequentially performing exposure and development to form an outer circuit pattern, the outer circuit pattern including an annular ring pattern surrounding the PTH hole; and during exposure, the two end points of the annular ring pattern corresponding to the V-cut line are exposed, and after development, an outer film region is formed at the two end points, and the width of the outer film region is greater than or equal to the width of the V-cut line; S3, performing pattern electroplating on the production board to sequentially plate a copper layer and a tin layer at the outer circuit pattern; S4. After the film is removed, the PTH hole is subjected to a half-hole treatment to form a PTH half-hole, and the center line of the half-hole is coincident with the middle of the V-secant line; S5. Etching the production board to remove the copper layer outside the outer circuit pattern and the copper layer in the outer coating area to form a concave copper-free area at both ends where the hole ring and the V-cut line intersect, and then tinning; S6. Making a solder mask layer on the production board, then performing a V-cut on the production board at a position corresponding to the V-cut line, and finally performing a molding process on the production board to obtain a circuit board; Among them, the production board is a multi-layer board in which the inner layer board and the outer layer copper foil are pressed into one by a semi-cured sheet. A hole ring is made around the position corresponding to the PTH hole in each inner layer circuit of the multi-layer board, and a concave copper-free area is also formed at both ends where the hole ring of the inner layer intersects with the V-cut line. The width of the copper-free area on each layer of the hole ring decreases by 4 mil from the outside to the inside.

2. The method for reducing flash when a V-CUT passes through a PTH half hole according to claim 1, characterized in that: In step S2, the distance between the two side edges of the outer coating area and the middle of the V-cut line is 12 mil.

3. The method for reducing flash when a V-CUT passes through a PTH half hole according to claim 1, characterized in that: In step S2, the vertical distance between the inner ring of the outer coating area and the inner ring of the hole ring pattern is ≥0.1 mm.

4. The method for reducing flash when a V-CUT passes through a PTH half hole according to any one of claims 1 to 3, characterized in that: In step S2, the ring width of the hole ring pattern is ≥0.15 mm.

5. The method for reducing flash when a V-CUT passes through a PTH half hole according to claim 1, characterized in that: The inner layer board is a double-sided copper-clad core board or a four-layer board in which the inner layer core board and the copper foil are pressed together by a prepreg.

6. The method for reducing flash when a V-CUT passes through a PTH half hole according to claim 5, characterized in that: When the multilayer board is a six-layer board, the width of the copper-free area on the second outer hole ring is 4 mil smaller than that on the outer hole ring, and the width of the copper-free area on the inner hole ring is 4 mil smaller than that on the second outer hole ring.

7. The method for reducing flash when a V-CUT passes through a PTH half hole according to claim 5, characterized in that: When the multi-layer board is a four-layer board, the width of the copper-free area on the inner hole ring is 4 mil smaller than the width of the copper-free area on the outer hole ring.

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