Circuit board and battery management system

Abstract

The utility model discloses a circuit board and a battery management system. The circuit board comprises a solder mask layer; the conductive layer is arranged on one side of the solder mask layer; the semi-cured layer is arranged on one side, opposite to the solder mask layer, of the conductive layer; the copper core layer is arranged on the side, opposite to the conductive layer, of the semi-cured layer, and the copper core layer comprises a containing groove; and the at least one common mode inductor is arranged in the accommodating groove, the common mode inductor comprises a signal input end and a signal output end, and the signal input end and the signal output end extend out of the accommodating groove to be connected with the component. According to the utility model, the creepage distance between a high-voltage signal and a low-voltage signal on the circuit board can be reduced, so that the area of the circuit board is reduced.

Description

Technical Field

[0001] This utility model relates to the field of circuit board design, and in particular to a circuit board and battery management system. Background Technology

[0002] A PCB (Printed Circuit Board) is a board used to connect electronic components. It is typically composed of insulating materials (such as fiberglass) and conductive layers (such as copper).

[0003] In the design process of circuit boards, especially for high-voltage circuit boards, it is necessary to consider that the contamination level of the circuit board surface meets relevant requirements. Furthermore, the size of electrical clearances and creepage distances must be considered during circuit board design, as these factors affect electrical performance, safety, and reliability. Creepage distance refers to the shortest path length formed along the surface of insulating material between conductive components of different voltage levels, preventing arcing or breakdown in high-voltage environments and ensuring the safe operation of the circuit board. Electrical clearance refers to the shortest distance between two adjacent electrodes in an electrical device or circuit, preventing electrical breakdown caused by charge migration between electrical device or circuit components.

[0004] Normally, electrical clearance does not change with the increase of circuit board voltage. However, the creepage distance between high-voltage and low-voltage signals increases with the increase of voltage. Therefore, in high-voltage circuit boards, there is a problem that the area of ​​the circuit board is too large due to the increase of creepage distance, and it will result in poor universality of the circuit board. For example, a 400V circuit board cannot be used in an 800V working environment, and different circuit boards need to be developed for 400V and 800V working environments respectively. Utility Model Content

[0005] The purpose of this invention is to solve the problem of excessively large circuit board area caused by large creepage distances in existing technologies. This invention provides a circuit board that reduces the creepage distance between high-voltage and low-voltage signals, thereby reducing the circuit board area.

[0006] To address the aforementioned technical problems, this utility model discloses a circuit board, comprising:

[0007] The solder mask layer includes multiple soldering positions for soldering components.

[0008] A conductive layer is disposed on one side of the solder resist layer;

[0009] A semi-cured layer is disposed on the side of the conductive layer opposite to the solder resist layer;

[0010] A copper core layer is disposed on the side of the semi-cured layer opposite to the conductive layer, and the copper core layer includes a receiving groove.

[0011] At least one common-mode inductor is disposed in the receiving slot. The common-mode inductor includes a signal input terminal and a signal output terminal, which extend out of the receiving slot and are connected to the component.

[0012] By employing the above technical solution, without adding any extra structure, a receiving groove is set in the copper core layer of the circuit board, and the common-mode inductor is placed within the receiving groove. Firstly, compared to placing the common-mode inductor on the surface layer of the circuit board (e.g., solder mask), which requires consideration of creepage distances between the signal input and output terminals of the common-mode inductor, as well as between the common-mode inductor and other conductive components, the above technical solution eliminates the need to consider creepage distances between the signal input and output terminals, and between the common-mode inductor and other conductive components. Therefore, the PCB area can be reduced, and since the creepage distance between the signal input and output terminals does not need to be considered, even with increased voltage, the circuit board does not need to be redesigned, improving the PCB's versatility. Secondly, embedding the common-mode inductor within the copper core layer also conceals the signal radiation of the common-mode inductor within the copper core layer, preventing it from affecting other components on the circuit board.

[0013] According to another specific embodiment of the present invention, a circuit board is disclosed, wherein the components include at least one signal source and at least one load, a common-mode inductor is connected in series between each signal source and each load, the signal input terminal is connected to the signal source, and the signal output terminal is connected to the load.

[0014] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a circuit board, the circuit board including a conformal coating layer, the conformal coating layer being used to cover the solder resist layer and the components, wherein the common mode inductor is not located at the soldering position.

[0015] By adopting the above technical solution, since the common-mode inductor is located in the receiving slot of the copper core layer and not at the soldering position, the contamination level of the common-mode inductor is only level 1 even without conformal coating. Furthermore, because the common-mode inductor is built into the copper core layer, there is no issue of some components not being able to be coated with conformal coating due to component layout design or limitations of spraying equipment. Coating all components on the circuit board with conformal coating reduces the circuit board's contamination level (e.g., from level 2 to level 1), thereby reducing the creepage distance between components and further reducing the circuit board area.

[0016] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a circuit board, wherein the common mode inductor includes a first coil, a second coil and a nanocrystalline iron core, and the first coil and the second coil are connected in parallel between the signal source and the load;

[0017] The nanocrystalline iron core includes an upper part and a lower part, with the first coil wound on the upper part and the second coil wound on the lower part, the first coil and the second coil being wound in the same direction.

[0018] Using the above technical solution, a common-mode inductor is formed by winding a first coil and a second coil on a nanocrystalline iron core. Based on the excellent comprehensive magnetic properties and small volume of nanocrystalline materials, the common-mode inductor made of nanocrystalline iron core is embedded in the receiving slot without increasing the thickness of the circuit board, and has excellent ability to suppress common-mode signals.

[0019] According to another specific embodiment of the present invention, a circuit board is disclosed, wherein the first coil includes a first signal output terminal and a first signal input terminal, the second coil includes a second signal output terminal and a second signal input terminal, the first signal input terminal and the second signal input terminal together form the signal input terminal, and the first signal output terminal and the second signal output terminal together form the signal output terminal.

[0020] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a circuit board, wherein the conductive layer includes a copper foil layer.

[0021] According to another specific embodiment of the present invention, an embodiment of the present invention discloses a circuit board, wherein the semi-cured layer includes a resin layer.

[0022] The present invention also discloses a battery management system, which includes at least the circuit board described in any of the above embodiments. Attached Figure Description

[0023] Figure 1 A schematic diagram of the stacked layers of a circuit board provided in an embodiment of this application is shown.

[0024] Figure 2 A schematic diagram of the common-mode inductor of the circuit board provided in an embodiment of this application is shown.

[0025] Figure 3 A simplified schematic diagram of the common-mode inductor of the circuit board provided in an embodiment of this application is shown.

[0026] Figure 4 A simplified circuit diagram of the common-mode inductor of the circuit board provided in an embodiment of this application is shown.

[0027] Figure 5 This diagram illustrates the connection between the common-mode inductor and components of the circuit board provided in an embodiment of this application. Detailed Implementation

[0028] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. Although the description of this utility model will be presented in conjunction with preferred embodiments, this does not mean that the features of this utility model are limited to this embodiment. On the contrary, the purpose of describing the utility model in conjunction with the embodiments is to cover other options or modifications that may be derived based on the claims of this utility model. To provide a deep understanding of this utility model, many specific details will be included in the following description. This utility model may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of this utility model, some specific details will be omitted in the description. It should be noted that, without conflict, the embodiments and features in the embodiments of this utility model can be combined with each other.

[0029] It should be noted that in this specification, similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0030] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the utility model product is usually placed in during use. They are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the utility model.

[0031] The terms “first”, “second”, etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0032] In the description of this embodiment, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this embodiment based on the specific circumstances.

[0033] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in further detail below with reference to the accompanying drawings.

[0034] In the prior art, referring to the description of pollution levels in IEC 60664-1 or GB / T 16935.1-2008 standards, pollution levels are used to determine the microscopic environment of electrical clearances or creepage distances, and are divided into four levels:

[0035] Level 1 contamination: No contamination or only dry, non-conductive contamination. The contamination has no impact.

[0036] Level 2 contamination: Aside from short-term, incidental contamination caused by foreseeable condensation, only non-conductive contamination occurs;

[0037] Level 3 contamination: Applicable to localized internal environments within equipment that are subject to conductive contamination or dry non-conductive contamination that may become conductive due to anticipated water vapor condensation, or to equipment located in an area where the external environment is subject to conductive contamination or may become conductive dry non-conductive contamination.

[0038] Level 4 pollution: Pollution that produces persistent conductivity, caused by conductive dust, rainwater, or snowflakes.

[0039] In circuit board design, especially for high-voltage circuit boards such as those used in BMS (Battery Management System) circuit boards, the higher the contamination level of the circuit board surface, the greater the creepage distance needs to be to ensure the safety and reliability of the circuit board. For example, if components are placed on the surface of the circuit board, with a contamination level of 2, the distance between a 400V high-voltage signal and a low-voltage signal is 2.5mm, and the distance between an 800V high-voltage signal and a low-voltage signal is 4mm; with a contamination level of 1, the distance between the 400V high-voltage signal and the low-voltage signal is 2.3mm, and the distance between the 800V high-voltage signal and the low-voltage signal is 2.4mm. Therefore, with a contamination level of 2, the distance between the high-voltage and low-voltage signals on the circuit board is greater than that with a contamination level of 1, and this distance increases with increasing voltage, thus requiring a larger circuit board area.

[0040] Based on this, see Figure 1 , Figure 2 , Figure 3This application provides a circuit board including a solder resist layer 10, a conductive layer 20, a prepreg layer 30, a copper core layer 40, and at least one common-mode inductor 50. The circuit board has a stacked structure. Along the stacking direction X of the circuit board, the conductive layer 20 is disposed on one side of the solder resist layer 10, the prepreg layer 30 is disposed on the side of the conductive layer 20 facing away from the solder resist layer 10, and the copper core layer 40 is disposed on the side of the prepreg layer 30 facing away from the conductive layer 20.

[0041] For example, the semi-cured layer 30 includes an upper semi-cured layer 301 and a lower semi-cured layer 302, which are disposed on both sides of the copper core layer 40 along the stacking direction. The conductive layer 20 includes an upper conductive layer 201 and a lower conductive layer 202. Along the stacking direction X, the upper conductive layer 201 is disposed on the side of the upper semi-cured layer 301 facing away from the copper core layer 40 and is located between the upper conductive layer 201 and the copper core layer 40. The lower conductive layer 202 is disposed on the side of the lower semi-cured layer 302 facing away from the copper core layer 40 and is located between the lower conductive layer 202 and the copper core layer 40.

[0042] The solder resist layer 10 includes an upper solder resist layer 101 and a lower solder resist layer 102. Along the stacking direction X, the upper solder resist layer 101 is disposed on the side of the upper conductive layer 201 opposite to the upper semi-cured layer 301, and the upper conductive layer 201 is disposed between the upper semi-cured layer 301 and the upper solder resist layer 101. The lower solder resist layer 102 is disposed on the side of the lower conductive layer 202 opposite to the lower semi-cured layer 302, and the lower conductive layer 202 is disposed between the lower semi-cured layer 302 and the lower solder resist layer 102. The aforementioned upper semi-cured layer 301 and lower semi-cured layer 302, upper conductive layer 201 and lower conductive layer 202, and upper solder resist layer 101 and lower solder resist layer 102 are symmetrically disposed on both sides of the copper core layer 40.

[0043] In some embodiments, see Figure 1 , Figure 2 , Figure 4 and combined Figure 3 The copper core layer 40 includes a receiving groove 401, and a common-mode inductor 50 is disposed in the receiving groove 401 to suppress common-mode signals of the circuit board. The common-mode inductor 50 includes a signal input terminal 501 and a signal output terminal 502, both of which extend out of the receiving groove 401 and connect to components. This embodiment does not limit the connection method between the signal input terminal 501, the signal output terminal 502 and the components; for example, they can be connected by wiring on the conductive layer 20.

[0044] For example, see Figure 2 , Figure 3 , Figure 5The circuit board layers are interconnected via electroplated vias. For example, in the circuit board provided in this embodiment, at least two first electroplated vias 61 are provided between the solder mask layer 10 and the conductive layer 20, and a second electroplated via 62 is provided between the conductive layer 20 and the copper core layer 40. Components (e.g., signal sources and loads) are connected to the conductive layer 20 through the first electroplated vias 61, and signal input terminals 501 and 502 are connected to the conductive layer 20 through the second electroplated vias 62. Connection circuits are arranged on the conductive layer 20 to achieve the connection between the signal input terminals 501 and 502 and the components. It is understood that the electroplated vias can be through-holes, buried vias, or micro-vias.

[0045] Furthermore, the common-mode inductor provided in this application embodiment can be applied to circuit boards with different numbers of layers, and this application embodiment does not limit this.

[0046] For example, in the manufacturing process of the circuit board provided in this application embodiment, the common mode inductor 50 can be embedded in the receiving groove 401 first, and then the solder mask layer 10, conductive layer 20, prepreg layer 30, and copper core layer 40 can be pressed together. In some embodiments, the receiving groove 401 is located inside the copper core layer 40 at a position 2.5mm away from the edge of the circuit board. It can be understood that since the common mode inductor 50 is embedded inside the copper core layer 40, this application embodiment does not limit the position of the common mode inductor 50 inside the copper core layer 40, that is, this application embodiment does not limit the position of the receiving groove 401. For example, it can be opened at a position of 1mm, 2mm, 3mm, 4.1mm away from the edge of the circuit board.

[0047] By adopting the above technical solution, without adding any additional structure, a receiving groove 401 is provided in the copper core layer 40 of the circuit board, and the common-mode inductor is placed in the receiving groove 401. On the one hand, compared with the case where the common-mode inductor 50 is placed on the surface layer of the circuit board (e.g., solder mask layer 10), it is necessary to consider the creepage distance between the first signal input terminal 501 and the second signal input terminal 502 of the common-mode inductor 50, as well as the creepage distance between the common-mode inductor 50 and other conductive components. However, the above technical solution, by placing the common-mode inductor in the receiving groove 401, eliminates the need to consider the creepage distance between the first signal input terminal 501 and the second signal input terminal 502 of the common-mode inductor 50, and also eliminates the need to consider the creepage distance between the common-mode inductor 50 and other conductive components. Therefore, the area of ​​the PCB board can be reduced. Furthermore, since the creepage distance between the first signal input terminal 501 and the second signal input terminal 502 does not need to be considered, even if the voltage increases, the circuit board does not need to be redesigned, thus improving the versatility of the circuit board. On the other hand, the common-mode inductor is built into the copper core layer 40, which also allows the signal radiation of the common-mode inductor 50 to be contained within the copper core layer 40, thus avoiding interference with other components on the circuit board.

[0048] In some embodiments, see Figure 2 , Figure 3 , Figure 4 The circuit board includes at least one signal source and at least one load. A common-mode inductor 50 is connected in series between each signal source and each load. The signal input terminal 501 is connected to the signal source, and the signal output terminal 502 is connected to the load. This embodiment does not limit the number of common-mode inductors 50; the specific number can be determined based on the number of differential signals. For example, if the circuit board includes two signal sources and two loads, it has two pairs of differential signals, and two common-mode inductors 50 are correspondingly provided.

[0049] For example, the common-mode inductor 50 includes a first coil 51, a second coil 52, and a nanocrystalline iron core 53. The first coil 51 is connected in series between the signal source and the load, and the second coil 52 is connected in series between the signal source and the load, that is, the first coil 51 and the second coil 52 are connected in parallel between the signal source and the load. The nanocrystalline iron core 53 includes an upper part 531 and a lower part 532. The first coil 51 is wound on the upper part 531, and the second coil 52 is wound on the lower part 532. The winding directions of the first coil 51 and the second coil 52 are the same.

[0050] Understandably, the winding direction of the first coil 51 and the second coil 52 in the embodiments of this application is the same, which means that the direction of the magnetic field lines is the same. Specifically, according to Ampere's law, if you hold the wire with your right hand and the direction pointed to by your outstretched thumb is the same as the direction of the current, the direction pointed to by your bent four fingers is the direction of the magnetic field lines.

[0051] In some embodiments, see Figure 2 , Figure 3 , Figure 4 The first coil 51 includes a first signal input terminal 511 and a first signal output terminal 512. The second coil 52 includes a second signal input terminal 521 and a second signal output terminal 522. Both the first signal input terminal 511 and the second signal input terminal 521 are connected to a signal source. The first signal input terminal 511 and the second signal input terminal 521 together form a signal input terminal 501. Both the first signal output terminal 512 and the second signal output terminal 522 are connected to a load. The first signal output terminal 512 and the second signal output terminal 522 together form a signal output terminal 502.

[0052] The common-mode inductor 50 provided in this embodiment is a common-mode interference suppression device with a nanocrystalline iron core 53 as its magnetic core. It consists of two coils of the same size and number of turns symmetrically wound on the same nanocrystalline iron core 53. When common-mode current flows through the first signal input terminal 511 and the second signal input terminal 521, the magnetic fluxes in the first coil 51 and the second coil 52 are superimposed, resulting in a considerable inductance, which suppresses the common-mode current. However, when differential-mode current flows through the first coil 51 and the second coil 52, the magnetic fluxes in the magnetic core cancel each other out, resulting in almost no inductance. Therefore, the differential-mode current can pass through without attenuation.

[0053] In some embodiments, see Figure 1 The circuit board includes a conformal coating layer (not shown in the figure), which is used to cover the solder mask layer 10 and the components. Exemplarily, the conformal coating layer provided in this application embodiment includes, but is not limited to, solvent-containing acrylic resin conformal coating, solvent-free acrylic resin conformal coating, polyurethane conformal coating, silicone conformal coating, etc., which can be used to prevent components from getting damp, vibrated, and corroded.

[0054] By adopting the above technical solution, since the common-mode inductor 50 is located in the receiving groove 401 of the copper core layer 40 and is not located at the soldering position, the contamination level of the common-mode inductor 50 is only level 1 even without conformal coating. Furthermore, since the common-mode inductor 50 is built into the copper core layer 40, there is no issue of some components not being able to be coated with conformal coating due to component layout design or limitations of spraying equipment. After all components on the circuit board are coated with conformal coating, the contamination level of the circuit board can be reduced (e.g., from level 2 to level 1), thereby reducing the creepage distance between components and further reducing the area of ​​the circuit board.

[0055] In some embodiments, see Figure 1 The conductive layer 20 includes a copper foil layer. The copper foil layer is also known as copper foil. Commonly used copper foil materials for circuit boards include rolled copper foil and electrolytic copper foil. Rolled copper foil has a denser molecular structure, a smoother surface, better folding resistance and flexibility, and is less prone to breakage.

[0056] In some embodiments, see Figure 1 The prepreg layer 30 includes a resin layer. Prepreg layer 30 (PP, Prepreg), also known as prepreg material, is mainly used as an adhesive and insulating material for the inner conductive patterns of multilayer printed circuit boards. After the prepreg is laminated, the semi-cured epoxy resin is extruded, begins to flow and solidify, bonding the multilayer circuit boards together and forming a reliable insulating layer.

[0057] This application also provides a battery management system, including the circuit board in any of the foregoing embodiments.

[0058] Although the present invention has been illustrated and described with reference to certain preferred embodiments, those skilled in the art should understand that the above description is a further detailed explanation of the present invention in conjunction with specific embodiments, and should not be construed as limiting the specific implementation of the present invention to these descriptions. Those skilled in the art can make various changes in form and detail, including some simple deductions or substitutions, without departing from the spirit and scope of the present invention.

Claims

1. A circuit board, characterized in that, include: The solder mask layer includes multiple soldering positions for soldering components; A conductive layer, wherein the conductive layer is disposed on one side of the solder resist layer; A semi-cured layer is disposed on the side of the conductive layer opposite to the solder resist layer; A copper core layer is disposed on the side of the semi-cured layer opposite to the conductive layer, and the copper core layer includes a receiving groove. At least one common-mode inductor is disposed in the receiving slot. The common-mode inductor includes a signal input terminal and a signal output terminal, which extend out of the receiving slot and are connected to the component.

2. The circuit board as described in claim 1, characterized in that, The component includes at least one signal source and at least one load, with a common-mode inductor connected in series between each signal source and each load, the signal input terminal being connected to the signal source, and the signal output terminal being connected to the load.

3. The circuit board as described in claim 1, characterized in that, The circuit board includes a conformal coating layer, which is used to cover the solder mask layer and the components. The common mode inductor is not located at the soldering position.

4. The circuit board as described in claim 2, characterized in that, The common-mode inductor includes a first coil, a second coil, and a nanocrystalline iron core, with the first coil and the second coil connected in parallel between the signal source and the load; The nanocrystalline iron core includes an upper part and a lower part, with the first coil wound on the upper part and the second coil wound on the lower part, the first coil and the second coil being wound in the same direction.

5. The circuit board as described in claim 4, characterized in that, The first coil includes a first signal output terminal and a first signal input terminal, the second coil includes a second signal output terminal and a second signal input terminal, the first signal input terminal and the second signal input terminal together form the signal input terminal, and the first signal output terminal and the second signal output terminal together form the signal output terminal.

6. The circuit board according to any one of claims 1-5, characterized in that, The conductive layer includes a copper foil layer.

7. The circuit board as described in any one of claims 1-5, characterized in that, The semi-cured layer includes a resin layer.

8. A battery management system, characterized in that, Includes the circuit board as described in any one of claims 1-7.

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