A method and system for fetching branch instructions in a very long instruction word architecture

Abstract

The present application discloses a method and system for fetching instructions for branch instructions of a very long instruction word architecture, wherein the method includes: setting an instruction fetch buffer between an instruction cache and an instruction pipeline; setting an instruction packet counter at a hit check station, used to fetch instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; storing the instruction packet counter value and the instruction word together in the instruction fetch buffer; setting a branch delay slot distance counter at an instruction execution station, used to count the current branch delay slot length; after a branch jump request is generated, the instruction execution station sends the branch delay slot length to the instruction analysis station for branch delay slot sending judgment. Through the present application, it is ensured that when a branch jump is made, it is judged in advance whether the instructions in the branch delay slot have been obtained, and then it is possible to quickly jump to the branch target to fetch instructions, reduce the overhead of waiting for the branch delay slot, reduce the number of useless instructions, improve core performance, and save power consumption.

Description

Technical Field

[0001] The present application relates to the field of computer instruction architecture, and in particular, to a method and system for fast jumping of a very long instruction word architecture. Background Art

[0002] A digital signal processor (DSP) is a microprocessor chip that targets digital signal processing algorithms and is widely used in audio signal processing, telecommunications, digital image processing, radar, sonar, and speech recognition systems, as well as everyday consumer electronic devices such as mobile phones, disk drives, and high-definition television (HDTV) products. The goal of a DSP chip is usually to measure, filter, or compress continuous signals, which are computationally intensive and relatively regular, so DSP chips often use a dedicated core architecture that can support multiple instructions in parallel.

[0003] High-performance DSP cores usually use a very long instruction word architecture, where one instruction word contains multiple parallel instructions. The compiler analyzes and organizes the source program, and packages the parallel instructions into a fixed-length instruction word, but sometimes it cannot find enough parallel instructions, so the instruction word may not be full. In order to increase the instruction density of executable code and reduce instruction word holes, the compiler usually adds a parallel bit to each instruction to indicate whether it can be parallel with the previous instruction, so that both parallel and non-parallel instructions are placed in the same instruction word, that is, one instruction word may contain multiple parallel instruction packages, thereby improving the density of effective instructions in the instruction word. In addition, in order to improve the efficiency of program execution, the compiler will also place instructions that have no dependency on branch instructions in the branch delay slot. The instructions in the branch delay slot will be executed regardless of whether the branch jumps or not, so the pipeline pause caused by waiting for the branch calculation to be completed can be minimized.

[0004] Depending on the characteristics of the program, sometimes it may not be possible to find enough instructions to fill the branch delay slot (assuming that the length of the branch delay slot is 5, the maximum number of parallel instructions in the instruction word is 8, and it takes 40 instructions to fill the branch delay slot. If there are not enough instructions, even Nop is needed to occupy the place). Therefore, when the branch jumps, the instruction pipeline may have already obtained all the instructions in the branch delay slot, and sometimes even some useless instructions outside the branch delay slot may be taken. At this time, there is no need to wait until the instructions in the branch delay slot are dispatched, that is, you can directly jump to the branch target to fetch instructions, and clear the extra instructions outside the branch delay slot.

[0005] Ideally, for branch instructions in high-performance DSP cores, it is necessary to ensure that instructions in the branch delay slot are accurately executed, that is, no instructions are missed and no extra instructions outside the branch delay slot are sent to the back end of the instruction pipeline. In addition, it is necessary to quickly jump to the corresponding target address to fetch instructions for execution. While ensuring correctness, redundant instruction fetching at non-branch targets outside the delay slot can be reduced to improve the core instruction fetching efficiency. Summary of the invention

[0006] In order to solve the above technical problems, the present application provides a method and system for branch instruction jump fetching in a very long instruction word architecture. By judging in advance whether all instructions in the branch delay slot have been obtained when the branch jumps, it can quickly jump to the branch target to fetch instructions, reduce the overhead of waiting for the branch delay slot, reduce the number of useless instructions obtained, and achieve instruction fetching and execution from the branch target as quickly as possible when encountering a branch jump.

[0007] Specifically, the technical solution of this application is as follows:

[0008] In a first aspect, the present application discloses a method for fetching branch instructions of a very long instruction word architecture, comprising:

[0009] Performing instruction fetch address arbitration on the instruction through the address arbitration station to obtain the arbitration address of the instruction;

[0010] receiving the arbitration address and accessing the instruction cache via a cache access station;

[0011] Checking whether the instruction fetch hits the instruction cache through a hit check station, and judging whether the instruction analysis station can receive the instruction; setting an instruction packet counter and a cross flag at the hit check station; the instruction packet counter is used to obtain instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; the cross flag is used to judge whether the last parallel instruction packet crosses the instruction word;

[0012] When it is detected that the instruction fetch hits the instruction cache, the instruction word, the instruction packet counter value and the cross flag are written into the instruction fetch buffer;

[0013] The obtained instructions are cached by the instruction analysis station, and the obtained instructions are analyzed in parallel bits, and the instruction words are decomposed into parallel instruction packets and sent to the subsequent stations; N instruction fetch buffer entries are set by the instruction analysis station, and the instruction fetch buffer is implemented as a circular buffer; the instruction fetch buffer is respectively set with an allocation pointer and an instruction fetch pointer, the allocation pointer is used to write the fetched instruction word, the instruction packet counter value and the cross flag into the instruction fetch buffer entry to be currently allocated, and the instruction fetch pointer is used to select the parallel instruction packet to be sent to the next pipeline station; a branch delay slot counter is set at the instruction analysis station, and the branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot;

[0014] By setting a branch delay slot distance counter on the instruction execution station, the branch delay slot distance counter is used to count the current branch delay slot length; after a branch jump request is generated, the instruction execution station sends the branch delay slot length to the instruction analysis station for branch delay slot sending judgment.

[0015] In some implementations, the method for fetching branch instructions in a very long instruction word architecture further includes the steps of:

[0016] Dispatching the instructions in the parallel instruction package to a decoding station corresponding to a specific execution component through an instruction dispatching station;

[0017] Decoding the instruction by an instruction decoding station;

[0018] The instruction is executed by the instruction execution station to obtain a target address for branch jump, and the target address is fed back to the address arbitration station to participate in the instruction fetch address arbitration.

[0019] In some implementations, the instruction fetch buffer sets the allocation pointer to indicate the instruction fetch buffer entry into which the currently fetched instruction word is to be written;

[0020] Whenever an instruction hits the instruction cache and the instruction fetch buffer can receive it, the instruction word, the instruction packet counter value and the cross flag are written into the entry pointed to by the allocation pointer. When the entry pointed to by the allocation pointer is valid, the allocation pointer must coincide with the instruction fetch pointer, indicating that the instruction fetch buffer is full and cannot receive the newly written instruction;

[0021] Each time a new instruction word is written, the allocation pointer moves to the next entry in sequence.

[0022] In some implementations, the instruction fetch buffer sets the instruction fetch pointer to indicate the instruction fetch buffer entry to which the parallel instruction packet is currently to be sent;

[0023] Whenever a parallel instruction packet is sent to the next pipeline station, the corresponding instruction valid bit is cleared to 0. If the span flag of the instruction fetch buffer entry pointed to by the instruction fetch pointer is valid, it means that the current parallel instruction packet spans the instruction word. Then, when sending the last parallel instruction packet, it must be sent to the next station together with the parallel instruction packet starting with the next instruction word. If the next instruction word has not been obtained, it is necessary to wait. When there is no valid instruction in the entry pointed to by the instruction fetch pointer, it means that the instruction fetch buffer is empty and no instruction needs to be sent to the next pipeline station.

[0024] After all instructions in the currently pointed instruction fetch buffer entry have been sent, the instruction fetch pointer is moved to the next entry in sequence.

[0025] In some implementations, the method for fetching branch instructions in a very long instruction word architecture further includes the steps of:

[0026] When the instruction analysis station receives the branch jump request sent by the instruction execution station, comparing the value of the branch delay slot counter of the instruction analysis station with the value of the branch delay slot distance counter;

[0027] If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter, respond to the branch jump request, fetch instructions from the branch target address for execution, and clear the extra instructions fetched outside the branch delay slot;

[0028] If the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, the branch jump request will not be responded to, and the branch jump request, the branch target address and the length of the branch delay slot will be loaded into the instruction fetch request queue, and the current branch delay slot counter value will be saved; wait for all the parallel instruction packets in the current branch delay slot to be obtained, and then fetch instructions from the branch target address for execution.

[0029] In some implementations, the method for fetching branch instructions in a very long instruction word architecture further includes the steps of:

[0030] When the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, in the process of waiting for the parallel instruction packet in the current branch delay slot to be sent, each time a new instruction word is received, the number of parallel instruction packets thereof is accumulated to the saved branch delay slot counter;

[0031] If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter at the head of the instruction fetch request queue, the branch target address is taken out of the instruction fetch request queue and instructions are fetched from the branch target address for execution, while the extra instructions outside the branch delay slot are cleared.

[0032] In some implementations, the method for fetching branch instructions in a very long instruction word architecture further includes the steps of:

[0033] When the hit check station detects that the instruction fetch does not hit the instruction cache, or the instruction analysis station cannot receive the instruction, the hit check station generates a re-instruction fetch request and feeds it back to the address arbitration station, while clearing the instruction fetch request being processed by the cache access station.

[0034] In some embodiments, the instruction fetch address sources of the address arbitration station include: sequential instruction fetch addresses; re-fetch addresses of the hit check station; branch target instruction fetch addresses of the instruction execution station and exception / interrupt addresses.

[0035] In some implementations, the value of the branch delay slot counter when a branch jump request is received is calculated using the following formula:

[0036]

[0037] in, is the sum of the count values ​​of the instruction packet counters in the N instruction fetch buffers; ΣValid(stage j ) is the number of stations where instructions are valid between the analysis and sorting station and the instruction execution station. A valid station indicates that a parallel instruction package has been cached.

[0038] In a second aspect, the present application also discloses a branch instruction jump fetching system of a very long instruction word architecture, comprising:

[0039] An address arbitration station, used for performing instruction fetch address arbitration on the instruction to obtain the arbitration address of the instruction;

[0040] Accessed via cache, for the station to receive the arbitration address and access the instruction cache;

[0041] A hit check station is used to check whether the instruction fetch hits the instruction cache and determine whether the instruction analysis station can receive the instruction; the hit check station is also used to set an instruction packet counter and a cross flag; the instruction packet counter is used to obtain instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; the cross flag is used to determine whether the last parallel instruction packet crosses the instruction word;

[0042] The hit check station is further used to write the instruction word, the instruction packet counter value and the cross flag into the instruction fetch buffer when it is checked that the instruction fetch hits the instruction cache;

[0043] The instruction analysis station is used to cache the instructions that have been obtained, and perform parallel bit analysis on the obtained instructions, decompose the instruction words into parallel instruction packets and send them to subsequent stations; the instruction analysis station is also used to set N instruction fetch buffer entries and an allocation pointer and an instruction fetch pointer, and the allocation pointer and the instruction fetch pointer cooperate to manage the instruction fetch buffer; the instruction analysis station is also used to set a branch delay slot counter, and the branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot;

[0044] The instruction execution station is used to set a branch delay slot distance counter, and the branch delay slot distance counter is used to count the current branch delay slot length; after generating a branch jump request, the instruction execution station is also used to send the branch delay slot length to the instruction analysis station for branch delay slot sending judgment.

[0045] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0046] The present application sets an instruction fetch buffer between the instruction cache and the instruction pipeline, sets an instruction packet counter at the hit check station, which is used to obtain instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; stores the number of parallel instruction packets and instruction words together in the instruction fetch buffer; sets a branch delay slot distance counter at the instruction execution station to count the current branch delay slot length; after a branch jump request is generated, the instruction execution station sends the branch delay slot length to the instruction analysis station for instruction fetch judgment. This ensures that when a branch jump is made, it is possible to determine in advance whether all instructions in the branch delay slot have been obtained, and then quickly jump to the branch target to fetch instructions, reduce the overhead of waiting for the branch delay slot, reduce the number of useless instructions, improve core performance, and save power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0048] Figure 1 A flow chart of branch delay slot instruction fetching in the prior art provided by this application;

[0049] Figure 2 An analysis diagram of branch fetching in the prior art provided by this application;

[0050] Figure 3 This is the overall structure of the front-end instruction pipeline in a method embodiment of the present application. DETAILED DESCRIPTION

[0051] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0052] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0053] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0054] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0055] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0056] In a specific implementation, the terminal device described in the embodiments of the present application includes, but is not limited to, other portable devices such as mobile phones, laptop computers, tutoring machines, or tablet computers with touch-sensitive surfaces (e.g., touch screen displays and / or touch pads). It should also be understood that in some embodiments, the terminal device is not a portable communication device, but a desktop computer with a touch-sensitive surface (e.g., touch screen displays and / or touch pads).

[0057] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0058] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0059] The VLIW core has several pipeline stations from instruction fetch to execution. A typical VLIW architecture instruction pipeline is as follows: Figure 1 Specifically, the instruction pipeline includes the following pipeline stations:

[0060] The address arbitration (ARB) station is used to perform instruction fetch address arbitration. The instruction fetch address sources include: 1. Sequential instruction fetch address. 2. Hit check (CHECK) station re-fetch address, that is, due to miss or unacceptable analysis and sorting (PACK) station. 3. Instruction execution (EXE) station branch target instruction fetch address and exception / interrupt address.

[0061] The ICA station is used to receive the address arbitrated by the ARB station and access the instruction cache.

[0062] The hit check (CHECK) station is used to check whether the instruction fetch hits the instruction cache and whether the analysis and arrangement (PACK) station can receive the instruction. If one condition is not met, a re-instruction fetch request is generated and fed back to the address arbitration (ARB) station, and the instruction fetch request being processed by the cache access (ICA) station is cleared.

[0063] The analysis and sorting (PACK) station is used to cache instructions, perform parallel bit analysis on the obtained instruction words, and complete the splitting and merging of parallel instruction packets.

[0064] The instruction dispatch (DISP) station is used to complete the dispatch of instructions in the parallel instruction package to specific execution components.

[0065] The instruction decoding (DEC) station is used to perform instruction decoding.

[0066] The instruction execution (EXE) station is used to start executing instructions and obtain the branch jump target address, which is fed back to the address arbitration (ARB) station to participate in instruction fetch arbitration.

[0067] For branch instructions, the target address of the jump cannot be known until the instruction is executed. This period is called the branch delay slot. In order to improve the efficiency of program execution, the compiler usually fills the branch delay slot with irrelevant instructions to prevent pipeline pauses and improve processing efficiency. Figure 1In the very long instruction word core pipeline shown, the branch instruction requires 6 clock cycles from instruction fetch to execution, the branch delay slot is 5 clock cycles, and can accommodate 5 parallel instruction packets.

[0068] Since the compiler compresses and merges the instruction code, one instruction word may contain multiple parallel instruction packages, and one parallel instruction package may also cross the instruction word boundary. When fetching instructions, it is not known whether a branch instruction has been fetched. When the execution station finds a branch instruction jump, there may be two situations:

[0069] 1. Due to reasons such as missing instruction cache or the back end of the instruction pipeline being unable to receive instructions, the instruction delay slot between the analysis and sorting (PACK) station and the instruction decoding (DEC) station does not yet contain all the instructions in the branch delay slot.

[0070] 2. Since the parallel instruction packets in the branch delay slot are highly compressed, the instructions cached between the analysis and arrangement (PACK) station and the instruction decoding (DEC) station already include all the instructions in the branch delay slot.

[0071] For case 1, since the instructions in the branch delay slot have not been fully obtained, and the current hit check (CHECK) station may not hit, it is necessary to wait for the analysis and sorting (PACK) station to obtain the instructions in the branch delay slot before the instructions can be fetched and executed from the branch target.

[0072] For case 2, since all the instructions in the branch delay slot have been obtained, instruction fetching and execution can be started directly from the branch target. When all the instructions in the branch delay slot are sent from the instruction fetch buffer, the excess instructions (irrelevant instructions) outside the delay slot and not at the branch target need to be cleared.

[0073] In addition, special processing is required for the situation where branch instructions are nested in the branch delay slot. First, all instructions in the branch delay slot must be obtained, and then jump to the branch target for execution. At this time, the number of branch delay slots is no longer the distance from the instruction fetch station to the execution station, but is determined by the distance between the branch in the delay slot and the previous branch. As many parallel instruction packages as the distance is, several parallel instruction packages are executed at the first branch target, and then jump to the branch target in the delay slot for execution.

[0074] In the case of nested branch instructions in the branch delay slot, for example Figure 2 In the case shown, the branch instruction is represented by B, and the instruction in the delay slot is represented by S. In case 2, the second parallel package in the delay slot of branch B0 contains branch B2, and the fourth parallel package contains branch B4. It is guaranteed that after all the instructions in the delay slot of branch B0 are obtained, it jumps to the target of branch B2 to fetch instructions, and after obtaining two parallel packages, it jumps to the target of branch B4 to fetch instructions. That is, the delay slot length of B0 is 5, the delay slot length of B2 is 2, and the delay slot length of B4 is also 2.

[0075] It can be seen that for branch instructions in high-performance DSP cores, under ideal conditions, it is necessary to ensure that instructions in the branch delay slot are accurately executed, that is, no instructions are missed and no multiple instructions are sent to the back end of the instruction pipeline. In addition, for the case of nested branches in the branch delay slot, it is also necessary to be able to quickly jump to the corresponding target address to fetch and execute instructions, thereby improving the core instruction fetching efficiency and reducing redundant instruction fetching while ensuring correctness.

[0076] In order to achieve the above technical effects, the present application relates to a method and device for fast fetching of branch instructions in a high-performance DSP core. An instruction fetch buffer is set between the instruction cache and the instruction pipeline. Each buffer entry can hold an instruction word, and a parallel instruction packet counter is set at the same time. After obtaining the instruction word from the instruction cache, the number of parallel instruction packets therein is analyzed in advance and stored in the instruction fetch buffer together with the instruction word. The execution station sets a counter to calculate the distance between two branch instructions, the maximum distance of which is the default branch delay slot cycle number, so as to determine the branch delay slot length of the current branch. The instruction analysis station sets a counter. After the execution station generates a branch jump request, the number of parallel instruction packets in the current instruction fetch buffer and the number of parallel instruction packets between the instruction analysis station and the execution station are counted. If the number of cached parallel instruction packets is greater than or equal to the branch delay slot length, the instruction can be fetched directly from the branch target. If the number of cached parallel instruction packets is less than the branch delay slot length, it is necessary to wait until all the parallel instruction packets in the branch delay slot are obtained before the instruction can be fetched from the branch target for execution. This application can ensure that when a branch jump occurs, it can determine in advance whether all instructions in the branch delay slot have been obtained, and then quickly jump to the branch target to fetch instructions, reduce the overhead of waiting for the branch delay slot, reduce the number of useless instructions obtained, improve core performance, and save power consumption.

[0077] The present application discloses an embodiment of a method for fetching instructions for branch instructions in a very long instruction word architecture. The method aims to fetch instructions from a branch delay slot in a high-performance DSP core and fetch instructions from a branch target as quickly as possible when a branch jump is encountered while ensuring correct program execution. Figure 1 Based on this, the following improvements are made to the branch delay slot instruction fetch process, see the attached manual. Figure 3 :

[0078] 1. Hit the Check Station.

[0079] At the hit check station, the number of parallel instruction packets (Execute Packet, referred to as EP) contained in the current instruction word is analyzed in advance. For example, the instruction word length of the DSP core is 256b, including 8 standard instructions or 14 compressed instructions. The maximum number of instructions that can be executed in parallel is 8, that is, the parallel packet contains a maximum of 8 instructions. Then a 4-bit instruction packet counter (EPCnt) is set (there can be a maximum of 14 parallel instruction packets), and a span flag (SpanFlag) is set to indicate whether the last parallel instruction packet spans the instruction word. When the instruction fetch hits, the instruction word together with the instruction packet counter (EPCnt) and the span flag (SpanFlag) are written into the instruction fetch buffer (FetchBuffer).

[0080] 2. Analyze and organize the platform (Pack platform).

[0081] At the analysis and sorting station, an instruction fetch buffer (FetchBuffer) of n entries is set. In addition to the instruction word, each entry also contains a 4-bit parallel instruction packet counter (EPCnt) and a span flag (SpanFlag).

[0082] The Pack station also sets a branch delay slot counter (DelayCnt). Whenever a branch jump request is received, the branch distance (BrDist) transmitted by the execution station is stored. The branch distance is the delay slot length of the current branch. At the same time, the number of parallel instruction packets in the fetch buffer (FetchBuffer) is counted as the initial value of the branch delay slot counter (DelayCnt). The calculation method is as follows:

[0083]

[0084] That is, the instruction packet counters (EPCnt) of all entries are added together, and then the number of stations where the instruction is valid between the Pack station and the Execution station is added.

[0085] When the last parallel instruction packet in an instruction word spans across instruction words, its entry span must be valid. Since the number of instructions in a parallel packet will never exceed 8, the parallel packet can only span to the next instruction word at most, and the EPCnt of the next instruction word will be included in the parallel instruction packet counting.

[0086] When a branch jump request is received, the value of the branch delay slot counter (DelayCnt) and the branch distance (BrDist) are compared:

[0087] If DelayCnt is greater than or equal to BrDist, instructions can be fetched directly from the branch target for execution. If the instructions in the branch delay slot in FetchBuffer have not been sent out, the remaining instructions will be cleared after they are sent out, and the instructions already fetched from the branch target will not be cleared.

[0088] If DelayCnt is less than BrDist, the branch jump request cannot be responded to. At this time, the branch jump target request, branch target address and branch delay slot distance BrDist are loaded into the instruction fetch request queue FetchQueue, and DelayCnt is saved at the same time, waiting for the current branch delay slot to be sent. During this period, each time a new instruction word is received, its EPCnt is accumulated to DelayCnt. When DelayCnt is greater than or equal to BrDist saved at the head of the instruction fetch request queue, the branch target address is taken from the head of the FetchQueue and instructions are fetched from there for execution, and the extra instructions outside the branch delay slot are cleared.

[0089] 3. Command execution platform (EXE platform).

[0090] The instruction execution station sets the branch delay slot distance counter BrDist to count the distance between two branches, with an initial value of 5 (i.e. the default branch delay slot length). When a branch instruction jumps, BrDist is sent to the analysis and sorting station for fast instruction fetching. If an instruction arrives in the next beat, the count starts again from 1, otherwise it starts from 0 and remains unchanged after it reaches 5 (the length of the branch delay slot).

[0091] An embodiment of a method for fetching branch instructions in a very long instruction word architecture provided by the present application comprises the following steps:

[0092] S100 , performing instruction fetch address arbitration on the instruction through an address arbitration station to obtain an arbitration address of the instruction.

[0093] S200 , receiving the arbitration address and accessing the instruction cache through a cache access station.

[0094] S300, checking whether the instruction fetch hits the instruction cache through a hit check station, and determining whether the instruction analysis station can receive the instruction; setting an instruction packet counter and a cross flag at the hit check station; the instruction packet counter is used to obtain instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; the cross flag is used to determine whether the last parallel instruction packet crosses the instruction word.

[0095] S310, when it is detected that the instruction fetch hits the instruction cache, the instruction word, the instruction packet counter value and the stride flag are written into the instruction fetch buffer.

[0096] Specifically, if the last parallel instruction packet spans the instruction word, the compiler has split the instruction word, that is, the spanned part is stored in the next instruction word, and when counting the number of parallel packets in the instruction word, the upper half is not counted, and the lower half is counted in the number of parallel packets of the next instruction word. After obtaining the instruction word from the instruction cache, the number of parallel instruction packets in the instruction word is analyzed in advance through the parallel instruction packet counter, and stored in the instruction fetch buffer together with the instruction word.

[0097] S400, cache the instructions that have been obtained through the instruction analysis station, perform parallel bit analysis on the obtained instructions, decompose the instruction words into parallel instruction packets and send them to the subsequent stations; set N instruction fetch buffer entries through the instruction analysis station, and the instruction fetch buffer is implemented as a circular buffer; the instruction fetch buffer is respectively set with an allocation pointer and an instruction fetch pointer, the allocation pointer is used to write the fetched instruction word, instruction packet counter value and span flag into the instruction fetch buffer entry to be currently allocated, and the instruction fetch pointer is used to select the parallel instruction packet to be sent to the next pipeline station; set a branch delay slot counter at the instruction analysis station, and the branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot.

[0098] Specifically, the number N of the instruction fetch buffer entries is related to the number of valid stations from the address arbitration station to the instruction analysis station. The number N of the instruction fetch buffer entries is equal to the number of pipeline stages at which the newly fetched instructions arrive at the instruction analysis station (pack station) where the value buffer is located after a re-fetch request is generated, so as to reduce pipeline pauses caused by re-fetching.

[0099] Reference Manual Attached Figure 3 , the number of valid stations between the address arbitration station and the instruction analysis station is 4, then at the analysis and sorting station, a 4-entry instruction fetch buffer can be set, and each entry of the instruction fetch buffer includes one instruction word, one instruction packet counter and a cross flag. More preferably, in some other implementations of this embodiment, assuming that there are 6 valid stations between the address arbitration station and the instruction analysis station, then the number of instruction fetch buffer entries can be set to 6.

[0100] The branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot, including the number of parallel instruction packets currently in the instruction cache (that is, the number of parallel instruction packets in the instruction cache obtained by the instruction packet counter), and the number of parallel instruction packets flying between the instruction analysis station and the execution station (that is, the instruction packets in the delay slot).

[0101] S500, by setting a branch delay slot distance counter on the instruction execution station, the branch delay slot distance counter is used to count the current branch delay slot length; after generating a branch jump request, the instruction execution station sends the branch delay slot length to the instruction analysis station for branch delay slot sending judgment.

[0102] In another implementation of the present embodiment, the step S300 further includes S320: when the hit check station detects that the instruction fetch does not hit the instruction cache, or the instruction analysis station cannot receive the instruction, the hit check station generates a re-instruction fetch request and feeds it back to the address arbitration station, and at the same time clears the instruction fetch request being processed by the cache access station.

[0103] Specifically, instruction fetch address arbitration refers to the process of scheduling and making decisions on these requests when multiple instructions simultaneously request to read instructions from the memory in a computer system. In a multi-core processor or a multi-threaded system, since each core or thread has its own instruction stream, multiple instruction fetch requests may be issued at the same time. The goal of instruction fetch address arbitration is to reasonably allocate and schedule these requests to improve the performance and efficiency of the system. In the present application, since the hit check station detects that the instruction fetch does not hit the instruction cache, or the instruction analysis station cannot receive the instruction, the generated re-fetch address will become one of the instruction fetch address sources of the address arbitration station.

[0104] In another implementation of this embodiment, a very long instruction word architecture branch instruction jump instruction fetching method, after step S400, further includes step: S410, setting an allocation pointer and an instruction fetching pointer in the instruction fetching buffer of the instruction analysis station.

[0105] Specifically, the instruction fetch buffer sets the allocation pointer to indicate the instruction fetch buffer entry to which the currently fetched instruction word is to be written; whenever the instruction fetch hits the instruction cache and the instruction fetch buffer can receive it, the instruction word, the instruction packet counter value and the span flag are written into the entry pointed to by the allocation pointer. When the entry pointed to by the allocation pointer is valid, the allocation pointer must coincide with the instruction fetch pointer, indicating that the instruction fetch buffer is full and cannot receive the newly written instruction; whenever a new instruction word is written, the allocation pointer moves to the next entry in sequence. The instruction fetch buffer sets the instruction fetch pointer to indicate the instruction fetch buffer entry to which the parallel instruction packet is currently to be sent; whenever a parallel instruction packet is sent to the next pipeline station, the corresponding instruction valid bit is cleared to 0. If the span flag of the instruction fetch buffer entry pointed to by the instruction fetch pointer is valid, indicating that the current parallel instruction packet spans the instruction word, then when sending the last parallel instruction packet, it must be sent to the next station together with the parallel instruction packet starting with the next instruction word. If the next instruction word has not been obtained, it is necessary to wait. When the entry pointed to by the instruction fetch pointer has no valid instruction, it means that the instruction fetch buffer is empty and no instruction needs to be sent to the next pipeline station; after all instructions in the currently pointed instruction fetch buffer entry have been sent, the instruction fetch pointer is moved to the next entry in sequence.

[0106] Another embodiment of a method for fetching branch instructions in a very long instruction word architecture according to the present application, based on the above-mentioned embodiment, further comprises the following steps:

[0107] S600: Dispatching the instructions in the parallel instruction package to a decoding station corresponding to a specific execution component through an instruction dispatching station.

[0108] S700: Decode the instruction via an instruction decoding station.

[0109] S800, executing the instruction through the instruction execution station to obtain a target address of a branch jump, and feeding back the target address to the address arbitration station to participate in the instruction fetch address arbitration.

[0110] Specifically, the branch target instruction fetch address and the exception / interrupt address of the instruction execution station will also become one of the instruction fetch address sources of the address arbitration station.

[0111] Another embodiment of a method for fetching branch instructions in a very long instruction word architecture of the present application, based on any one of the above method embodiments, further includes the steps of:

[0112] S410, when the instruction analysis station receives the branch jump request sent by the instruction execution station, it compares the value of the branch delay slot counter and the value of the branch delay slot distance counter. Specifically, it compares the "number of parallel instruction packets in the branch delay slot obtained" and the "current branch delay slot length".

[0113] In some implementations, the value of the branch delay slot counter when a branch jump request is received is calculated using the following formula:

[0114]

[0115] in, is the sum of the count values ​​of the instruction packet counters in the N instruction fetch buffers; ΣValid(stage j ) is the number of stations where instructions are valid between the analysis and sorting station and the instruction execution station. A valid station indicates that a parallel instruction package has been cached.

[0116] In some other implementations, the current value of the branch delay slot counter, that is, the "number of parallel instruction packets cached in the branch delay slot" is calculated by the following formula:

[0117]

[0118] in, The sum of the count values ​​of the instruction packet counters in the N instruction fetch buffers; is the carry generated by adding the stride flags in the N instruction fetch buffers; ΣValid(stage j ) is the number of stations where instructions are valid between the analysis and sorting station and the instruction execution station.

[0119] Preferably, the value of the branch delay slot distance counter is the distance between two branch delay slots, that is, the "current branch delay slot length". Figure 1 The default initial value of the branch delay slot length is 5. When a branch instruction jump is encountered, the value of the branch delay slot distance counter is sent to the analysis and sorting station for fast branch delay slot sending judgment. If an instruction arrives in the next beat, the count starts again from 1, otherwise it starts from 0 and remains unchanged after it reaches 5 (the default branch delay slot length).

[0120] S420: If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter, respond to the branch jump request, fetch instructions from the branch target address and execute, and clear the remaining instructions in the branch delay slot.

[0121] S430: If the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, the branch jump request is not responded to, the branch jump request, the branch target address and the length of the branch delay slot are loaded into the instruction fetch request queue, and instructions are fetched from the branch target address for execution after all the parallel instruction packets in the current branch delay slot are obtained.

[0122] Specifically, after the execution station generates a branch jump request, the number of parallel instruction packets in the current instruction fetch buffer and the number of parallel instruction packets between the instruction analysis station and the execution station are counted. If the number of cached parallel instruction packets is greater than or equal to the length of the branch delay slot, instructions can be fetched directly from the branch target. If the number of cached parallel instruction packets is less than the length of the branch delay slot, it is necessary to wait until all parallel instruction packets in the branch delay slot are obtained before instructions can be fetched from the branch target for execution.

[0123] In another implementation of this embodiment, when the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, while waiting for the parallel instruction packet in the current branch delay slot to be sent, each time a new instruction word is received, the number of its parallel instruction packets is accumulated to the branch delay slot counter.

[0124] If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter, the branch target address is taken out of the instruction fetch request queue and instructions are fetched from the branch target address for execution, while the extra instructions fetched outside the branch delay slot are cleared.

[0125] Based on the same technical concept, the present application also discloses a very long instruction word architecture branch instruction jump instruction fetching system, which can be used to implement any of the above-mentioned very long instruction word architecture branch instruction jump instruction fetching methods. Specifically, an embodiment of a very long instruction word architecture branch instruction jump instruction fetching system of the present application includes:

[0126] The address arbitration station is used to perform instruction fetch address arbitration on the instruction to obtain the arbitration address of the instruction.

[0127] Through cache access, the station receives the arbitration address and accesses the instruction cache.

[0128] The hit check station is used to check whether the instruction fetch hits the instruction cache and determine whether the instruction analysis station can receive the instruction; the hit check station is also used to set an instruction packet counter and a cross flag; the instruction packet counter is used to obtain instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; the cross flag is used to determine whether the last parallel instruction packet crosses the instruction word.

[0129] The hit check station is further used to write the instruction word, the instruction packet counter value and the cross flag into the instruction fetch buffer when it is checked that the instruction fetch hits the instruction cache.

[0130] Specifically, if the last parallel instruction packet in the instruction word spans the instruction word, the parallel instruction packets need to be merged and sent at the instruction analysis station. When counting the number of parallel packets in the instruction word, the upper half is not counted, and the lower half is counted into the number of parallel packets of the next instruction word. After obtaining the instruction word from the instruction cache, the number of parallel instruction packets in the instruction word is analyzed in advance through the parallel instruction packet counter, and stored in the instruction fetch buffer together with the instruction word.

[0131] The instruction analysis station is used to cache the instructions that have been obtained, perform parallel bit analysis on the obtained instructions, decompose the instruction words into parallel instruction packets and send them to subsequent stations; the instruction analysis station is also used to set N instruction fetch buffer entries and an allocation pointer and an instruction fetch pointer, and the allocation pointer and instruction fetch pointer cooperate to manage the instruction fetch buffer; the instruction analysis station is also used to set a branch delay slot counter, and the branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot.

[0132] Specifically, the number N of the instruction fetch buffer entries is related to the number of valid stations between the address arbitration station and the instruction analysis station. The number N of the instruction fetch buffer entries is equal to the number of pipeline stages at which the newly fetched instructions arrive at the instruction analysis station (pack station) where the value buffer is located after a re-fetch request is generated.

[0133] Reference Manual Attached Figure 3 , the number of valid stations between the address arbitration station and the instruction analysis station is 4, then at the analysis and sorting station, a 4-entry instruction fetch buffer can be set, and each entry of the instruction fetch buffer includes one instruction word, one instruction packet counter and a cross flag. More preferably, in some other implementations of this embodiment, assuming that there are 6 valid stations between the address arbitration station and the instruction analysis station, then the number of instruction fetch buffer entries can be set to 6.

[0134] The branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot, including the number of parallel instruction packets currently in the instruction cache (that is, the number of parallel instruction packets in the instruction cache obtained by the instruction packet counter), and the number of parallel instruction packets flying between the instruction analysis station and the execution station (that is, the instruction packets in the delay slot).

[0135] The instruction execution station is used to set a branch delay slot distance counter, and the branch delay slot distance counter is used to count the current branch delay slot length. After a branch jump request is generated, the instruction execution station is also used to send the branch delay slot length to the instruction analysis station for branch delay slot sending judgment.

[0136] Another embodiment of a very long instruction word architecture branch instruction jump instruction fetching system provided by the present application, based on the above system embodiment, the very long instruction word architecture branch instruction jump instruction fetching system further includes:

[0137] The instruction dispatching station is used to dispatch the instructions in the parallel instruction package to the decoding station corresponding to the specific execution component.

[0138] The instruction decoding station is used for decoding the instruction.

[0139] The instruction execution station is also used to execute the instruction, obtain the target address of the branch jump, and feed the target address back to the address arbitration station to participate in the instruction fetch address arbitration.

[0140] Specifically, the branch target instruction fetch address and the exception / interrupt address of the instruction execution station will also become one of the instruction fetch address sources of the address arbitration station.

[0141] Another embodiment of a branch instruction jump fetch system for a very long instruction word architecture provided by the present application, based on the above system embodiment, the instruction analysis station is also used to: when the instruction analysis station receives a branch jump request sent by the instruction execution station, compare the value of the branch delay slot counter of the instruction analysis station with the value of the branch delay slot distance counter. Specifically, compare: "the number of parallel instruction packets cached in the branch delay slot" and "the current branch delay slot length".

[0142] In some implementations, the value of the branch delay slot counter when a branch jump request is received is calculated using the following formula:

[0143]

[0144] in, is the sum of the count values ​​of the instruction packet counters in the N instruction fetch buffers; ΣValid(stage j ) is the number of stations where instructions are valid between the analysis and sorting station and the instruction execution station. A valid station indicates that a parallel instruction package has been cached.

[0145] In some other implementations, the current value of the branch delay slot counter, that is, the "number of parallel instruction packets cached in the branch delay slot" is calculated by the following formula:

[0146]

[0147] in, The sum of the count values ​​of the instruction packet counters in the N instruction fetch buffers; is the carry generated by adding the stride flags in the N instruction fetch buffers; ΣValid(stage j ) is the number of stations where instructions are valid between the analysis and sorting station and the instruction execution station.

[0148] Preferably, the value of the branch delay slot distance counter is the distance between two branch delay slots, that is, the "current branch delay slot length". Figure 1 The default initial value of the branch delay slot length is 5. When a branch instruction jump is encountered, the value of the branch delay slot distance counter is sent to the analysis and sorting station for fast instruction fetch judgment (branch delay slot sending judgment). If an instruction arrives in the next beat, the count starts again from 1, otherwise it starts from 0 and remains unchanged after it reaches 5 (default branch delay slot length).

[0149] If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter, the branch jump request is responded to, instructions are fetched from the branch target address for execution, and the remaining instructions in the branch delay slot are cleared.

[0150] If the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, the branch jump request is not responded to, the branch jump request, the branch target address and the length of the branch delay slot are loaded into the instruction fetch request queue, and the instruction is fetched from the branch target address after the parallel instruction packet in the current branch delay slot is sent.

[0151] Specifically, after the execution station generates a branch jump request, the number of parallel instruction packets in the current instruction fetch buffer and the number of parallel instruction packets between the instruction analysis station and the execution station are counted. If the number of cached parallel instruction packets is greater than or equal to the length of the branch delay slot, instructions can be fetched directly from the branch target. If the number of cached parallel instruction packets is less than the length of the branch delay slot, it is necessary to wait until all parallel instruction packets in the branch delay slot are obtained before instructions can be fetched from the branch target for execution.

[0152] In some other implementations of this embodiment, the instruction analysis station is also used for: when the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, while waiting for the parallel instruction packet in the current branch delay slot to be sent, each time a new instruction word is received, the number of parallel instruction packets is accumulated to the branch delay slot counter.

[0153] If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter, the branch target address is taken out of the instruction fetch request queue and instructions are fetched from the branch target address for execution, while the extra instructions fetched outside the branch delay slot are cleared.

[0154] The present application provides another embodiment of a branch instruction jump instruction fetch system for a very long instruction word architecture. Based on the above system embodiment, the hit check station is also used for: when the hit check station detects that the instruction fetch does not hit the instruction cache, or the instruction analysis station cannot receive the instruction, the hit check station generates a re-instruction fetch request and feeds it back to the address arbitration station, and at the same time clears the instruction fetch request being processed by the cache access station.

[0155] Specifically, in the present application, since the hit check station detects that the instruction fetch does not hit the instruction cache, or the instruction analysis station cannot receive the instruction, the generated re-fetch address will become one of the instruction fetch address sources of the address arbitration station.

[0156] The present application's branch instruction jump fetch method and system for a very long instruction word architecture have the same technical concept, and the technical details of the two embodiments are applicable to each other. To reduce repetition, they will not be repeated here.

[0157] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned program modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program units or modules to complete all or part of the functions described above. The program modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into a processing unit, and the above-mentioned integrated unit can be implemented in the form of hardware or in the form of software program units. In addition, the specific names of the program modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

[0158] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0159] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0160] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. Exemplarily, the device embodiments described above are merely schematic. Exemplarily, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation. Exemplarily, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0161] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0163] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0164] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for fetching branch instructions in a very long instruction word architecture, characterized in that: Includes steps: Performing instruction fetch address arbitration on the instruction through the address arbitration station to obtain the arbitration address of the instruction; receiving the arbitration address and accessing the instruction cache via a cache access station; Checking whether the instruction fetch hits the instruction cache through a hit check station, and judging whether the instruction analysis station can receive the instruction; setting an instruction packet counter and a cross flag at the hit check station; the instruction packet counter is used to obtain instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; the cross flag is used to judge whether the last parallel instruction packet crosses the instruction word; When it is detected that the instruction fetch hits the instruction cache, the instruction word, the instruction packet counter value and the cross flag are written into the instruction fetch buffer; The instruction analysis station caches the instructions that have been obtained, and performs parallel bit analysis on the obtained instructions, decomposes the instruction words into parallel instruction packets and sends them to the subsequent stations; the instruction analysis station sets N instruction fetch buffer entries, and the instruction fetch buffer is implemented as a circular buffer; the instruction fetch buffer is respectively set with an allocation pointer and an instruction fetch pointer, the allocation pointer is used to write the fetched instruction word, the instruction packet counter value and the cross flag into the instruction fetch buffer entry to be currently allocated, and the instruction fetch pointer is used to select the parallel instruction packet to be sent to the next pipeline station; the instruction analysis station sets a branch delay slot counter, and the branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot; By setting a branch delay slot distance counter on the instruction execution station, the branch delay slot distance counter is used to count the current branch delay slot length; after a branch jump request is generated, the instruction execution station sends the branch delay slot length to the instruction analysis station for branch delay slot sending judgment.

2. A method for fetching branch instructions in a very long instruction word architecture as claimed in claim 1, characterized in that: Also includes the steps: Dispatching the instructions in the parallel instruction package to a decoding station corresponding to a specific execution component through an instruction dispatching station; Decoding the instruction by an instruction decoding station; The instruction is executed by the instruction execution station to obtain a target address for branch jump, and the target address is fed back to the address arbitration station to participate in the instruction fetch address arbitration.

3. A method for fetching branch instructions in a very long instruction word architecture as claimed in claim 1, characterized in that: Also includes the steps: The instruction fetch buffer sets the allocation pointer to indicate the instruction fetch buffer entry into which the currently fetched instruction word is to be written; Whenever an instruction hits the instruction cache and the instruction fetch buffer can receive it, the instruction word, the instruction packet counter value and the cross flag are written into the entry pointed to by the allocation pointer; when the entry pointed to by the allocation pointer is valid, the allocation pointer must coincide with the instruction fetch pointer, indicating that the instruction fetch buffer is full and cannot receive the newly written instruction; Each time a new instruction word is written, the allocation pointer moves to the next entry in sequence.

4. A method for fetching branch instructions in a very long instruction word architecture as claimed in claim 3, characterized in that: Also includes the steps: The instruction fetch buffer sets the instruction fetch pointer to indicate the instruction fetch buffer entry to which the parallel instruction packet is currently to be sent; Whenever a parallel instruction packet is sent to the next pipeline station, the corresponding instruction valid bit is cleared to 0. If the span flag of the instruction fetch buffer entry pointed to by the instruction fetch pointer is valid, it means that the current parallel instruction packet spans the instruction word. Then, when the last parallel instruction packet is sent, it must be sent to the next station together with the parallel instruction packet starting with the next instruction word. If the next instruction word has not been obtained, it is necessary to wait. When there is no valid instruction in the entry pointed to by the instruction fetch pointer, it means that the instruction fetch buffer is empty and no instruction needs to be sent to the next pipeline station. After all instructions in the currently pointed instruction fetch buffer entry have been sent, the instruction fetch pointer is moved to the next entry in sequence.

5. A method for fetching branch instructions of a very long instruction word architecture as claimed in claim 1, characterized in that: Also includes the steps: When the instruction analysis station receives the branch jump request sent by the instruction execution station, comparing the value of the branch delay slot counter of the instruction analysis station with the value of the branch delay slot distance counter; If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter, respond to the branch jump request, fetch instructions from the branch target address for execution, and clear the extra instructions fetched outside the branch delay slot; If the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, the branch jump request will not be responded to, and the branch jump request, the branch target address and the length of the branch delay slot will be loaded into the instruction fetch request queue; at the same time, the value of the branch delay slot counter will be saved, and the instruction will be fetched from the branch target address for execution after all the parallel instruction packets in the current branch delay slot are obtained.

6. A method for fetching branch instructions in a very long instruction word architecture as claimed in claim 5, characterized in that: Also includes the steps: When the value of the branch delay slot counter is less than the value of the branch delay slot distance counter, in the process of waiting for the parallel instruction packet in the current branch delay slot to be sent, when the instruction fetch buffer receives a new instruction word, the number of parallel instruction packets is accumulated to the saved branch delay slot counter; If the value of the branch delay slot counter is greater than or equal to the value of the branch delay slot distance counter at the head of the instruction fetch request queue, the branch target address is taken out of the instruction fetch request queue and instructions are fetched from the branch target address for execution, and the extra instructions outside the branch delay slot are cleared.

7. A method for fetching branch instructions in a very long instruction word architecture as claimed in claim 1, characterized in that: Also includes the steps: When the hit check station detects that the instruction fetch does not hit the instruction cache, or the instruction analysis station cannot receive the instruction, the hit check station generates a re-instruction fetch request and feeds it back to the address arbitration station, while clearing the instruction fetch request being processed by the cache access station.

8. A method for fetching branch instructions in a very long instruction word architecture as claimed in claim 7, characterized in that: The instruction fetch address sources of the address arbitration station include: sequential instruction fetch addresses; re-fetch addresses of the hit check station; branch target instruction fetch addresses of the instruction execution station and exception / interrupt addresses.

9. A method for fetching branch instructions in a very long instruction word architecture as claimed in claim 1, characterized in that: The value of the branch delay slot counter when a branch jump request is received is calculated by the following formula: in, is the sum of the count values ​​of the instruction packet counters in the N instruction fetch buffers; ΣCalid(stage j ) is the number of stations where instructions are valid between the analysis and sorting station and the instruction execution station. A valid station indicates that a parallel instruction package has been cached.

10. A branch instruction jump fetch system for a very long instruction word architecture, characterized in that: include: An address arbitration station, used for performing instruction fetch address arbitration on the instruction to obtain the arbitration address of the instruction; Accessed via cache, for the station to receive the arbitration address and access the instruction cache; A hit check station is used to check whether the instruction fetch hits the instruction cache and determine whether the instruction analysis station can receive the instruction; the hit check station is also used to set an instruction packet counter and a cross flag; the instruction packet counter is used to obtain instruction words from the instruction cache and analyze the number of parallel instruction packets in the instruction cache; the cross flag is used to determine whether the last parallel instruction packet crosses the instruction word; The hit check station is further used to write the instruction word, the instruction packet counter value and the cross flag into the instruction fetch buffer when it is checked that the instruction fetch hits the instruction cache; The instruction analysis station is used to cache the instructions that have been obtained, and perform parallel bit analysis on the obtained instructions, decompose the instruction words into parallel instruction packets and send them to the subsequent stations; the instruction analysis station is also used to set N instruction fetch buffer entries and an allocation pointer and an instruction fetch pointer, and the allocation pointer and the instruction fetch pointer cooperate to manage the instruction fetch buffer; the instruction analysis station is also used to set a branch delay slot counter, and the branch delay slot counter is used to calculate the number of parallel instruction packets cached in the branch delay slot; The instruction execution station is used to set a branch delay slot distance counter, and the branch delay slot distance counter is used to count the current branch delay slot length; after generating a branch jump request, the instruction execution station is also used to send the branch delay slot length to the instruction analysis station for branch delay slot sending judgment.

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