A GaN smart power chip with junction temperature monitoring capability and a preparation method thereof

Abstract

The present invention relates to a GaN intelligent power chip with junction temperature monitoring capability, comprising: a two-dimensional electron gas structure, a first isolation groove, a second isolation groove, a lateral power device, an ohmic contact structure, and a temperature sensor diode, wherein the first isolation groove and the second isolation groove are arranged in the two-dimensional electron gas structure to isolate the two-dimensional electron gas channel in the two-dimensional electron gas structure, so that the two-dimensional electron gas structure forms a power device region, an ohmic contact resistance region, and a temperature sensor region that are arranged laterally in sequence; the lateral power device is arranged in the power device region, the ohmic contact structure is arranged in the ohmic contact resistance region, and the temperature sensor diode is arranged in the temperature sensor region; the temperature sensor diode is cascaded with the ohmic contact structure to form a temperature monitoring circuit. The GaN intelligent power chip has the advantages of fast response speed, high sensitivity, good linearity, high integration, low power loss, and small parasitic effect.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor intelligent power modules, and in particular relates to a GaN intelligent power chip with junction temperature monitoring capability and a preparation method thereof. Background Art

[0002] In recent years, GaN materials have attracted extensive attention and applications in the field of power electronics due to their advantages such as large bandgap, high breakdown electric field, fast response speed, radiation resistance and high temperature resistance. High electron mobility transistor (HEMT) devices made of them have gradually become the first choice in high-frequency and high-power applications due to their excellent switching characteristics and voltage resistance. GaN-based HEMT devices are core devices for high-frequency power conversion applications. In recent years, they have been widely used in fast chargers, electric vehicles, space radars and other fields. However, new applications have higher reliability requirements for GaN-based HEMT devices, and the reliability problems caused by device degradation cannot be ignored. The most common is the impact of long-term high operating temperature on the performance of GaN-based HEMT devices. When HEMT devices are working, frequent switching conversions will cause the heterojunction temperature to rise rapidly, and the carrier mobility of the two-dimensional electron gas (2DEG) channel will deteriorate due to the influence of temperature. Long-term operation at high temperatures may cause device degradation and reduced life, and serious safety problems.

[0003] In order to reduce or avoid device failures caused by high temperatures, in practical applications, the temperature of GaN-based power devices can be monitored by designing a temperature monitoring circuit at the board level. However, this method has several disadvantages: 1. The response speed is slow and the junction temperature of the HEMT device cannot be monitored in situ; 2. The integration is low, the design and production costs are high, and the board-level circuit volume is large, which does not conform to the design trend of power chips; 3. It will generate additional power consumption and a series of parasitic crosstalk, which is not conducive to the efficient operation of the power module and energy conservation. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a GaN smart power chip with junction temperature monitoring capability and a preparation method thereof. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The embodiment of the present invention provides a GaN smart power chip with junction temperature monitoring capability, comprising: a two-dimensional electron gas structure, a first isolation groove, a second isolation groove, a lateral power device, an ohmic contact structure, and a temperature sensor diode, wherein:

[0006] The first isolation groove and the second isolation groove are arranged in the two-dimensional electron gas structure to isolate the two-dimensional electron gas channel in the two-dimensional electron gas structure, so that the two-dimensional electron gas structure forms a power device region, an ohmic contact resistance region and a temperature sensor region which are arranged in sequence laterally;

[0007] The lateral power device is arranged in the power device region, the ohmic contact structure is arranged in the ohmic contact resistance region, and the temperature sensor diode is arranged in the temperature sensor region;

[0008] The temperature sensor diode is cascaded with the ohmic contact structure to form a temperature monitoring circuit.

[0009] In one embodiment of the present invention, the two-dimensional electron gas structure includes a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a first portion of a P-type GaN layer and a second portion of a P-type GaN layer, wherein:

[0010] The substrate, the nucleation layer, the buffer layer, the channel layer and the barrier layer are stacked in sequence from bottom to top, and the channel layer and the barrier layer form a two-dimensional electron gas channel;

[0011] The first portion of the P-type GaN layer is located on the surface of the barrier layer in the power device region;

[0012] The second portion of the P-type GaN layer is located on the surface of the barrier layer in the temperature sensor region.

[0013] In one embodiment of the present invention, both the first isolation groove and the second isolation groove extend from a surface of the barrier layer to a surface of the buffer layer.

[0014] In one embodiment of the present invention, the lateral power device comprises a source electrode, a drain electrode and a gate electrode, wherein:

[0015] The source electrode is located on one side of the first portion of the P-type GaN layer and above the two-dimensional electron gas channel;

[0016] The drain electrode is located on the other side of the first portion of the P-type GaN layer and above the two-dimensional electron gas channel;

[0017] The gate electrode is disposed on the first portion of the P-type GaN layer.

[0018] In one embodiment of the present invention, the ohmic contact structure includes a first ohmic contact electrode and a second ohmic contact electrode, wherein:

[0019] The first ohmic contact electrode and the second ohmic contact electrode are both located above the two-dimensional electron gas channel;

[0020] The first ohmic contact electrode is used for grounding.

[0021] In one embodiment of the present invention, the temperature sensor diode comprises a cathode and an anode, wherein:

[0022] The cathode is spaced apart and arranged on one side of the second portion of the P-type GaN layer and is located above the two-dimensional electron gas channel;

[0023] The anode is arranged on the surface of the barrier layer on the other side of the second portion of the P-type GaN layer and is in contact with the second portion of the P-type GaN layer;

[0024] The cathode is connected to the second ohmic contact electrode through a metal interconnection line and is used to output voltage; the anode is used to input power supply voltage.

[0025] In one embodiment of the present invention, a passivation layer is further included, wherein:

[0026] The passivation layer covers a surface of the first isolation groove, a surface of the second isolation groove, a surface of the barrier layer, a surface of a portion of the first portion of the P-type GaN layer, and a surface of the second portion of the P-type GaN layer;

[0027] The anode overlaps the passivation layer.

[0028] Another embodiment of the present invention provides a method for preparing a GaN smart power chip with a junction temperature monitoring capability, comprising the steps of:

[0029] S1. Preparation of two-dimensional electron gas structure;

[0030] S2, etching the two-dimensional electron gas structure to below the two-dimensional electron gas channel to form a first isolation groove and a second isolation groove, isolating the two-dimensional electron gas structure into a power device region, an ohmic contact resistance region, and a temperature sensor region which are sequentially arranged laterally;

[0031] S3, depositing a passivation layer on the surface of the two-dimensional electron gas structure, the surface of the first isolation groove, and the surface of the second isolation groove;

[0032] S4, preparing a metal electrode above the two-dimensional electron gas channel of the two-dimensional electron gas structure to form a lateral power device arranged in the power device area, an ohmic contact structure arranged in the ohmic contact resistance area, and a temperature sensor diode arranged in the temperature sensor area;

[0033] S5. cascade-connecting the temperature sensor diode and the ohmic contact structure using interconnecting metal wires.

[0034] In one embodiment of the present invention, step S1 comprises:

[0035] S11, sequentially preparing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a P-type GaN layer on the cladding surface of the substrate, wherein a two-dimensional electron gas channel is formed between the channel layer and the barrier layer;

[0036] S12, etching the P-type GaN layer to form a first portion of the P-type GaN layer and a second portion of the P-type GaN layer that are spaced apart.

[0037] In one embodiment of the present invention, step S4 includes:

[0038] S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer, and etching the passivation layer and the barrier layer in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves extending to the surface of the channel layer;

[0039] S42, depositing ohmic metal in the plurality of ohmic metal electrode grooves and performing annealing to form a cathode, a first ohmic contact electrode, a second ohmic contact electrode, a source electrode, and a drain electrode, wherein the cathode is arranged in the temperature sensor region and located on one side of the second portion of the P-type GaN layer, the first ohmic contact electrode and the second ohmic contact electrode are arranged in the ohmic contact resistance region with an interval, and the source electrode and the drain electrode are distributed in the power device region and located on both sides of the first portion of the P-type GaN layer;

[0040] S43, defining a gate region and an anode region on the surface of the passivation layer, and etching the passivation layer in the gate region to the first portion of the P-type GaN layer, and etching the passivation layer in the anode region to the barrier layer to form a gate groove and an anode groove;

[0041] S44. Depositing Schottky metal in the gate groove and the anode groove to form a gate electrode and an anode, wherein the gate electrode is located in the power device region and on the first portion of the P-type GaN layer, and the anode is in contact with the other side of the second portion of the P-type GaN layer and overlaps the passivation layer.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] In the GaN intelligent power chip of the present invention, the lateral power device and the temperature monitoring circuit are integrated on the two-dimensional electron gas structure, and the junction temperature change of the GaN HEMT can be measured in situ, thereby improving the response speed of the HEMT temperature monitoring; the cascade design of the temperature sensor diode and the ohmic contact structure is adopted to ensure that the temperature sensing function part is jointly completed by the sensor diode and the ohmic contact structure when the voltage input remains unchanged, and the temperature sensing ability is the superposition of the sensor diode and the ohmic contact structure, which greatly improves the temperature sensitivity of the temperature sensing function part; therefore, the GaN intelligent power chip has the advantages of fast response speed, high sensitivity, good linearity, high integration, low power loss and small parasitic effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the three-dimensional structure of a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of a main view of a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention;

[0046] Figure 3 A schematic flow chart of a method for preparing a GaN smart power chip with junction temperature monitoring capability provided by an embodiment of the present invention;

[0047] Figure 4a-Figure 4i A schematic diagram of a process of preparing a GaN smart power chip with junction temperature monitoring capability provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0049] Embodiment 1

[0050] See also Figure 1 and Figure 2 , Figure 1 A schematic diagram of the three-dimensional structure of a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention, Figure 2 A schematic front view of a GaN smart power chip with over-temperature protection capability provided in an embodiment of the present invention.

[0051] The GaN smart power chip with junction temperature monitoring capability of this embodiment includes two parts, from left to right: 1. lateral power device, such as GaN lateral power HEMT device; 2. Junction temperature monitoring smart circuit part, including ohmic contact resistor and GaN lateral diode temperature sensor. The GaN smart power chip specifically includes: a two-dimensional electron gas structure 1, a first isolation groove 2, a second isolation groove 3, a lateral power device 4, an ohmic contact structure 5, and a temperature sensor diode 6. Among them, the first isolation groove 2 and the second isolation groove 3 are arranged in the two-dimensional electron gas structure 1, and the two-dimensional electron gas channel in the two-dimensional electron gas structure 1 is isolated, so that the two-dimensional electron gas structure 1 forms a power device area, an ohmic contact resistor area and a temperature sensor area which are arranged in sequence in a transverse direction; the lateral power device 4 is arranged in the power device area, the ohmic contact structure 5 is arranged in the ohmic contact resistor area, and the temperature sensor diode 6 is arranged in the temperature sensor area; the temperature sensor diode 6 is cascaded with the ohmic contact structure 5 to form a temperature monitoring circuit.

[0052] Specifically, the bottoms of the first isolation groove 2 and the second isolation groove 3 extend to below the two-dimensional electron gas channel in the two-dimensional electron gas structure 1, isolating the two-dimensional electron gas channel, so that the two-dimensional electron gas structure 1 forms an electrically isolated power device region, an ohmic contact resistance region, and a temperature sensor region, and these three regions are arranged horizontally in sequence, and are correspondingly provided with a lateral power device 4, an ohmic contact structure 5, and a temperature sensor diode 6. Further, the ohmic contact structure 5 and the temperature sensor diode 6 are cascaded to form a temperature monitoring circuit to realize the temperature monitoring function.

[0053] In the GaN intelligent power chip of the present invention, the lateral power device and the temperature monitoring circuit are integrated on the two-dimensional electron gas structure, and the junction temperature change of the GaN HEMT can be measured in situ, thereby improving the response speed of the HEMT temperature monitoring; the cascade design of the temperature sensor diode and the ohmic contact structure is adopted to ensure that the temperature sensing function part is jointly completed by the sensor diode and the ohmic contact structure when the voltage input remains unchanged, and the temperature sensing ability is the superposition of the sensor diode and the ohmic contact structure, which greatly improves the temperature sensitivity of the temperature sensing function part; therefore, the GaN intelligent power chip has the advantages of fast response speed, high sensitivity, good linearity, high integration, low power loss and small parasitic effect.

[0054] In a specific embodiment, the two-dimensional electron gas structure 1 includes a substrate 11, a nucleation layer 12, a buffer layer 13, a channel layer 14, a barrier layer 15, a first portion of a P-type GaN layer 16, and a second portion of a P-type GaN layer 17. The substrate 11, the nucleation layer 12, the buffer layer 13, the channel layer 14, and the barrier layer 15 are stacked in sequence from bottom to top, and the channel layer 14 and the barrier layer 15 form a two-dimensional electron gas channel; the first portion of the P-type GaN layer 16 is located on the surface of the barrier layer 15 in the power device region; and the second portion of the P-type GaN layer 17 is located on the surface of the barrier layer 15 in the temperature sensor region.

[0055] Specifically, the substrate 11 is made of P-type (1, 1, 1) crystal orientation silicon material; the nucleation layer 12, the buffer layer 13, the channel layer 14 and the barrier layer 15 are made of AlN material, AlGaN material, GaN material and AlGaN material respectively. A two-dimensional electron gas channel is formed between the GaN channel layer 14 and the AlGaN barrier layer 15; accordingly, the first isolation groove 2 and the second isolation groove 3 separate the two-dimensional electron gas channel, which can extend to the inside of the GaN channel layer 14 or to the surface of the GaN buffer layer 13.

[0056] Specifically, the first portion of the P-type GaN layer 16 and the second portion of the P-type GaN layer 17 are stacked at different positions laterally above the barrier layer 15, and the materials of both layers include Mg + Ion-doped GaN, hole doping concentration is 10 17 -10 18 cm -3 , the thickness is 60-80nm.

[0057] In a specific embodiment, the lateral power device 4 is a HEMT power device, including a source electrode 41, a drain electrode 42 and a gate electrode 43. The source electrode 41, the gate electrode 43 and the drain electrode 42 are all arranged in the power device region; the source electrode 41 is located on one side of the first part of the P-type GaN layer 16 and is located above the two-dimensional electron gas channel; the drain electrode 42 is located on the other side of the first part of the P-type GaN layer 16 and is located above the two-dimensional electron gas channel; the gate electrode 43 is arranged on the first part of the P-type GaN layer 16.

[0058] Specifically, the source electrode 41 and the drain electrode 42 are located above the two-dimensional electron gas channel, and may extend to the surface of the GaN channel layer 14 or to the inside of the AlGaN barrier layer 15 .

[0059] It should be noted that the power device of this embodiment is not limited to the HEMT power device, and may also include other types of power devices, such as a GaN GIT device.

[0060] In a specific embodiment, the ohmic contact structure 5 includes a first ohmic contact electrode 51 and a second ohmic contact electrode 52 , wherein the first ohmic contact electrode 51 and the second ohmic contact electrode 52 are both located above the two-dimensional electron gas channel; the first ohmic contact electrode 51 is used for grounding.

[0061] Specifically, the first ohmic contact electrode 51 and the second ohmic contact electrode 52 are located above the two-dimensional electron gas channel, and may extend to the surface of the GaN channel layer 14 or to the inside of the AlGaN barrier layer 15 .

[0062] In a specific embodiment, the temperature sensor diode 6 includes a cathode 61 and an anode 62, wherein the cathode 61 is arranged at an interval on one side of the second portion of the P-type GaN layer 17 and is located above the two-dimensional electron gas channel; the anode 62 is arranged on the surface of the barrier layer 15 on the other side of the second portion of the P-type GaN layer 17 and is in contact with the second portion of the P-type GaN layer 17; the cathode 61 is connected to the second ohmic contact electrode 52 through a metal interconnection line and is used for outputting voltage; the anode 62 is used for inputting power supply voltage.

[0063] Specifically, the cathode 61 is located above the two-dimensional electron gas channel, and may extend to the surface of the GaN channel layer 14 , or may extend to the inside of the AlGaN barrier layer 15 .

[0064] In a specific embodiment, the GaN smart power chip also includes a passivation layer 7, wherein the passivation layer 7 covers the surface of the first isolation groove 2, the surface of the second isolation groove 3, the surface of the barrier layer 15, the partial surface of the first portion of the P-type GaN layer 16, and the surface of the second portion of the P-type GaN layer 17; the anode 62 overlaps the passivation layer 7.

[0065] Specifically, the passivation layer 7 covers the bottom and sidewalls of the first isolation groove 2, the bottom and sidewalls of the second isolation groove 3, the upper surface of the barrier layer 15, the upper surface of the first portion of the P-type GaN layer 16 except the gate electrode 10, the upper surface of the second portion of the P-type GaN layer 17 and the side surface close to the cathode 62. The material of the passivation layer 7 includes Si3N4, and the thickness is 100-150nm.

[0066] Furthermore, the electrode structure of the above-mentioned GaN smart power chip can be realized by electrode grooves, including a source electrode groove, a drain electrode groove, a gate electrode groove, a first ohmic contact electrode groove, a second ohmic contact electrode groove, a cathode groove and an anode groove.

[0067] Specifically, the source electrode groove and the drain electrode groove are located on both sides of the first part of the P-type GaN layer 16 in the power device region in different opposite directions, and the source electrode groove is close to the first part of the P-type GaN layer 16, and the drain electrode groove is far away from the first part of the P-type GaN layer 16. The groove depth is equal to the sum of the thickness of the passivation layer 7 and the barrier layer 15; the source and drain electrodes are both made of ohmic contact metal, which fills the source electrode groove and the drain electrode groove and overlaps the passivation layer 7 around the groove. The gate groove is located above the first part of the P-type GaN layer 16 in the power HEMT mesa region, and the groove depth is less than the thickness of the passivation layer 7; the gate electrode is a gate Schottky metal, which fills the gate groove and overlaps the passivation layer 7 around the gate groove.

[0068] The first ohmic contact electrode groove and the second ohmic contact electrode groove are located on both lateral sides of the ohmic contact resistance area and are separated by a certain distance. The distance between the two sides is determined by the designed resistance value. The larger the designed resistance value, the larger the distance. The groove depth is equal to the sum of the thickness of the passivation layer 7 and the barrier layer 15. The first ohmic contact electrode 51 adopts ohmic contact metal, which fills the first ohmic contact electrode groove and overlaps the passivation layer 7 around the groove, and is used to connect the ground terminal. The second ohmic contact electrode 52 adopts ohmic contact metal, which fills the second ohmic contact electrode groove and overlaps the passivation layer 7 around the groove, and is connected to the rectangular cathode 61 of the high-sensitivity lateral GaN temperature sensor through an interconnecting metal wire.

[0069] The anode groove is located on one side of the second part of the P-type GaN layer 17 in the temperature sensor area, and the groove depth is equal to the thickness of the passivation layer 7; the anode 62 is a T-shaped anode, using an anode Schottky metal, the anode Schottky metal fills the anode groove and overlaps the passivation layer 7 around the anode groove, the top of the T-shaped anode metal covers the passivation layer 7, and the anode Schottky metal contacts the side of the second part of the P-type GaN layer 17. The cathode groove is located on the other side of the temperature sensor area away from the second part of the P-type GaN layer 17, and the groove depth is equal to the sum of the thickness of the passivation layer 7 and the barrier layer 15; the cathode 61 is a rectangular cathode, using a cathode ohmic metal, the cathode ohmic metal fills the cathode groove and overlaps the passivation layer 7 around the cathode groove.

[0070] In this embodiment, the electrode overlaps the passivation layer around the groove, which means that the width of the top of the electrode is greater than the width of the bottom, and the top covers the passivation layer around the groove.

[0071] Exemplarily, the material of the source electrode 41 and the drain electrode 42 is ohmic metal, including one or more of Ti, Al, Ni, and Au; the material of the gate electrode 43 is Schottky metal, including one or more of TiN, Ti, and Al; the material of the first ohmic contact electrode 51 and the second ohmic contact electrode 52 both include one or more of Ti, Al, Ni, and Au; the material of the cathode 61 is ohmic metal, including one or more of Ti, Al, Ni, and Au; the material of the anode 62 is Schottky metal, including one or more of TiN, Ti, and Al; the material of the interconnecting metal wire includes Cu.

[0072] This embodiment does not limit the thickness of each structural layer of the GaN intelligent power chip, and the thickness can be selected according to the actual performance requirements for the T-type anode GaN Schottky temperature sensor.

[0073] It should be noted that the power device, ohmic contact structure, and temperature sensor diode of the present invention are not limited to the above-mentioned structures. On the basis of satisfying the concept that the power device, ohmic contact structure, and temperature sensor diode are all integrated on the same epitaxial wafer and the ohmic contact structure and the temperature sensor diode are cascaded, the power device, ohmic contact structure, and temperature sensor diode may adopt other structures.

[0074] A small-amplitude power supply voltage is applied to the anode of the above-mentioned GaN intelligent power chip, and the output voltage detection is connected in parallel with the second ohmic contact electrode and the cathode of the temperature sensor, and the first ohmic contact electrode is grounded, wherein the ohmic contact resistance is used to measure the performance of the ohmic contact electrode. The temperature monitoring circuit enters the working state, and the current-voltage relationship between the temperature sensor diode and the ohmic contact resistor is affected differently by temperature. The temperature sensor and the ohmic contact resistor are set in the same branch to keep the current consistent. When the HEMT junction temperature changes, the junction temperature of the sensor diode and the ohmic contact resistor also changes rapidly. The output voltage value is the power supply voltage minus the diode voltage drop, and at the same time the voltage drop on the ohmic contact resistor, which is equivalent to combining the temperature sensing capabilities of the temperature sensor diode and the resistor, significantly increasing the temperature sensitivity of the temperature monitoring circuit.

[0075] Therefore, the temperature monitoring circuit of this embodiment is integrated with the GaN power HEMT on the same epitaxial wafer, and the junction temperature change of the GaN HEMT can be measured in situ, thereby improving the response speed of the HEMT temperature monitoring; the design adopts a cascade design of a lateral GaN temperature sensor diode and an ohmic contact resistor, so that when the voltage input remains unchanged, the temperature sensing function part is jointly completed by the sensor diode and the ohmic contact resistor, and the temperature sensing capability is the superposition of the sensor diode and the ohmic contact resistor, which greatly improves the temperature sensitivity of the temperature sensing function part.

[0076] Compared with traditional board-level integrated circuits, the GaN smart power chip of this embodiment has the advantages of low parasitic crosstalk, small chip size, high integration, low manufacturing cost, and low power loss, and is very suitable for industrial production.

[0077] In summary, the GaN smart power chip of this embodiment has the following advantages: 1. It can monitor the junction temperature change of HEMT in situ with fast response speed; 2. It adopts a combination of diode and resistor as the temperature sensing part, with high temperature sensitivity and good linearity; 3. It has high integration; 4. It has low power loss and small parasitic effect.

[0078] Embodiment 2

[0079] Based on Example 1, see Figure 3 and Figure 4a-Figure 4i , Figure 3 A schematic diagram of a process for preparing a GaN smart power chip with junction temperature monitoring capability provided by an embodiment of the present invention is provided. Figure 4a-Figure 4i A schematic diagram of a process for preparing a GaN smart power chip with junction temperature monitoring capability provided by an embodiment of the present invention. The preparation method comprises the following steps:

[0080] S1, preparing a two-dimensional electron gas structure 1. Specifically comprising the steps of:

[0081] S11, sequentially preparing a nucleation layer 12, a buffer layer 13, a channel layer 14, a barrier layer 15 and a P-type GaN layer on the cladding surface of the substrate 11, wherein a two-dimensional electron gas channel is formed between the channel layer 14 and the barrier layer 15, such as Figure 4a shown.

[0082] Specifically, the two-dimensional electron gas structure 1 includes a substrate 11, a nucleation layer 12, a buffer layer 13, a channel layer 14, a barrier layer 15 and a P-type GaN layer stacked in sequence from bottom to top. The substrate 11 is made of P-type (1, 1, 1) crystal orientation silicon material; the nucleation layer 12, the buffer layer 13, the channel layer 14 and the barrier layer 15 are made of AlN material, AlGaN material, GaN material and AlGaN material respectively. The material of the P-type GaN layer is Mg + Ion-doped GaN. For example, the buffer layer 13 is made of Al 0.3 Ga 0.7 N material, the barrier layer 15 is made of Al 0.2 Ga 0.8 N material.

[0083] Step S11 specifically includes:

[0084] S111. A low-temperature AlN nucleation layer is epitaxially grown on the upper surface of the Si material substrate 11 using a metal-organic chemical vapor deposition (MOCVD) technique, and then a high-temperature AlN nucleation layer is epitaxially grown on the upper surface of the low-temperature AlN nucleation layer, and the two together form a nucleation layer 12; the thickness of the low-temperature AlN nucleation layer may be 30 nm, and the thickness of the high-temperature AlN nucleation layer may be 170 nm.

[0085] S112, using trimethylaluminum as an aluminum source, trimethylgallium as a gallium source, and ammonia as an ammonia source, using MOCVD technology to deposit undoped Al on the surface of the nucleation layer 12 0.3 Ga 0.7 N buffer layer 13, the thickness of the buffer layer 13 is 5 μm.

[0086] S113, using trimethylgallium as a gallium source and ammonia as an ammonia source, an undoped GaN channel layer 14 is deposited on the upper surface of the buffer layer 13 by using MOCVD technology, and the thickness of the channel layer 14 is 200 nm.

[0087] S114, using trimethylgallium as a gallium source, trimethylaluminum as an aluminum source, and ammonia as an ammonia source, an undoped Al2O3 layer is deposited on the upper surface of the channel layer 14 by MOCVD technology. 0.2 Ga 0.8 N barrier layer 15; the thickness of the barrier layer 15 is 15 nm.

[0088] S115, epitaxially growing a Mg+ doped GaN layer on the upper surface of the barrier layer 15 by using MOCVD technology, and forming a P-type GaN layer by high temperature annealing of the epitaxially grown Mg+ doped GaN layer; the thickness of the P-type GaN layer is 60nm-80nm, and the hole doping concentration of the P-type GaN layer is 10 17 -10 18 cm -3 .

[0089] S12, etching the P-type GaN layer to form a first portion of the P-type GaN layer 16 and a second portion of the P-type GaN layer 17 spaced apart from each other, as shown in FIG. Figure 4b shown.

[0090] Specifically, first, a P-GaN region under the HEMT gate and a P-GaN region under the temperature sensor diode anode are defined on one side of the surface of the P-GaN layer. Next, a photoresist is spin-coated and exposed and developed, and the P-GaN layer outside the defined region is etched downward using plasma (ICP) slow etching until the etching depth extends to the barrier layer 15, thereby forming a first portion of the P-GaN layer 16 and a second portion of the P-GaN layer 17.

[0091] S2, etching the two-dimensional electron gas structure 1 to below the two-dimensional electron gas channel to form a first isolation groove 2 and a second isolation groove 3, isolating the two-dimensional electron gas structure 1 into a power device region, an ohmic contact resistance region, and a temperature sensor region which are sequentially arranged laterally, such as Figure 4c shown.

[0092] Specifically, a power device area, an ohmic contact resistance area and a diode temperature sensor area are defined on the surface of the current sample, and then photoresist is spin-coated and exposed and developed, and plasma (ICP) is used to etch down the AlGaN barrier layer 15 and the GaN channel layer 14 outside the defined area until the etching depth extends to the buffer layer 13, forming a first isolation groove 2 and a second isolation groove 3.

[0093] S3, depositing a passivation layer 7 on the surface of the two-dimensional electron gas structure 1, the surface of the first isolation groove 2, and the surface of the second isolation groove 3, such as Figure 4d shown.

[0094] Specifically, the barrier layer 15 on the surface of the current sample, i.e., the area where the P-type GaN layer is etched, the upper surface of the first part of the P-type GaN layer 44, the upper surface of the second part of the P-type GaN layer 63, the bottom and side of the first isolation groove 2, and the bottom and side of the second isolation groove 3, are used to deposit the passivation layer 7 using PECVD technology with silane as the silicon source and ammonia as the ammonia source, so that the thickness of the passivation layer 7 reaches 100-150nm. After the passivation layer 7 is deposited, it covers the upper surface of the P-type GaN layer. Exemplarily, the passivation layer 7 can be a Si3N4 passivation layer.

[0095] S4. Prepare a metal electrode above the two-dimensional electron gas channel of the two-dimensional electron gas structure 1 to form a lateral power device 4 arranged in the power device area, an ohmic contact structure 5 arranged in the ohmic contact resistance area, and a temperature sensor diode 6 arranged in the temperature sensor area.

[0096] Exemplarily, taking the case where the lateral power device 4 includes a source electrode 41, a drain electrode 42 and a gate electrode 43, the ohmic contact structure 5 includes a first ohmic contact electrode 51 and a second ohmic contact electrode 52, and the temperature sensor diode 6 includes a cathode 61 and an anode 62, step S4 specifically includes the following steps:

[0097] S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer 7, and etching the passivation layer 7 and the barrier layer 15 in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves extending to the surface of the channel layer 14, such as Figure 4e shown.

[0098] First, on the passivation layer 7 on the surface of the current sample, the source electrode groove region, the drain electrode groove region, the cathode groove region, the first ohmic contact electrode groove region, and the second ohmic contact electrode groove region of the HEMT device are defined. Then, photoresist is spin-coated on the surface of the current sample and exposed and developed, and the passivation layer 7 outside the defined region is etched downward by reactive ion etching (RIE) until the etching depth extends to the channel layer 13, and finally the photoresist is removed.

[0099] S42, depositing ohmic metal in a plurality of ohmic metal electrode grooves and performing annealing to form a cathode 62, a first ohmic contact electrode 51, a second ohmic contact electrode 52, a source electrode 41 and a drain electrode 42, wherein the cathode 62 is arranged in the temperature sensor region and is located on one side of the second portion of the P-type GaN layer 17, the first ohmic contact electrode 51 and the second ohmic contact electrode 52 are arranged at intervals in the ohmic contact resistance region, the source electrode 41 and the drain electrode 42 are distributed in the power device region and are located on both sides of the first portion of the P-type GaN layer 16, as shown in FIG. Figure 4f shown.

[0100] Specifically, first, on the surface of the current sample, define the source electrode region and drain electrode region of the HEMT device, the cathode region of the temperature sensor, the first ohmic contact electrode region, and the second ohmic contact electrode region. Then, a double-layer photoresist is spin-coated and exposed and developed, and Ti, Al, Ni and Au are deposited from bottom to top using electron beam evaporation technology to prepare ohmic contacts, and the thickness of each metal layer is 20nm, 140nm, 50nm and 40nm, respectively. Next, the deposited ohmic metal is subjected to a rapid thermal annealing process to form an ohmic contact electrode; illustratively, the rapid thermal annealing temperature is 850°C and the time is 30 seconds. Finally, the photoresist on the surface of the sample is removed to form a cathode 62, a first ohmic contact electrode 51, a second ohmic contact electrode 52, a source electrode 41 and a drain electrode 42.

[0101] S43, defining a gate region and an anode region on the surface of the passivation layer 7, and etching the passivation layer 7 in the gate region to the first part of the P-type GaN layer 16, and etching the passivation layer 7 in the anode region to the barrier layer 15, to form a gate groove and an anode groove, such as Figure 4g shown.

[0102] Specifically, first, the gate electrode groove region of the HEMT device and the anode groove region of the temperature sensor diode are defined on the surface of the current sample, wherein the gate electrode groove region is located on the surface of the first part of the P-type GaN layer 16, and the anode groove region is located on the surface of the passivation layer 7 away from the cathode in the temperature sensor diode region. Then, the photoresist is spin-coated and exposed and developed, and the passivation layer 7 defining the gate groove region and the anode groove region is etched downward by reactive ion etching (RIE), and the etching depth extends to the surface of the first part of the P-type GaN layer 16 and the surface of the barrier layer 15, respectively. Finally, the photoresist on the surface of the sample is removed to form the gate electrode groove and the anode groove.

[0103] S44, depositing Schottky metal in the gate groove and the anode groove to form a gate electrode 43 and an anode 62, wherein the gate electrode 43 is located in the power device region and on the first part of the P-type GaN layer 16, and the anode 62 is in contact with the other side of the second part of the P-type GaN layer 17 and overlaps the passivation layer 7, as shown in FIG. Figure 4h shown.

[0104] Specifically, first, define the gate electrode region of the HEMT device and the anode region of the temperature sensor diode. Then, spin-coat a double-layer photoresist and expose and develop it. Use magnetron sputtering technology to sputter TiN, Ti, Al and TiN metals from bottom to top to prepare the Schottky contact gate and T-type anode. The thickness of each metal layer is 30nm, 20nm, 220nm and 30nm respectively. Finally, remove the photoresist on the surface of the sample to form a gate electrode 43 and an anode 62.

[0105] S5, cascade the temperature sensor diode 6 and the ohmic contact structure 5 using interconnecting metal wires, such as Figure 4i shown.

[0106] Specifically, the temperature sensor diode cathode 61 is connected in series with the second ohmic contact electrode 52 through metal wire interconnection, and the first ohmic contact electrode 51 is connected to ground, thereby completing the preparation of a GaN smart power chip with junction temperature monitoring capability.

[0107] The preparation method of the GaN smart power chip in this embodiment is highly consistent with the existing power HEMT preparation process, which can reduce production costs; the designed temperature monitoring circuit can be horizontally integrated with the power HEMT in the same epitaxial wafer, and no additional process steps are required, and the process steps are simple. The manufactured GaN smart power chip can monitor the junction temperature change of the HEMT in situ, with a fast response speed; compared with traditional board-level circuit integration, it has the advantages of low parasitic crosstalk, small chip size, high integration, low manufacturing cost, and low power loss, and is very suitable for industrial production.

[0108] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A GaN smart power chip with junction temperature monitoring capability, characterized in that: include: A two-dimensional electron gas structure (1), a first isolation groove (2), a second isolation groove (3), a lateral power device (4), an ohmic contact structure (5), and a temperature sensor diode (6), wherein: The first isolation groove (2) and the second isolation groove (3) are arranged in the two-dimensional electron gas structure (1) to isolate the two-dimensional electron gas channel in the two-dimensional electron gas structure (1), so that the two-dimensional electron gas structure (1) forms a power device region, an ohmic contact resistance region and a temperature sensor region which are arranged in sequence laterally; The lateral power device (4) is arranged in the power device area, the ohmic contact structure (5) is arranged in the ohmic contact resistance area, and the temperature sensor diode (6) is arranged in the temperature sensor area; The temperature sensor diode (6) is cascaded with the ohmic contact structure (5) to form a temperature monitoring circuit.

2. The GaN smart power chip with junction temperature monitoring capability according to claim 1, characterized in that: The two-dimensional electron gas structure (1) comprises a substrate (11), a nucleation layer (12), a buffer layer (13), a channel layer (14), a barrier layer (15), a first portion of a P-type GaN layer (16) and a second portion of a P-type GaN layer (17), wherein: The substrate (11), the nucleation layer (12), the buffer layer (13), the channel layer (14) and the barrier layer (15) are stacked in sequence from bottom to top, and the channel layer (14) and the barrier layer (15) form a two-dimensional electron gas channel; The first portion of the P-type GaN layer (16) is located on the surface of the barrier layer (15) in the power device region; The second portion of the P-type GaN layer (17) is located on the surface of the barrier layer (15) in the temperature sensor region.

3. The GaN smart power chip with junction temperature monitoring capability according to claim 2, characterized in that: The first isolation groove (2) and the second isolation groove (3) both extend from the surface of the barrier layer (15) to the surface of the buffer layer (13).

4. The GaN smart power chip with junction temperature monitoring capability according to claim 2, characterized in that: The lateral power device (4) comprises a source electrode (41), a drain electrode (42) and a gate electrode (43), wherein: The source electrode (41) is located on one side of the first portion of the P-type GaN layer (16) and above the two-dimensional electron gas channel; The drain electrode (42) is located on the other side of the first portion of the P-type GaN layer (16) and is located above the two-dimensional electron gas channel; The gate electrode (43) is arranged on the first portion of the P-type GaN layer (16).

5. The GaN smart power chip with junction temperature monitoring capability according to claim 2, characterized in that: The ohmic contact structure (5) comprises a first ohmic contact electrode (51) and a second ohmic contact electrode (52), wherein: The first ohmic contact electrode (51) and the second ohmic contact electrode (52) are both located above the two-dimensional electron gas channel; The first ohmic contact electrode (51) is used for grounding.

6. The GaN smart power chip with junction temperature monitoring capability according to claim 5, characterized in that: The temperature sensor diode (6) comprises a cathode (61) and an anode (62), wherein: The cathode (61) is arranged at intervals on one side of the second portion of the P-type GaN layer (17) and is located above the two-dimensional electron gas channel; The anode (62) is arranged on the surface of the barrier layer (15) on the other side of the second portion of the P-type GaN layer (17), and is in contact with the second portion of the P-type GaN layer (17); The cathode (61) is connected to the second ohmic contact electrode (52) via a metal interconnection line and is used to output voltage; the anode (62) is used to input power supply voltage.

7. The GaN smart power chip with junction temperature monitoring capability according to claim 6, characterized in that: It also includes a passivation layer (7), wherein: The passivation layer (7) covers the surface of the first isolation groove (2), the surface of the second isolation groove (3), the surface of the barrier layer (15), the surface of part of the first partial P-type GaN layer (16), and the surface of the second partial P-type GaN layer (17); The anode (62) overlaps the passivation layer (7).

8. A method for preparing a GaN smart power chip with junction temperature monitoring capability, characterized in that: Includes steps: S1. preparing a two-dimensional electron gas structure (1); S2, etching the two-dimensional electron gas structure (1) to below the two-dimensional electron gas channel to form a first isolation groove (2) and a second isolation groove (3), and isolating the two-dimensional electron gas structure (1) into a power device region, an ohmic contact resistance region, and a temperature sensor region that are sequentially arranged laterally; S3, depositing a passivation layer (7) on the surface of the two-dimensional electron gas structure (1), the surface of the first isolation groove (2), and the surface of the second isolation groove (3); S4, preparing a metal electrode above the two-dimensional electron gas channel of the two-dimensional electron gas structure (1), forming a lateral power device (4) arranged in the power device area, an ohmic contact structure (5) arranged in the ohmic contact resistance area, and a temperature sensor diode (6) arranged in the temperature sensor area; S5. cascade-connecting the temperature sensor diode (6) and the ohmic contact structure (5) using interconnecting metal wires.

9. The method for preparing a GaN smart power chip with junction temperature monitoring capability according to claim 8, characterized in that: Step S1 includes: S11, sequentially preparing a nucleation layer (12), a buffer layer (13), a channel layer (14), a barrier layer (15) and a P-type GaN layer on the cladding surface of the substrate (11), wherein a two-dimensional electron gas channel is formed between the channel layer (14) and the barrier layer (15); S12, etching the P-type GaN layer to form a first portion of the P-type GaN layer (16) and a second portion of the P-type GaN layer (17) that are spaced apart.

10. The method for preparing a GaN smart power chip with junction temperature monitoring capability according to claim 9, characterized in that: Step S4 includes: S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer (7), and etching the passivation layer (7) and the barrier layer (15) in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves extending to the surface of the channel layer (14); S42, depositing ohmic metal in the plurality of ohmic metal electrode grooves and performing annealing to form a cathode (61), a first ohmic contact electrode (51), a second ohmic contact electrode (52), a source electrode (41) and a drain electrode (42), wherein the cathode (61) is arranged in the temperature sensor region and is located on one side of the second portion of the P-type GaN layer (17), the first ohmic contact electrode (51) and the second ohmic contact electrode (52) are arranged at intervals in the ohmic contact resistance region, and the source electrode (41) and the drain electrode (42) are distributed in the power device region and are located on both sides of the first portion of the P-type GaN layer (16); S43, defining a gate region and an anode region on the surface of the passivation layer (7), etching the passivation layer (7) in the gate region to the first portion of the P-type GaN layer (16), and etching the passivation layer (7) in the anode region to the barrier layer (15), to form a gate groove and an anode groove; S44. Depositing Schottky metal in the gate groove and the anode groove to form a gate electrode (43) and an anode (62), wherein the gate electrode (43) is located in the power device region and on the first portion of the P-type GaN layer (16), and the anode (62) is in contact with the other side of the second portion of the P-type GaN layer (17) and overlaps the passivation layer (7).

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