A chip pin hanging detection circuit and detection method based on variable current

Abstract

The present invention provides a chip pin hanging detection circuit and detection method based on variable current, and the circuit part includes a timing circuit, a current source, a current mirror circuit, a switch circuit, a reference voltage source circuit, a comparator, a trigger and a logic function module. The present invention has good functional completeness. By connecting a resistor and a current source to the pin inside the chip, a specific potential difference (the potential difference in the hanging situation, i.e., the expected value) will be formed at both ends of the resistor under the action of the current source. If there is an external circuit on the pin, the actual potential difference at both ends of the resistor will deviate from the expected value under the influence of the external circuit. Whether the pin is hanging is judged based on whether the potential difference at both ends of the resistor has deviated. Considering the various situations that may exist in the load, it is necessary to change the size of the current source for two judgments to achieve the completeness of the detection function.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical components, and in particular to a chip pin hanging detection circuit and a detection method based on variable current. Background Art

[0002] In integrated circuit applications, in many cases, the circuit needs to be set according to the actual application scenario. For example, in power chip applications, different voltage protection and current protection need to be achieved through settings. This setting can often be achieved through external circuits. In some practical applications, in addition to external settings, some chips also have reserved function modules inside the chip. Usually, only one of the two can be selected.

[0003] In practical applications, it is possible to determine whether the chip uses external settings or internal settings by judging whether there is an external circuit; when there is an external circuit, use the external circuit for setting; when there is no external circuit, use the internal circuit for setting. The prerequisite for completing this function is to detect whether there is an external circuit function circuit connected to the chip, that is, to determine whether the chip pin is suspended. Suspended means there is no external circuit, and non-suspended means there is an external circuit.

[0004] In practical applications, non-suspended external circuits may have Figure 1a to 1c The three situations shown put forward requirements for the completeness of the detection circuit function.

[0005] Therefore, a detection circuit and a detection method are needed that can determine whether a chip pin is suspended and is adaptable to various external functional circuit conditions. Summary of the invention

[0006] The present invention is to solve the problem of whether the chip pin is connected to the external setting, and provides a chip pin floating detection circuit and detection method based on variable current. By connecting a resistor and a current source to the pin inside the chip, a specific potential difference (the potential difference in the floating situation, that is, the expected value) will be formed at both ends of the resistor under the action of the current source. If there is an external circuit on the pin, the actual potential difference across the resistor will deviate from the expected value due to the influence of the external circuit. Whether the pin is floating is judged based on whether the potential difference across the resistor deviates. Taking into account the various situations that may exist in the load, it is necessary to change the size of the current source for two judgments to achieve the completeness of the detection function.

[0007] The present invention provides a chip pin floating detection circuit based on variable current, comprising a switch circuit connected to a PIN pin, a first variable current source circuit or a second variable current source circuit connected to the switch circuit, an NMOS tube mirror circuit connected to a reference current source CurrentSource, a PMOS tube mirror circuit connected to a power supply voltage Vdd, a first reference voltage generating circuit, a second reference voltage generating circuit, a comparator U1 connected to the PIN pin in a positive phase and the first reference voltage generating circuit in an inverse phase, a comparator U2 connected to the second reference voltage generating circuit in a positive phase and the PIN pin in an inverse phase, and a timing circuit connected to the switch circuit, the first variable current source circuit or the second variable current source circuit;

[0008] The timing circuit outputs an enable signal according to the timing to control the connection and disconnection of the switch circuit, the reference current source CurrentSource provides a reference current I0, and the first reference voltage generating circuit generates a reference voltage Vdd-V R , the second reference voltage generating circuit generates a reference voltage V R , both the NMOS tube mirror circuit and the PMOS tube mirror circuit copy the reference current I0 to the branch in proportion;

[0009] The first variable current source circuit includes a resistor R1 and a PMOS tube variable current source, and the second variable current source circuit includes a resistor R1 and an NMOS tube variable current source. The first variable current source circuit and the second variable current source circuit can independently determine whether the PIN pin is suspended;

[0010] The PMOS tube variable current source and the NMOS tube variable current source generate a potential difference across the resistor R1 and compare the potential difference with Vdd-V through comparators U1 and U2. R and V R A comparison is performed to determine whether the PIN pin is floating.

[0011] The present invention discloses a variable current based chip pin floating detection circuit, as a preferred embodiment, the switch circuit includes an NMOS tube NM0, a third PMOS tube PM3, and a fourth NMOS tube NM4, the NMOS tube mirror circuit includes a first NMOS tube NM1, a second NMOS tube NM2, and a third NMOS tube NM3, the PMOS tube mirror circuit includes a first PMOS tube PM1 and a second PMOS tube PM2, the first reference voltage generating circuit includes a resistor R2, and the second reference voltage generating circuit includes a resistor R3;

[0012] The gate of NM0 inputs the EN_N signal, the source is grounded, and the drain is connected to the reference current source CurrentSource. The gates of NM1, NM2, and NM3 are all connected, the sources are all connected and then grounded. The drain of NM1 is connected to the gate and then connected to the reference current source CurrentSource. The drain of NM2 is connected to the drain and gate of PM1. The drain of NM3 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the sources of PM1 and PM2 and then connected to the power supply voltage Vdd. The gates of PM1 and PM2 are all connected, the sources are all connected and then connected to the power supply voltage Vdd. The drain of PM2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the sources of NM1, NM2, and NM3 and then grounded.

[0013] The non-inverting input terminal of the comparator U1 is connected to the PIN pin and the drain of NM4, and the inverting input terminal is connected between the resistor R2 and the drain of NM3; the non-inverting input terminal of the comparator U2 is connected between the drain of PM2 and the resistor R3, and the inverting input terminal is connected to the PIN pin and the drain of NM4.

[0014] In the variable current chip pin floating detection circuit described in the present invention, as a preferred embodiment, the resistance values ​​of the resistors R2 and R3 are the same, both being R, and the resistance value of the resistor R1 is R / 2;

[0015] It also includes a trigger U3 connected to the output end of the comparator U1, a trigger U4 connected to the output end of the comparator U2, a logic AND gate U5 connected to the output end of the trigger U3 and the output end of the trigger U4, an inverting circuit U6 connected to the EN signal output end, an inverting circuit U7 connected to the EN2 signal output end, and an inverting circuit U8 connected to the EN4 signal output end;

[0016] The reverse circuit U6 outputs an EN_N signal, the reverse circuit U7 outputs an EN2_N signal, and the reverse circuit U8 outputs an EN4_N signal;

[0017] The logic AND gate U5 infers whether the PIN pin is floating through the output results of the comparator U1 and the comparator U2.

[0018] The present invention describes a variable current based chip pin floating detection circuit, as a preferred embodiment, the timing circuit includes a delay module, EN is an input enable signal, EN1, EN2, EN3, EN4 are delayed signals respectively, EN_N signal is the inverted signal of EN signal, EN_2N signal is the inverted signal of EN2 signal, EN4_N signal is the inverted signal of EN4 signal.

[0019] The present invention discloses a chip pin floating detection circuit based on variable current. As a preferred embodiment, the PMOS tube variable current source includes a fourth PMOS tube PM4 and a fifth PMOS tube PM5, whose gate is connected to both the gates of PM1 and PM2, whose source is connected to both the source of PM1 and PM2 and then connected to the power supply voltage Vdd. The switch circuit also includes a sixth PMOS tube PM6, whose gate inputs an EN2_N signal, whose drain is connected to the drain of PM4 and then connected to the source of PM3, and whose source is connected to the drain of PM5;

[0020] One end of the resistor R1 is connected to the source of NM4, and the other end is connected to the sources of NM1, NM2, and NM3 and then grounded;

[0021] The CLK pin of the trigger U3 inputs the EN3 signal, and the trigger U3 saves the output result of the comparator U1 at time t3 and outputs OUT1; the CLK pin of the trigger U4 inputs the EN1 signal, and the trigger U4 saves the output result of the comparator U2 at time t1 and outputs OUT2.

[0022] The variable current chip pin floating detection circuit described in the present invention is preferably configured such that the currents flowing through NM1, NM2, and NM3 are I1, I2, and I3 respectively;

[0023] The channel width and length of NM1, NM2, and NM3 are the same, I1=I2=I3=I0;

[0024] The currents flowing through PM2, PM4, and PM5 are I7, I5, and I6 respectively. The channel width and length of PM1, PM2, and PM4 are the same, and the width-to-length ratio of PM5 is k times that of PM1:

[0025]

[0026] Then I5=I7=I2=I0, I6=k*I2=k*I0.

[0027] The present invention discloses a chip pin floating detection circuit based on variable current. As a preferred embodiment, the NMOS tube variable current source includes a fifth NMOS tube NM5 and a sixth NMOS tube NM6, whose gates are connected to the gates of NM1, NM2 and NM3, whose sources are connected to the sources of NM1, NM2 and NM3 and then grounded; the switch circuit also includes a seventh NMOS tube NM7, whose gate inputs an EN2 signal, whose drain is connected to the source of NM4 and the drain of NM5, and whose source is connected to the drain of NM6;

[0028] One end of the resistor R1 is connected to the source of PM1, the source of PM2, one end of the resistor R2 is connected to the power supply voltage Vdd, and the other end is connected to the source of PM3;

[0029] The CLK pin of the trigger U3 inputs the EN1 signal, and the trigger U3 saves the output result of the comparator U1 at time t1 and outputs OUT1; the CLK pin of the trigger U4 inputs the EN3 signal, and the trigger U4 saves the output result of the comparator U2 at time t3 and outputs OUT2.

[0030] The chip pin floating detection circuit based on variable current described in the present invention is preferably configured such that the currents flowing through NM1, NM2, NM3, NM5, and NM6 are I1, I2, I3, I8, and I9 respectively;

[0031] The channel width and length of NM1, NM2, NM3, and NM5 are the same, and the width-to-length ratio of NM6 is k times that of NM1:

[0032]

[0033] I1=I2=I3=I8=I0,, I9=k*I1=k*I0;

[0034] The channel width and length of PM1 and PM2 are the same, I7=I2=I0.

[0035] The present invention provides a detection method for a chip pin hanging detection circuit based on variable current, comprising the following steps:

[0036] At S1 and t0, the signal EN is at a low level, NM0 is turned on, and the circuit does not work;

[0037] At S2, t0~t1, the signal EN changes from low level to high level, NM0 is turned off, and the circuit starts to work; PM6 is turned off, and the voltage across R1 is V R / 2;

[0038] When PIN has no external pull-up circuit, the output of comparator U2 is high level; when PIN has an external pull-up circuit, the output of comparator U2 is low level;

[0039] At S3 and t1, the signal EN1 changes from low level to high level, and the trigger U4 latches the result to obtain OUT2;

[0040] At S4 and t2, EN2 is high, EN4 is low, PM3, NN4, and PM6 are turned on, and the first variable current source circuit increases the current in the path. The voltage across R1 is (k+1)*V R / 2 and make (k+2)*V R / 2≈Vdd;

[0041] S5, t2~t3 determine whether there is an external pull-down circuit on the PIN. When there is no external pull-down circuit on the PIN, the PIN voltage is approximately Vdd-V R / 2, the comparator U1 output is high level; when PIN has an external pull-down circuit, the comparator U1 output is low level;

[0042] At S6 and t3, EN3 is at a high level, the flip-flop U3 latches the result to obtain OUT1, and the logic AND gate U5 outputs the result Floating, which is used to determine whether OUT1 and OUT2 are both at a high level;

[0043] At S7 and t4, EN4 is at a high level, NM4 and PM3 are turned off, and the circuit channel is closed;

[0044] Floating is a high level, indicating that the pin of the chip under test is floating; Floating is a low level, indicating that the pin of the chip under test is not floating.

[0045] The present invention provides a detection method for a chip pin hanging detection circuit based on variable current, comprising the following steps:

[0046] At S1 and t0, the signal EN is at a low level, NM0 is turned on, and the circuit does not work;

[0047] At S2, t0~t1, the signal EN changes from low level to high level, NM0 is turned off, and the circuit starts to work; the signal EN2 is low level, NM7 is turned off, and the voltage across R1 is V R / 2;

[0048] When there is no external pull-down circuit on PIN, the PIN voltage is greater than Vdd-V R , the comparator U1 output is low level; when PIN has an external pull-down circuit, the PIN voltage is less than Vdd-V R , the comparator U1 output is high level;

[0049] At S3 and t1, the signal EN1 changes from low level to high level, and the trigger U3 latches the result to obtain OUT1;

[0050] At S4 and t2, EN2 is high, NM7 is turned on, the second variable current source circuit increases the current in the path, and the voltage across R1 is (k+1)*V R / 2 and make (k+2)*V R / 2≈Vdd;

[0051] S5, t2~t3 determine whether there is an external pull-up circuit on PIN. When there is no external pull-up circuit on PIN, the PIN voltage is less than V R , the comparator U2 output is high level; when PIN has an external pull-up circuit, the PIN voltage is greater than V R , the comparator U2 output is low level;

[0052] At S6 and t3, EN3 is at a high level, the flip-flop U4 latches the result to obtain OUT2, and the logic AND gate U5 outputs the result Floating, which is used to determine whether OUT1 and OUT2 are both at a high level;

[0053] Floating is high level, indicating that the pin of the chip under test is floating; Floating is low level, indicating that the pin of the chip under test is not floating;

[0054] At S7 and t4, EN4 is at a high level, NM4 and PM3 are turned off, and the circuit channel is closed.

[0055] The present invention provides a chip pin hanging detection circuit based on variable current, which can cover Figure 1a to 1c The circuit can detect all situations in the chip, and has good functional completeness. The principle of this circuit is: a resistor and a current source are connected to the pin inside the chip. Under the action of the current source, a specific potential difference (the potential difference in the suspended state, that is, the expected value) will be formed at both ends of the resistor. If there is an external circuit on the pin, the actual potential difference at both ends of the resistor will deviate from the expected value under the influence of the external circuit. Whether the potential difference at both ends of the resistor deviates is determined based on whether there is a deviation to determine whether the pin is suspended. Considering the various situations that may exist in the load, it is necessary to change the size of the current source for two judgments to achieve the completeness of the detection function. The circuit includes: a timing circuit, which is used to control each functional module to work in a certain time sequence; a current source, which provides a reference current; a current mirror circuit, which copies the reference current to other circuit branches in a certain proportional relationship; a switch circuit, which is used to control the conduction of each branch; a reference voltage source circuit, which provides a reference voltage for comparison; a comparator, which is used to compare the voltage in the circuit; a trigger, which is used for latching the circuit; and a logic function module, which performs logical judgment.

[0056] The present invention has the following advantages:

[0057] The present invention provides a chip pin hanging detection circuit based on variable current, which can cover Figure 1a to 1c The circuit can detect all situations in the chip and has good functional completeness. The principle of this circuit is: a resistor and a current source are connected to the pin inside the chip. Under the action of the current source, a specific potential difference (the potential difference in the floating situation, that is, the expected value) will be formed at both ends of the resistor. If there is an external circuit on the pin, the actual potential difference across the resistor will deviate from the expected value due to the influence of the external circuit. Whether the pin is floating is judged based on whether the potential difference across the resistor deviates. Taking into account the various possible situations of the load, it is necessary to change the size of the current source for two judgments to achieve the completeness of the detection function. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1a A is a circuit diagram of a non-suspended external circuit in the prior art;

[0059] Figure 1b Circuit diagram b of a non-suspended external circuit in the prior art;

[0060] Figure 1c The circuit diagram c is a circuit diagram of a non-suspended external circuit in the prior art;

[0061] Figure 2 A circuit diagram of a chip pin floating detection circuit embodiment 1 based on variable current;

[0062] Figure 3 A circuit diagram of a second embodiment of a chip pin floating detection circuit based on variable current;

[0063] Figure 4 The present invention is a flow chart of a detection method of a chip pin floating detection circuit based on variable current. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0065] Example 1

[0066] A chip pin hanging detection circuit and detection method based on variable current, the chip pin hanging detection circuit is as follows Figure 2 As shown, the description is as follows:

[0067] 1. The working flow diagram of the detection circuit is shown in Figure 4 .

[0068] 2. PIN is the chip pin to be tested.

[0069] 3. In the timing circuit, delay is the delay module, EN is the input enable signal, and EN1, EN2, EN3, and EN4 are the delayed signals respectively.

[0070] 4. Circuit Figure 2 In the process, t0~t1 determines whether there is an external pull-up circuit for PIN, the result is latched at t1, the current in the path is increased at t2, t2~t3 determines whether there is an external pull-down circuit for PIN, the result is latched at t3, and the circuit path is closed at t4.

[0071] 5. CurrentSource is the reference current source, and the current size of the current source is I0.

[0072] 6. Circuit Figure 2 In the circuit, NM1, NM2, and NM3 form a current mirror circuit, and the currents flowing through them are I1, I2, and I3 respectively. The channel width and length of NM1, NM2, and NM3 are the same, that is:

[0073]

[0074] Then I1=I2=I3=I0. PM1, PM2, PM4, and PM5 form a current mirror circuit. The channel width and length of PM1, PM2, and PM4 are the same, and the width-to-length ratio of PM5 is k times that of PM1, that is:

[0075]

[0076] Then I5=I7=I2=I0, I6=k*I2=k*I0.

[0077] 7. When the signal EN is low, NM0 is turned on and the circuit does not work. When the signal EN changes from low to high, NM0 is turned off and the circuit starts to work.

[0078] 8. Circuit Figure 2 In the circuit, NM4, PM3, and PM6 form a switch circuit. When EN2 is low, PM6 is turned off. When EN2 is high, PM6 is turned on. When EN4 is low, NM4 and PM3 are turned on. When EN4 is high, NM4 and PM3 are turned off.

[0079] 9. R2 and R3 are used in the reference voltage generation circuit, and the reference voltages provided are Vdd-V R and V R Take R2=R3=R, the voltage across R2 and R3 is equal, and the voltage across the resistor is V R =I0*R, choose a reasonable value for R so that V R About 200mV.

[0080] 10. Circuit Figure 2 In the example, R1 = R / 2, then when PM6 is turned off, the voltage across R1 is V R / 2, about 100mV. When PM6 is turned on, the voltage across R1 is (k+1)*V R / 2. Choose a suitable k so that (k+2)*V R / 2≈Vdd.

[0081] 11. Circuit Figure 2 In the example, U1 and U2 are comparators. The positive input of U2 is the reference voltage V R , the inverting input is the voltage value of PIN. When PIN has no external pull-up circuit, the PIN voltage is approximately V R / 2, the comparator U2 output is high level; when PIN has an external pull-up circuit, due to V R Only about 200mV, the value is small, and the PIN voltage is much larger than V R / 2, so it will also be greater than V R , the comparator U2 output is low level. The positive input of U1 is the voltage value of PIN, and the negative input is the reference voltage Vdd-V R When there is no external pull-down circuit on the PIN, the PIN voltage is approximately Vdd-V R / 2, the comparator U1 output is high level; when PIN has an external pull-down circuit, due to V R It is only about 200mV, which is a small value. The PIN voltage is much smaller than Vdd-V R / 2, so it will also be less than Vdd-V R , the comparator U1 output is low level.

[0082] 12. Circuit Figure 2 In the example, U3 and U4 are triggers used to store the comparison results. U4 stores the result of U2 at the rising edge of EN1 (at time t1) and outputs OUT2. U3 stores the result of U1 at the rising edge of EN3 (at time t3) and outputs OUT1.

[0083] 13. Circuit Figure 2 Among them, U6, U7, and U8 are inverting circuits, which are used to invert the signals EN, EN2, and EN4, and the outputs are EN_N, EN2_N, and EN4_N.

[0084] 14. U5 is a logic AND gate, and the output result Floating is used to determine whether OUT1 and OUT2 are both high. Floating is high, indicating that the pin of the chip under test is suspended, and Floating is low, indicating that the pin of the chip under test is not suspended.

[0085] Example 2

[0086] A chip pin hanging detection circuit and detection method based on variable current, the chip pin hanging detection circuit is as follows Figure 3 As shown, the description is as follows;

[0087] 1. The working flow diagram of the detection circuit is shown in Figure 4 .

[0088] 2. PIN is the chip pin to be tested.

[0089] 3. In the timing circuit, delay is the delay module, EN is the input enable signal, and EN1, EN2, EN3, and EN4 are the delayed signals respectively.

[0090] 4. Circuit Figure 3 In the process, t0~t1 determines whether there is an external pull-down circuit for PIN, the result is latched at t1, the current in the path is increased at t2, t2~t3 determines whether there is an external pull-up circuit for PIN, the result is latched at t3, and the circuit path is closed at t4.

[0091] 5. CurrentSource is the reference current source, and the current size of the current source is I0.

[0092] 6. Circuit Figure 3 In the figure, NM1, NM2, NM3, NM5, and NM6 form a current mirror circuit, and the currents flowing through them are I1, I2, I3, I8, and I9 respectively. The channel width and length of NM1, NM2, NM3, and NM5 are the same, and the width-to-length ratio of NM6 is k times that of NM1, that is:

[0093]

[0094] Then I1=I2=I3=I8=I0, I9=k*I1=k*I0. PM1 and PM2 form a current mirror circuit, and the channel width and length of PM1 and PM2 are the same, that is:

[0095]

[0096] Then I7=I2=I0.

[0097] 7. When the signal EN is low, NM0 is turned on and the circuit does not work. When the signal EN changes from low to high, NM0 is turned off and the circuit starts to work.

[0098] 8. Circuit Figure 3 In the circuit, NM4, NM7, and PM3 form a switch circuit. When EN2 is low, NM7 is turned off. When EN2 is high, NM7 is turned on. When EN4 is low, NM4 and PM3 are turned on. When EN4 is high, NM4 and PM3 are turned off.

[0099] 9. R2 and R3 are used in the reference voltage generation circuit, and the reference voltages provided are Vdd-V R and V R Take R2=R3=R, the voltage across R2 and R3 is equal, and the voltage across the resistor is V R =I0*R, choose a reasonable value for R so that V R About 200mV.

[0100] 10. Circuit Figure 3 In the example, R1=R / 2, then when NM7 is turned off, the voltage across R1 is V R / 2, about 100mV. When NM7 is turned on, the voltage across R1 is (k+1)*V R / 2. Choose a suitable k so that (k+2)*V R / 2≈Vdd.

[0101] 11. Circuit Figure 3In the figure, U1 and U2 are comparators. The positive input of U1 is the voltage value of PIN, and the negative input is the reference voltage Vdd-V R When there is no external pull-down circuit on the PIN, the PIN voltage is approximately Vdd-V R / 2, the comparator U1 output is high level; when PIN has an external pull-down circuit, due to V R It is only about 200mV, which is a small value. The PIN voltage is much smaller than Vdd-V R / 2, so it will also be less than Vdd-V R , the comparator U1 output is low level.

[0102] The positive input of U2 is the reference voltage V R , the inverting input is the voltage value of PIN. When PIN has no external pull-up circuit, the PIN voltage is approximately V R / 2, the comparator U2 output is high level; when PIN has an external pull-up circuit, due to V R Only about 200mV, the value is small, and the PIN voltage is much larger than V R / 2, so it will also be greater than V R , the comparator U2 output is low level.

[0103] 12. Circuit Figure 3 In the example, U3 and U4 are triggers used to store the comparison results. U3 stores the result of U1 at the rising edge of EN1 (at time t1) and outputs OUT1. U4 stores the result of U2 at the rising edge of EN3 (at time t3) and outputs OUT2.

[0104] 13. Circuit Figure 3 In the figure, U6 and U7 are inverting circuits, which are used to invert the signals EN and EN4, and the outputs are EN_N and EN4_N.

[0105] 14. U5 is a logic AND gate, and the output result Floating is used to determine whether OUT1 and OUT2 are both high. Floating is high, indicating that the pin of the chip under test is suspended, and Floating is low, indicating that the pin of the chip under test is not suspended.

[0106] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A chip pin hanging detection circuit based on variable current, characterized in that: It includes a switch circuit connected to a PIN pin, a first variable current source circuit or a second variable current source circuit connected to the switch circuit, an NMOS tube mirror circuit connected to a reference current source CurrentSource, a PMOS tube mirror circuit connected to a power supply voltage Vdd, a first reference voltage generating circuit, a second reference voltage generating circuit, a comparator U1 connected to the PIN pin in a positive phase and the first reference voltage generating circuit in an inverse phase, a comparator U2 connected to the second reference voltage generating circuit in a positive phase and the PIN pin in an inverse phase, and a timing circuit connected to the switch circuit, the first variable current source circuit or the second variable current source circuit; The timing circuit outputs an enable signal in a timing sequence to control the connection and disconnection of the switch circuit, the reference current source CurrentSource provides a reference current I0, and the first reference voltage generating circuit generates a reference voltage Vdd-V R , the second reference voltage generating circuit generates a reference voltage V R , the NMOS tube mirror circuit and the PMOS tube mirror circuit both copy the reference current I0 to the branch in proportion; The first variable current source circuit includes a resistor R1 and a PMOS tube variable current source, and the second variable current source circuit includes a resistor R1 and an NMOS tube variable current source. The first variable current source circuit and the second variable current source circuit can independently determine whether the PIN pin is suspended; The PMOS variable current source and the NMOS variable current source generate a potential difference at both ends of the resistor R1 and compare the potential difference with Vdd-V through the comparator U1 and the comparator U2. R and V R Compare to determine whether the PIN pin is floating; The switch circuit includes an NMOS transistor NM0, a third PMOS transistor PM3, and a fourth NMOS transistor NM4; the NMOS transistor mirror circuit includes a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3; the PMOS transistor mirror circuit includes a first PMOS transistor PM1 and a second PMOS transistor PM2; the first reference voltage generating circuit includes a resistor R2; and the second reference voltage generating circuit includes a resistor R3; The gate of NM0 inputs the EN_N signal, the source is grounded, and the drain is connected to the reference current source CurrentSource. The gates of NM1, NM2, and NM3 are all connected, the sources are all connected and then grounded. The drain of NM1 is connected to the gate and then connected to the reference current source CurrentSource. The drain of NM2 is connected to the drain and gate of PM1. The drain of NM3 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the sources of PM1 and PM2 and then connected to the power supply voltage Vdd. The gates of PM1 and PM2 are all connected, the sources are all connected and then connected to the power supply voltage Vdd. The drain of PM2 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the sources of NM1, NM2, and NM3 and then grounded. The non-inverting input terminal of the comparator U1 is connected to the PIN pin and the drain of NM4, and the inverting input terminal is connected between the resistor R2 and the drain of NM3; the non-inverting input terminal of the comparator U2 is connected between the drain of PM2 and the resistor R3, and the inverting input terminal is connected to the PIN pin and the drain of NM4; The resistance values ​​of resistors R2 and R3 are the same, both R, and the resistance value of resistor R1 is R / 2; It also includes a trigger U3 connected to the output end of the comparator U1, a trigger U4 connected to the output end of the comparator U2, a logic AND gate U5 connected to the output end of the trigger U3 and the output end of the trigger U4, an inverting circuit U6 connected to the EN signal output end, an inverting circuit U7 connected to the EN2 signal output end, and an inverting circuit U8 connected to the EN4 signal output end; The reverse circuit U6 outputs an EN_N signal, the reverse circuit U7 outputs an EN2_N signal, and the reverse circuit U8 outputs an EN4_N signal; The logic AND gate U5 infers whether the PIN pin is floating through the output results of the comparator U1 and the comparator U2; The timing circuit includes a delay module, EN is an input enable signal, EN1, EN2, EN3, and EN4 are delayed signals respectively, EN_N signal is an inverted signal of the EN signal, EN_2N signal is an inverted signal of the EN2 signal, and EN4_N signal is an inverted signal of the EN4 signal.

2. The chip pin hanging detection circuit based on variable current according to claim 1, characterized in that: The PMOS tube variable current source includes a fourth PMOS tube PM4 and a fifth PMOS tube PM5, whose gate is connected to both the gates of PM1 and PM2, whose source is connected to both the source of PM1 and PM2 and then connected to the power supply voltage Vdd, and the switch circuit also includes a sixth PMOS tube PM6, whose gate inputs an EN2_N signal, whose drain is connected to the drain of PM4 and then connected to the source of PM3, and whose source is connected to the drain of PM5; One end of the resistor R1 is connected to the source of NM4, and the other end is connected to the sources of NM1, NM2, and NM3 and then grounded; The CLK pin of the trigger U3 inputs the EN3 signal, and the trigger U3 saves the output result of the comparator U1 at time t3 and outputs OUT1; the CLK pin of the trigger U4 inputs the EN1 signal, and the trigger U4 saves the output result of the comparator U2 at time t1 and outputs OUT2.

3. The chip pin hanging detection circuit based on variable current according to claim 2, characterized in that: The currents flowing through NM1, NM2, and NM3 are I1, I2, and I3 respectively; The channel width and length of NM1, NM2, and NM3 are the same, I1=I2=I3=I0; The currents flowing through PM2, PM4, and PM5 are I7, I5, and I6 respectively. The channel width and length of PM1, PM2, and PM4 are the same, and the width-to-length ratio of PM5 is k times that of PM1: Then I5=I7=I2=I0, I6=k*I2=k*I0.

4. The chip pin floating detection circuit based on variable current according to claim 1, characterized in that: The NMOS variable current source includes a fifth NMOS tube NM5 and a sixth NMOS tube NM6, whose gates are connected to the gates of NM1, NM2 and NM3, whose sources are connected to the sources of NM1, NM2 and NM3 and then grounded; the switch circuit also includes a seventh NMOS tube NM7, whose gate inputs an EN2 signal, whose drain is connected to the source of NM4 and the drain of NM5, and whose source is connected to the drain of NM6; One end of the resistor R1 is connected to the source of PM1, the source of PM2, one end of the resistor R2 is connected to the power supply voltage Vdd, and the other end is connected to the source of PM3; The CLK pin of the trigger U3 inputs the EN1 signal, and the trigger U3 saves the output result of the comparator U1 at time t1 and outputs OUT1; the CLK pin of the trigger U4 inputs the EN3 signal, and the trigger U4 saves the output result of the comparator U2 at time t3 and outputs OUT2.

5. The chip pin floating detection circuit based on variable current according to claim 4, characterized in that: The currents flowing through NM1, NM2, NM3, NM5, and NM6 are I1, I2, I3, I8, and I9 respectively; The channel width and length of NM1, NM2, NM3, and NM5 are the same, and the width-to-length ratio of NM6 is k times that of NM1: I1=I2=I3=I8=I0, I9=k*I1=k*I0; The channel width and length of PM1 and PM2 are the same, I7=I2=I0.

6. The detection method of a chip pin hanging detection circuit based on variable current according to claim 3, characterized in that: The following steps are involved: At S1 and t0, the signal EN is at a low level, NM0 is turned on, and the circuit does not work; At S2, t0~t1, the signal EN changes from low level to high level, NM0 is turned off, and the circuit starts to work; PM6 is turned off, and the voltage across R1 is V R / 2; When PIN has no external pull-up circuit, the output of comparator U2 is high level; when PIN has an external pull-up circuit, the output of comparator U2 is low level; At S3 and t1, the signal EN1 changes from low level to high level, and the trigger U4 latches the result to obtain OUT2; At S4 and t2, EN2 is high, EN4 is low, PM3, NN4, and PM6 are turned on, and the first variable current source circuit increases the current in the path. The voltage across R1 is (k+1)*V R / 2 and make (k+2)*V R / 2≈Vdd; S5, t2~t3 determine whether there is an external pull-down circuit on the PIN. When there is no external pull-down circuit on the PIN, the PIN voltage is approximately Vdd-V R / 2, the comparator U1 output is high level; when PIN has an external pull-down circuit, the comparator U1 output is low level; At S6 and t3, EN3 is at a high level, the flip-flop U3 latches the result to obtain OUT1, and the logic AND gate U5 outputs the result Floating, which is used to determine whether OUT1 and OUT2 are both at a high level; Floating is high level, indicating that the pin of the chip under test is floating; Floating is low level, indicating that the pin of the chip under test is not floating; At S7 and t4, EN4 is at a high level, NM4 and PM3 are turned off, and the circuit channel is closed.

7. The detection method of a chip pin hanging detection circuit based on variable current according to claim 6, characterized in that: The following steps are involved: At S1 and t0, the signal EN is at a low level, NM0 is turned on, and the circuit does not work; At S2, t0~t1, the signal EN changes from low level to high level, NM0 is turned off, and the circuit starts to work; the signal EN2 is low level, NM7 is turned off, and the voltage across R1 is V R / 2; When there is no external pull-down circuit on PIN, the PIN voltage is greater than Vdd-V R , the comparator U1 output is low level; when PIN has an external pull-down circuit, the PIN voltage is less than Vdd-V R , the comparator U1 output is high level; At S3 and t1, the signal EN1 changes from low level to high level, and the trigger U3 latches the result to obtain OUT1; At S4 and t2, EN2 is at a high level, NM7 is turned on, and the second variable current source circuit increases the current in the path, and the voltage across R1 is (k+1)*V R / 2 and make (k+2)*V R / 2≈Vdd; S5, t2~t3 determine whether there is an external pull-up circuit on PIN. When there is no external pull-up circuit on PIN, the PIN voltage is less than V R , the comparator U2 output is high level; when PIN has an external pull-up circuit, the PIN voltage is greater than V R , the comparator U2 output is low level; At S6 and t3, EN3 is at a high level, the flip-flop U4 latches the result to obtain OUT2, and the logic AND gate U5 outputs the result Floating, which is used to determine whether OUT1 and OUT2 are both at a high level; At S7 and t4, EN4 is at a high level, NM4 and PM3 are turned off, and the circuit channel is closed; Floating is a high level, indicating that the pin of the chip under test is floating; Floating is a low level, indicating that the pin of the chip under test is not floating.

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