Chip testing method, system and storage medium

Abstract

The present application provides a chip testing method, system and storage medium, in which an electronic device calculates the power consumption corresponding to a target chip when the junction temperature of the ambient temperature reaches a target temperature and sends the power consumption to a test machine, so that the test machine tests a first chip in the target chip and reaches a first time of an over-temperature protection temperature at the power consumption; then, the electronic device receives the first time sent by the test machine, calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time, and sends the second time to the test machine, so that the test machine controls a second chip in the target chip and tests the target performance of the second chip at the power consumption and after the second time, thereby realizing high temperature testing, and no additional heating equipment is required during the test process, thereby reducing resource waste and testing costs.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a chip testing method, system and storage medium. Background Art

[0002] High temperature testing is necessary in chip testing, which helps to evaluate the performance and reliability of chips in high temperature environments and improve product quality and reliability. Usually, high temperature testing is performed during the final test (FT).

[0003] The current high temperature testing method is to raise the air temperature around the chip to a certain value, so that the internal junction temperature of the chip reaches a high temperature state.

[0004] However, these high-temperature testing methods usually require additional heating equipment, increasing resource consumption and testing costs. Summary of the invention

[0005] The present application provides a chip testing method, system and storage medium to reduce resource consumption and testing costs during high temperature testing.

[0006] In a first aspect, the present application provides a chip testing method, the method being used in an electronic device, the method comprising:

[0007] Calculate the power consumption of the target chip when the junction temperature reaches the target temperature under the ambient temperature;

[0008] Sending the power consumption to a test machine, so that the test machine tests a first chip in the target chip and reaches a first time of an over-temperature protection temperature under the power consumption;

[0009] receiving a first time sent by the test machine, and calculating a second time to reach the target temperature according to the over-temperature protection temperature and the first time;

[0010] The second time is sent to the test machine, so that the test machine controls the second chip in the target chip to test the target performance of the second chip under the power consumption and after the second time.

[0011] In some embodiments, sending the power consumption to a test machine so that the test machine tests the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption specifically includes:

[0012] Calculating a corresponding test voltage according to the power consumption and the preset driving current;

[0013] The preset driving current and the corresponding test voltage are sent to a test machine, so that the test machine tests a first chip in the target chip and reaches a first time of over-temperature protection temperature under the preset driving current and the corresponding test voltage.

[0014] In some embodiments, sending the power consumption to a test machine so that the test machine tests a first chip in the target chip and reaches a first time of an over-temperature protection temperature under the power consumption specifically includes:

[0015] Finding multiple driving currents of the target chip, and calculating a test voltage corresponding to each driving current according to the power consumption and the multiple driving currents;

[0016] Sending each driving current and the corresponding test voltage to the test machine, so that the test machine tests the first chip in the target chip and reaches the first time of the over-temperature protection temperature under each driving current and the corresponding test voltage;

[0017] The receiving the first time sent by the test machine, and calculating the second time to reach the target temperature according to the over-temperature protection temperature and the first time, specifically includes:

[0018] receiving each first time sent by the test machine, and calculating each second time for reaching the target temperature according to the over-temperature protection temperature and each first time;

[0019] The sending the second time to the test machine specifically includes:

[0020] A second time is selected from a plurality of second times and sent to the test machine.

[0021] In some embodiments, sending the preset driving current and the corresponding test voltage to a test machine specifically includes:

[0022] Generate a test program including the preset driving current and the corresponding test voltage, and send the test program to a test machine;

[0023] sending the second time to the testing machine;

[0024] The test program is modified according to the second time, and the modified test program is sent to the test machine.

[0025] In some embodiments, the calculating the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature specifically includes:

[0026] Preset target temperature and obtain ambient temperature;

[0027] Calculating a difference between the target temperature and the ambient temperature;

[0028] The ratio between the difference and the thermal resistance between the chip junction and the environment is calculated to obtain the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature.

[0029] In a second aspect, the present application provides a chip testing method, the method being used for testing a machine, the method comprising:

[0030] receiving power consumption sent by an electronic device, where the power consumption is power consumption corresponding to when the junction temperature of a target chip reaches a target temperature under an ambient temperature calculated by the electronic device;

[0031] Testing the first time when a first chip in the target chips reaches the over-temperature protection temperature under the power consumption;

[0032] sending the first time to the electronic device, so that the electronic device calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time;

[0033] The second time is received, a second chip in the target chip is controlled to operate at the power consumption and after the second time, a target performance of the second chip is tested.

[0034] In some embodiments, the receiving power consumption sent by the electronic device specifically includes:

[0035] Receiving a preset driving current and a corresponding test voltage sent by an electronic device, wherein the test voltage corresponding to the preset driving current is calculated based on the power consumption;

[0036] The first time when the first chip in the test target chip reaches the over-temperature protection temperature under the power consumption specifically includes:

[0037] A first time at which a first chip in the target chips reaches an over-temperature protection temperature under the preset driving current and the corresponding test voltage is tested.

[0038] In some embodiments, the receiving power consumption sent by the electronic device specifically includes:

[0039] Receiving a plurality of driving currents and corresponding test voltages sent by an electronic device, wherein the test voltage corresponding to each driving current is calculated based on the power consumption;

[0040] The first time when the first chip in the test target chip reaches the over-temperature protection temperature under the power consumption specifically includes:

[0041] Testing the first time when a first chip in the target chips reaches an over-temperature protection temperature under each driving current and corresponding test voltage;

[0042] The sending the first time to the electronic device so that the electronic device calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time specifically includes:

[0043] Each first time is sent to the electronic device, so that the electronic device calculates each second time to reach the target temperature according to the over-temperature protection temperature and each first time, and selects one second time from multiple second times and sends it to the test machine.

[0044] In some embodiments, the receiving of the preset driving current and the corresponding test voltage sent by the electronic device specifically includes:

[0045] Receiving a test program sent by an electronic device, wherein the test program includes a preset driving current and a corresponding test voltage;

[0046] The first time when the first chip in the test target chip reaches the over-temperature protection temperature under the power consumption specifically includes:

[0047] Run the test program to test the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption;

[0048] The receiving the second time, controlling the second chip in the target chip to test the target performance of the second chip at the power consumption and after the second time, specifically includes:

[0049] The modified test program is received, the modified test program is run, and a second chip in the target chip is controlled to test a target performance of the second chip at the power consumption and after the second time.

[0050] In a third aspect, the present application provides a chip testing device, comprising:

[0051] The first calculation module is used to calculate the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature;

[0052] A first sending module, used for sending the power consumption to a test machine, so that the test machine tests a first chip in the target chip and reaches a first time of an over-temperature protection temperature under the power consumption;

[0053] A second calculation module, configured to receive the first time sent by the test machine, and calculate a second time to reach the target temperature according to the over-temperature protection temperature and the first time;

[0054] The second sending module is used to send the second time to the test machine, so that the test machine controls the second chip in the target chip to test the target performance of the second chip under the power consumption and after the second time.

[0055] In a fourth aspect, the present application provides a chip testing device, comprising:

[0056] A first receiving module, used to receive power consumption sent by an electronic device, where the power consumption is the power consumption corresponding to when the junction temperature of a target chip reaches a target temperature under an ambient temperature calculated by the electronic device;

[0057] A first test module, used for testing the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption;

[0058] A second receiving module, used for sending the first time to the electronic device, so that the electronic device calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time;

[0059] The second test module is used to receive the second time, control the second chip in the target chip to test the target performance of the second chip under the power consumption and after the second time.

[0060] In a fifth aspect, the present application provides an electronic device, including: a memory and a processor;

[0061] The memory is used to store instructions; the processor is used to call the instructions in the memory to execute the method in the first aspect and any possible design of the first aspect.

[0062] In a sixth aspect, the present application provides an electronic device, including: a memory and a processor;

[0063] The memory is used to store instructions; the processor is used to call the instructions in the memory to execute the method in the second aspect and any possible design of the second aspect.

[0064] In a seventh aspect, the present application provides a computer-readable storage medium, in which computer instructions are stored. When at least one processor of an electronic device executes the computer instructions, the electronic device executes the above method.

[0065] In an eighth aspect, the present application provides a computer program product, which includes computer instructions. When at least one processor of an electronic device executes the computer instructions, the electronic device executes the above method.

[0066] The chip testing method, system and storage medium provided by the present application, the electronic device calculates the corresponding power consumption of the target chip when the junction temperature of the ambient temperature reaches the target temperature and sends the power consumption to the test machine, so that the test machine tests the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption; then, the electronic device receives the first time sent by the test machine, calculates the second time to reach the target temperature according to the over-temperature protection temperature and the first time, and sends the second time to the test machine, so that the test machine controls the second chip in the target chip, and tests the target performance of the second chip under the power consumption and after the second time, thereby realizing high temperature testing, and no additional heating equipment is required during the test process, reducing resource waste and testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] Figure 1 A schematic diagram of a chip testing method provided in one embodiment of the present application;

[0069] Figure 2 A schematic diagram of a chip testing method provided in another embodiment of the present application;

[0070] Figure 3 A schematic diagram of the structure of a chip testing system provided in one embodiment of the present application;

[0071] Figure 4 A test schematic diagram provided for an embodiment of the present application;

[0072] Figure 5 A test schematic diagram provided for another embodiment of the present application;

[0073] Figure 6 A schematic diagram of a chip testing method provided in another embodiment of the present application;

[0074] Figure 7 A temperature-time curve diagram provided for an embodiment of the present application;

[0075] Figure 8 A schematic diagram of a chip testing method provided in yet another embodiment of the present application;

[0076] Fig. 9 A schematic diagram of the structure of a chip testing device provided in one embodiment of the present application;

[0077] Fig.10 A schematic diagram of the structure of a chip testing device provided in another embodiment of the present application;

[0078] Fig.11 A schematic diagram of the hardware structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0080] Chip testing is an important part of the chip manufacturing process. It is often necessary to perform chip testing under high temperature conditions for the following reasons:

[0081] 1. Impact of temperature on chip performance: In actual applications, chips may encounter high temperature environments, which may have a negative impact on the performance and reliability of the chip, such as causing changes in the chip's electrical performance, increased power consumption, decreased signal integrity, and even leading to power failures or thermal failures.

[0082] 2. Product reliability requirements: Many application fields have high requirements for chip reliability and need to be able to work normally in a wide temperature range. Therefore, high temperature testing can simulate the working conditions of the chip under high temperature conditions and evaluate its stability and reliability in high temperature environments.

[0083] 3. Design verification and process improvement: High temperature testing can also be used to verify the effectiveness of chip design and process. By testing the chip under high temperature conditions, the robustness of the design and the stability of the process can be evaluated to find potential problems and make improvements.

[0084] In summary, high temperature testing is necessary in chip testing, which helps to evaluate the performance and reliability of chips in high temperature environments and improve product quality and credibility.

[0085] Usually, high temperature testing is performed during the final test (FT). The final test is the last interception before the chip leaves the factory. The test object is the packaged chip. The methods for high temperature testing during the final test are mainly the following heating methods:

[0086] 1. Hot plate method: This method places the chip on a hot plate and heats the hot plate to increase the temperature of the chip. The hot plate method can provide uniform temperature distribution, but for high-power chips, additional cooling measures may be required to prevent heating.

[0087] 2. Thermal air flow method: This method uses thermal air flow to heat the chip. The chip is placed in a thermal air flow and the temperature of the chip is controlled by adjusting the temperature and flow rate of the thermal air flow. The thermal air flow method can provide faster temperature changes, but may produce uneven temperature distribution, affecting the test accuracy.

[0088] 3. Hot plate and hot air flow combination method: This method combines the characteristics of the hot plate method and the hot air flow method, and heats the chip by using the hot plate and hot air flow at the same time. This method can speed up the temperature change while providing uniform temperature distribution, but it will increase the test cost.

[0089] Therefore, the usual high-temperature testing method is to increase the air temperature around the chip to a certain value so that the internal junction temperature of the chip reaches a high temperature state, but these high-temperature testing methods usually require additional heating equipment, increasing resource consumption and testing costs.

[0090] In response to the above problems, the present application proposes a chip testing method, in which the electronic device calculates the power consumption corresponding to the chip when the chip reaches the target temperature according to the chip junction temperature calculation formula, and sends the power consumption to the test machine, so that the test machine tests the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption. After receiving the first time, the electronic device calculates the second time to reach the target temperature and sends it to the test machine, so that the test machine controls the second chip in the target chip to act under the power consumption for the second time, and then tests the target performance of the second chip, thereby completing the high temperature test, and no additional heating equipment is required, reducing resource consumption and testing costs.

[0091] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0092] Figure 1 FIG. 1 is a flow chart of a chip testing method provided by an embodiment of the present application. Figure 1 As shown, with an electronic device (such as a computer device, a terminal, etc.) as the execution subject, the method of this embodiment may include the following steps:

[0093] S101 , calculating the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature.

[0094] In practical applications, the target chip can be a voltage or current driven chip (for example, a backlight driver chip), and the process standard selected by the chip can withstand high voltage and high current, that is, it can continue to work under high voltage and high current conditions, and it is still within the normal range guaranteed by the chip design, and will not cause electrical stress and thermal stress damage that will shorten the life of the chip or reduce performance, and will not damage the yield. In addition, the chip can have an over-temperature protection function to prevent the chip from being damaged by overheating. For example, the current drive pin of the target chip can withstand a maximum voltage of tens of volts (such as 40V), and the output current value of the pin can reach tens of milliamperes (such as 64mA).

[0095] In some embodiments, a target temperature is preset and the ambient temperature is obtained, and then the difference between the target temperature and the ambient temperature is calculated, and the ratio of the difference to the thermal resistance between the chip junction and the environment is calculated to obtain the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature.

[0096] Specifically, the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature is calculated according to the chip junction temperature calculation formula, wherein the chip junction temperature calculation formula is:

[0097] TJ = TA + (RTA * PD);

[0098] TJ is the junction temperature. The junction temperature (TJ) is the actual operating temperature of the switch MOS tube and other devices in the chip. The chip includes a variety of tiny components made of a bunch of materials, including tiny MOS, diodes, integrated resistors, capacitors, etc. These components will also generate heat when current passes through them. Especially in the application of some power chips with excessive current, the junction temperature becomes a parameter that must be considered. The junction temperature is directly related to the power consumption of the chip.

[0099] TA is the air temperature around the chip;

[0100] RJA is the thermal resistance from junction to ambient, which can be obtained from the data sheet;

[0101] PD is the chip power consumption, where the chip power consumption may be equal to the product of the voltage V and the current I (PD=V*I), so that the voltage and / or current may be calculated based on the chip power consumption later.

[0102] In actual applications, high temperature testing is performed during the final test process, and the selected temperature can be 85°C or 125°C and other temperature levels. Usually, the probes and fixtures used in general final test machines can withstand a high temperature of 85°C. Accordingly, the target temperature can be 85°C, 100°C, 125°C, etc., which can be determined according to actual conditions.

[0103] For example, the goal is to increase the junction temperature to 85°C, that is, the target temperature is 85°C, and the ambient temperature is known to be 25°C. After checking the chip data sheet, the thermal resistance from the chip node to the environment is 80.6°C / W. The chip junction temperature calculation formula can be used to calculate that the chip power consumption is approximately 0.74W.

[0104] S102 , sending the power consumption to a test machine, so that the test machine tests a first chip in the target chips and determines the first time when the over-temperature protection temperature is reached under the power consumption.

[0105] The applicant considers that there is a certain gap between the actual mass production test process and the ideal environment, and the internal temperature of the chip will be affected by the actual test environment, such as the contact of the test machine probe and the test fixture. The thermal resistance coefficient from the environment to the inside of the chip is relatively complex, and it is not a single heat conduction path from air to the chip. Since the time required to reach thermal equilibrium cannot be determined, there are some errors in calculating the internal temperature (junction temperature) of the chip according to the power consumption and air temperature under the above ideal conditions. Although it is possible to collect test data after a long enough time to ensure that the internal temperature of the chip reaches a stable temperature, a large number of chips need to be tested in the final test stage. If it takes a long time for the internal temperature of the chip to reach a stable temperature, it may take longer.

[0106] The applicant has found through research that the power consumption of the chip is proportional to the time required to reach a stable junction temperature under the power consumption. That is, under a fixed power consumption and environmental conditions, T1 / t1=T2 / t2, where t1 is the time taken for the junction temperature to reach T1°C (first time), and t2 is the time taken for the junction temperature to reach T2°C (second time). And considering the actual mass production test environment, the test can more accurately test the time required to reach over-temperature protection under a certain power consumption condition.

[0107] Therefore, in this step, the power consumption obtained in step 1 is sent to the test machine, and the test machine tests the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption and sends it to the electronic device, so that the electronic device can subsequently use the characteristic of T1 / t1=T2 / t2 to determine the test data collection time, thereby reducing the test time. It should be noted that the first chip is a small part of the target chip.

[0108] For example, the current driver chip is equipped with an over-temperature protection function, and the temperature that triggers the over-temperature protection is 150°C. When the chip works under a certain power consumption condition, the channel continues to output current. After a period of time t1, the temperature inside the chip reaches 150°C, and the over-temperature protection function will automatically shut down the chip action, and the current output is 0. The t1 time can be obtained by testing the pin output current.

[0109] S103, receiving the first time sent by the test machine, and calculating the second time to reach the target temperature according to the over-temperature protection temperature and the first time.

[0110] In this step, after the electronic device receives the first time t1 sent by the test machine, it can calculate the second time t2 to reach the target temperature T2 by T1 / t1=T2 / t2 and the over-temperature protection temperature T1, and then send the second time to the test machine.

[0111] S104, sending the second time to the test machine, so that the test machine controls the second chip in the target chip to test the target performance of the second chip under the power consumption and after the second time.

[0112] In this step, the electronic device sends the second time to the test machine, so that the test machine controls the second chip in the target chip to collect data of the second chip after the second time under the power consumption in step 1 to test the corresponding performance. For example, if it is necessary to test whether high temperature affects the electrical performance of the chip, parameters such as resistance and capacitance can be collected after the second time. If it is necessary to test whether high temperature affects the thermal performance of the chip, thermal conductivity, thermal diffusion coefficient, etc. can be collected after the second time. Among them, the second chip is other chips in the target chip except the first chip, and the number of the second chips is greater than the number of the first chips, which are most of the chips in the target chip.

[0113] The chip testing method provided in the present application is that the electronic device calculates the power consumption corresponding to the chip when the chip reaches the target temperature according to the chip junction temperature calculation formula, and sends the power consumption to the test machine, so that the test machine tests the first chip, and when the over-temperature protection temperature is reached at the first time under the power consumption, the electronic device calculates the second time to reach the target temperature after receiving the first time and sends it to the test machine, so that the test machine controls the second chip after the above power consumption acts for the second time, and tests the target performance of the second chip, thereby completing the high temperature test, and no additional heating equipment is required, reducing resource consumption and testing costs.

[0114] Figure 2 A chip testing method provided in an embodiment of the present application is as follows: Figure 2 As shown, the chip testing method provided in this embodiment includes:

[0115] S201. Calculate the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature according to the chip junction temperature calculation formula.

[0116] Among them, step S201 and Figure 1 The implementation of step S101 in the embodiment is similar and will not be repeated here in this embodiment.

[0117] S202: Calculate a corresponding test voltage according to power consumption and a preset drive current.

[0118] Here, PD=V*I, so after the power consumption is obtained according to step S101, the test voltage corresponding to the preset driving current can be calculated.

[0119] In practical applications, the chip data sheet can be used to determine that the chip pin has different drive current levels, and the preset drive current can be a drive current of any level, such as 64 mA.

[0120] In some embodiments, the corresponding preset driving current may also be calculated according to the power consumption and the output voltage of the chip.

[0121] S203, sending the preset driving current and the corresponding test voltage to the test machine, so that the test machine tests the first chip in the target chips and reaches the first time of the over-temperature protection temperature under the preset driving current and the corresponding test voltage.

[0122] In this step, the electronic device sends the preset driving current and the corresponding test voltage to the test machine, and the test machine controls the first chip to reach the over-temperature protection temperature under the preset driving current and the corresponding test voltage, and obtains the first time when the over-temperature protection temperature is reached. For example, the time when the preset driving current and the corresponding test voltage are applied to the first chip until the current output is 0 is obtained.

[0123] In some embodiments, after obtaining the preset driving current and the corresponding test voltage, a test program including the preset driving current and the corresponding test voltage may be generated, and the test program may be sent to a test machine, such as Figure 3 As shown, after receiving the test program, the test machine applies a preset drive current and a corresponding test voltage to the first chip to obtain the first time when the first chip reaches the over-temperature protection temperature under the preset drive current and the corresponding test voltage, such as Figure 4 shown.

[0124] In other embodiments, after obtaining the preset driving current and the corresponding test voltage, the test voltage can be sent to the test machine so that the test machine sets the test voltage. The electronic device can also generate a test program including the preset driving current and send it to the test machine so that the test machine applies the preset driving current to the first chip after receiving the test program, thereby applying the preset driving current and the corresponding test voltage to the first chip to obtain the first time when the first chip reaches the over-temperature protection temperature under the preset driving current and the corresponding test voltage.

[0125] S204, receiving the first time sent by the test machine, and calculating the second time to reach the target temperature according to the over-temperature protection temperature and the first time.

[0126] For example, under the conditions of voltage = 8V and current = 64mA, the time taken to trigger the 150°C temperature protection is 350ms, and the time taken for the chip to rise 1°C is about 2.3ms. It can be calculated that the time required for the chip temperature to reach 85°C is about 198ms.

[0127] S205 , sending the second time to the test machine, so that the test machine controls the second chip in the target chip to test the target performance of the second chip under the power consumption and after the second time.

[0128] In some embodiments, if the preset driving current is sent to the test machine through the test program, after obtaining the second time, the test program can be modified and the modified test program can be sent to the test machine, so that the test machine controls the second chip in the target chip to test the target performance of the second chip after the second time under power consumption. For example, the length of the test program can be modified according to the second time, such as Figure 5 As shown, the execution time of the test program increases by the second time.

[0129] The chip testing method provided in this embodiment calculates the corresponding test voltage based on the power consumption and the preset driving current, and sends the preset driving current and the corresponding test voltage to the testing machine, so that the testing machine tests the first chip and reaches the over-temperature protection temperature for the first time under the preset driving current and the corresponding test voltage.

[0130] Figure 6 A chip testing method provided in an embodiment of the present application is as follows: Figure 6 As shown, the chip testing method provided in this embodiment includes:

[0131] S301 . Calculate the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature according to the chip junction temperature calculation formula.

[0132] Among them, step S301 and Figure 1 The implementation of step S101 in the embodiment is similar and will not be repeated here in this embodiment.

[0133] S302 , searching for multiple driving currents of the target chip, and calculating a test voltage corresponding to each driving current according to the power consumption and the multiple driving currents.

[0134] Specifically, multiple driving currents of the target chip can be found in the chip data sheet, and the test voltage corresponding to each driving current can be calculated according to the power consumption.

[0135] S303, sending each driving current and the corresponding test voltage to a test machine, so that the test machine tests the first chip in the target chips and reaches the first time of the over-temperature protection temperature under each driving current and the corresponding test voltage.

[0136] S304, receiving each first time sent by the test machine, and calculating each second time to reach the target temperature according to the over-temperature protection temperature and each first time.

[0137] In some embodiments, when testing multiple driving currents and corresponding test voltages, multiple time-temperature curves can be obtained after the first time of reaching the over-temperature protection temperature, such as Figure 7 As shown, the second time to reach the target temperature can then be obtained according to the time-temperature curve.

[0138] S305 , selecting a second time from a plurality of second times and sending the second time to the test machine, so that the test machine controls the second chip in the target chip and tests the target performance of the second chip under the power consumption and after the second time.

[0139] In some embodiments, the optimal voltage and current combination may be selected as the FT test condition in terms of chip safety and time consumption, thereby improving test efficiency.

[0140] The chip testing method provided in this embodiment obtains the second time when the target temperature is reached under multiple driving currents and corresponding test voltages, and selects a second time as a test condition for high temperature testing, thereby improving test efficiency and ensuring chip safety.

[0141] Figure 8 Another embodiment of the present invention provides a chip testing method, such as Figure 8 As shown, the chip testing method provided in this embodiment includes:

[0142] S401 , receiving power consumption sent by an electronic device, where the power consumption is the power consumption corresponding to when the junction temperature of a target chip reaches a target temperature under an ambient temperature, calculated by the electronic device.

[0143] In some embodiments, a preset driving current and a corresponding test voltage sent by an electronic device are received, and the test voltage corresponding to the preset driving current is calculated based on power consumption. Specifically, the test voltage corresponding to the preset driving current can be obtained by dividing the power consumption by the preset driving current.

[0144] In practical applications, a test program sent by an electronic device may be received, where the test program includes a preset driving current and a corresponding test voltage.

[0145] In some embodiments, multiple driving currents and corresponding test voltages sent by the electronic device may also be received, and the test voltage corresponding to each driving current is calculated based on the power consumption. Specifically, the power consumption is divided by each driving current to obtain the test voltage corresponding to each driving current.

[0146] S402 , testing the first time when a first chip in the target chips reaches an over-temperature protection temperature under power consumption.

[0147] In some embodiments, if a preset driving current and a corresponding test voltage are received, a first time for a first chip in the target chips to reach an over-temperature protection temperature under the preset driving current and the corresponding test voltage is tested.

[0148] In some embodiments, if multiple driving currents and corresponding test voltages are received, the first chip in the test target chip reaches the first time of the over-temperature protection temperature under each driving current and the corresponding test voltage. It can be understood that each driving current and the corresponding test voltage have a corresponding first time.

[0149] In some embodiments, if a test program is received, the test program is run to test the first time when the first chip in the target chip reaches the over-temperature protection temperature under power consumption. The test program may also include multiple drive currents and corresponding test voltages, and the test machine runs the test program to test the first time when the first chip reaches the over-temperature protection temperature under each drive current and corresponding test voltage.

[0150] S403: Send the first time to the electronic device, so that the electronic device calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time.

[0151] Specifically, the second time t2 for reaching the target temperature T2 is calculated by T1 / t1 = T2 / t2 , the over-temperature protection temperature T1 , and the first time t1 .

[0152] In some embodiments, if multiple first times are calculated, the multiple first times are sent to the electronic device, so that the electronic device calculates each second time to reach the target temperature according to the over-temperature protection temperature and each first time. It can be understood that each driving current and the corresponding test voltage have a corresponding second time. Then, the electronic device can select a second time from the multiple second times and send it to the test machine. For example, a relatively suitable voltage, current and second time combination can be selected from aspects such as chip safety and consumption time, and the second time of the combination can be sent to the test machine, that is, the combination is sent to the test machine.

[0153] S404, receiving a second time, controlling a second chip in the target chip to test target performance of the second chip under power consumption and after the second time.

[0154] In some embodiments, the test machine may receive the modified test program, and then run the modified test program to control the second chip in the target chip to test the target performance of the second chip after the second time under power consumption.

[0155] The chip testing method provided in the present application is that a testing machine receives the power consumption corresponding to when the chip reaches the target temperature, tests the first time when the first chip reaches the over-temperature protection temperature under the power consumption and sends it to the electronic device, so that the electronic device calculates the second time when the target temperature is reached and sends it to the testing machine. The testing machine controls the second chip after receiving the second time, and tests the target performance of the second chip after the above power consumption acts for the second time, thereby completing the high temperature test without the need for additional heating equipment, reducing resource consumption and testing costs.

[0156] Fig. 9 FIG. 1 shows a schematic diagram of a chip testing device provided by an embodiment of the present application. Fig. 9 As shown, the chip testing device 10 of this embodiment is used to implement the operation corresponding to the electronic device in any of the above method embodiments. The chip testing device 10 of this embodiment includes:

[0157] The first calculation module 11 is used to calculate the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature;

[0158] A first sending module 12, used for sending the power consumption to a test machine, so that the test machine tests the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption;

[0159] A second calculation module 13, configured to receive the first time sent by the test machine, and calculate a second time to reach the target temperature according to the over-temperature protection temperature and the first time;

[0160] The second sending module 14 is used to send the second time to the test machine, so that the test machine controls the second chip in the target chip to test the target performance of the second chip under the power consumption and after the second time.

[0161] The chip testing device 10 provided in the embodiment of the present application can execute the above method embodiment. Its specific implementation principle and technical effects can be found in the above method embodiment, and this embodiment will not be repeated here.

[0162] Fig.10 FIG. 1 shows a schematic diagram of a chip testing device provided by an embodiment of the present application. Fig.10 As shown, the chip testing device 20 of this embodiment is used to implement the operation corresponding to the test machine in any of the above method embodiments. The chip testing device 20 of this embodiment includes:

[0163] A first receiving module 21 is used to receive power consumption sent by an electronic device, where the power consumption is the power consumption corresponding to when the junction temperature of a target chip reaches a target temperature under an ambient temperature calculated by the electronic device;

[0164] A first test module 22, used for testing the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption;

[0165] A second receiving module 23, used for sending the first time to the electronic device, so that the electronic device calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time;

[0166] The second testing module 24 is configured to receive the second time, control a second chip in the target chip to test target performance of the second chip at the power consumption and after the second time.

[0167] The chip testing device 20 provided in the embodiment of the present application can execute the above method embodiment. Its specific implementation principles and technical effects can be found in the above method embodiment, and this embodiment will not be repeated here.

[0168] Fig.11 FIG. 1 shows a hardware structure diagram of an electronic device provided in an embodiment of the present application. Fig.11 As shown, the electronic device 30 is used to implement the operations corresponding to the electronic device or the test machine in any of the above method embodiments. The electronic device 30 of this embodiment may include: a memory 31 , a processor 32 and a communication interface 33 .

[0169] The memory 31 is used to store computer instructions. The memory 31 may include a high-speed random access memory (RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a disk or an optical disk.

[0170] The processor 32 is used to execute the computer instructions stored in the memory to implement the method in the above embodiment. For details, please refer to the relevant description in the above method embodiment. The processor 32 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the invention can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0171] Optionally, the memory 31 may be independent or integrated with the processor 32 .

[0172] The communication interface 33 may be connected to the processor 32. The processor 32 may control the communication interface 33 to implement the functions of receiving and sending signals.

[0173] The electronic device provided in this embodiment can be used to execute the above method, and its implementation method and technical effect are similar, which will not be described in detail in this embodiment.

[0174] The present application also provides a chip testing system, including a testing machine and an electronic device, wherein the electronic device is used to execute the method in the above embodiment with the electronic device as the execution subject, and the testing machine is used to execute the method in the above embodiment with the testing machine as the execution subject.

[0175] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed by a processor, they are used to implement the methods provided in the various embodiments described above.

[0176] The present application also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium. At least one processor of a device can read the computer instructions from the computer-readable storage medium, and at least one processor executes the computer instructions so that the device implements the methods provided in the various embodiments described above.

[0177] An embodiment of the present application also provides a chip, which includes a memory and a processor, wherein the memory is used to store computer instructions, and the processor is used to call and execute the computer instructions from the memory, so that a device equipped with the chip executes the methods described in the various possible implementation modes above.

[0178] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip testing method, characterized in that: The method is used for an electronic device, and the method comprises: Calculate the power consumption of the target chip when the junction temperature reaches the target temperature under the ambient temperature; Sending the power consumption to a test machine so that the test machine tests a first chip in the target chip at a first time when the over-temperature protection temperature is reached under the power consumption, the first chip being a small part of the target chip; receiving a first time sent by the test machine, and calculating a second time to reach the target temperature according to the over-temperature protection temperature and the first time, wherein under fixed power consumption and environmental conditions, a ratio of the over-temperature protection temperature to the first time is the same as a ratio of the target temperature to the second time; The second time is sent to the test machine, so that the test machine controls the second chip in the target chip to test the target performance of the second chip under the power consumption and after the second time.

2. The method according to claim 1, characterized in that The sending of the power consumption to a test machine so that the test machine tests a first chip in the target chip and reaches a first time of an over-temperature protection temperature under the power consumption specifically includes: Calculating a corresponding test voltage according to the power consumption and the preset driving current; The preset driving current and the corresponding test voltage are sent to a test machine, so that the test machine tests a first chip in the target chip and reaches a first time of over-temperature protection temperature under the preset driving current and the corresponding test voltage.

3. The method according to claim 1, characterized in that The sending of the power consumption to a test machine so that the test machine tests a first chip in the target chip and reaches a first time of an over-temperature protection temperature under the power consumption specifically includes: Finding multiple driving currents of the target chip, and calculating a test voltage corresponding to each driving current according to the power consumption and the multiple driving currents; Sending each driving current and the corresponding test voltage to the test machine, so that the test machine tests the first chip in the target chip and reaches the first time of the over-temperature protection temperature under each driving current and the corresponding test voltage; The receiving the first time sent by the test machine, and calculating the second time to reach the target temperature according to the over-temperature protection temperature and the first time, specifically includes: receiving each first time sent by the test machine, and calculating each second time for reaching the target temperature according to the over-temperature protection temperature and each first time; The sending the second time to the test machine specifically includes: A second time is selected from a plurality of second times and sent to the test machine.

4. The method according to claim 2, characterized in that: The sending the preset driving current and the corresponding test voltage to the test machine specifically includes: Generate a test program including the preset driving current and the corresponding test voltage, and send the test program to a test machine; After obtaining the second time, the test program is modified according to the second time, and the modified test program is sent to the test machine.

5. The method according to any one of claims 1 to 4, characterized in that: The calculating the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature specifically includes: Preset target temperature and obtain ambient temperature; Calculating a difference between the target temperature and the ambient temperature; The ratio between the difference and the thermal resistance between the chip node and the environment is calculated to obtain the power consumption corresponding to the target chip when the junction temperature reaches the target temperature under the ambient temperature.

6. A chip testing method, characterized in that: The method is used for testing a machine, and the method comprises: receiving power consumption sent by an electronic device, where the power consumption is power consumption corresponding to when the junction temperature of a target chip reaches a target temperature under an ambient temperature calculated by the electronic device; Testing the first time when a first chip in the target chips reaches the over-temperature protection temperature under the power consumption, wherein the first chip is a small part of the target chips; sending the first time to the electronic device so that the electronic device calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time, wherein under fixed power consumption and environmental conditions, a ratio of the over-temperature protection temperature to the first time is the same as a ratio of the target temperature to the second time; The second time is received, a second chip in the target chip is controlled to operate at the power consumption and after the second time, a target performance of the second chip is tested.

7. The method according to claim 6, characterized in that The power consumption sent by the receiving electronic device specifically includes: Receiving a preset driving current and a corresponding test voltage sent by an electronic device, wherein the test voltage corresponding to the preset driving current is calculated based on the power consumption; The first time when the first chip in the test target chip reaches the over-temperature protection temperature under the power consumption specifically includes: A first time at which a first chip in the target chips reaches an over-temperature protection temperature under the preset driving current and the corresponding test voltage is tested.

8. The method according to claim 6, characterized in that The power consumption sent by the receiving electronic device specifically includes: Receiving a plurality of driving currents and corresponding test voltages sent by an electronic device, wherein the test voltage corresponding to each driving current is calculated based on the power consumption; The first time when the first chip in the test target chip reaches the over-temperature protection temperature under the power consumption specifically includes: Testing the first time when a first chip in the target chips reaches an over-temperature protection temperature under each driving current and corresponding test voltage; The sending the first time to the electronic device so that the electronic device calculates a second time to reach the target temperature according to the over-temperature protection temperature and the first time specifically includes: Each first time is sent to the electronic device, so that the electronic device calculates each second time to reach the target temperature according to the over-temperature protection temperature and each first time, and selects one second time from multiple second times and sends it to the test machine.

9. The method according to claim 7, characterized in that: The receiving device sends a preset driving current and a corresponding test voltage, specifically including: Receiving a test program sent by an electronic device, wherein the test program includes a preset driving current and a corresponding test voltage; The first time when the first chip in the test target chip reaches the over-temperature protection temperature under the power consumption specifically includes: Run the test program to test the first time when the first chip in the target chip reaches the over-temperature protection temperature under the power consumption; The receiving the second time, controlling the second chip in the target chip to operate at the power consumption and after the second time, and testing the target performance of the second chip specifically includes: Receive a modified test program, run the modified test program, control the second chip in the target chip under the power consumption and after the second time, and test the target performance of the second chip, wherein the modified test program is modified by the electronic device according to the second time after obtaining the second time.

10. A chip testing system, characterized in that: The method comprises a test machine and an electronic device, wherein the electronic device is used to execute the method described in any one of claims 1 to 5, and the test machine is used to execute the method described in any one of claims 6 to 9.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which are used to implement the method according to any one of claims 1 to 9 when executed by a processor.

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