Glitch Filtering Circuit, Glitch Filtering Method and Electronic Device

Abstract

The present disclosure provides a glitch filtering circuit, a glitch filtering method, and an electronic device. The glitch filtering circuit includes: an input circuit, receiving an enable signal and an input signal, for generating a same-direction input signal and a reverse input signal; a rising and falling edge signal generating circuit, receiving a rising edge delay signal, a falling edge delay signal, and the same-direction input signal, for generating a falling edge signal and a rising edge signal; a falling edge delay circuit, receiving a falling edge signal and an enable signal, for generating a falling edge delay signal; a rising edge delay circuit, receiving a rising edge signal and an enable signal, for generating a rising edge delay signal, wherein the falling edge delay signal is delayed by a predetermined time compared to the falling edge signal, and the rising edge delay signal is delayed by a predetermined time compared to the rising edge signal; and an output circuit, receiving the same-direction input signal, the reverse input signal, the falling edge delay signal, and the rising edge delay signal, for generating an output signal, wherein the output signal filters out glitches in the input signal whose width is less than or equal to twice the predetermined time.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a glitch filtering circuit, a glitch filtering method, and an electronic device. Background Art

[0002] Glitch filtering circuits are often required in chip design. Glitches are erroneous signals generated by interference in the input signal. For example, the input signals of a chip's peripheral pins may have high or low-level glitches of uncertain width. These glitches can cause circuit functions to respond incorrectly. Only signals with sufficiently wide widths are the true signals required by the system, so glitches smaller than a certain width must be filtered out.

[0003] Delay circuits are often used to filter out glitches. For example, delay units can be composed of resistors and capacitors, or they can be composed of digital gate circuits. If the pulse width of the filtered signal is relatively long, more delay units are required, and a larger area is occupied.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure provides a glitch filtering circuit, a glitch filtering method, and an electronic device. The glitch filtering circuit uses two delay units of predetermined lengths to filter out glitches in an input signal whose width is less than or equal to twice the predetermined length, thereby saving the number of delay units and reducing the area occupied by the delay units, thereby saving costs.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] The embodiment of the present disclosure provides a glitch filtering circuit, comprising: an input circuit, receiving an enable signal and an input signal, for generating a same-direction input signal and a reverse input signal according to the enable signal and the input signal; a rising and falling edge signal generating circuit, receiving a rising edge delay signal, a falling edge delay signal, and the same-direction input signal, for generating a falling edge signal and a rising edge signal according to the rising edge delay signal, the falling edge delay signal, and the same-direction input signal; a falling edge delay circuit, receiving the falling edge signal and the enable signal, for generating a falling edge delay signal according to the falling edge signal and the enable signal, the falling edge delay signal being compared with the rising edge delay signal. The falling edge signal is delayed for a predetermined time length; a rising edge delay circuit receives the rising edge signal and the enable signal, and is used to generate a rising edge delayed signal according to the rising edge signal and the enable signal, and the rising edge delayed signal is delayed by the predetermined time length compared with the rising edge signal; an output circuit receives the same-direction input signal, the reverse input signal, the falling edge delayed signal and the rising edge delayed signal, and is used to generate an output signal according to the same-direction input signal, the reverse input signal, the falling edge delayed signal and the rising edge delayed signal, and the output signal filters out glitches in the input signal whose width is less than or equal to twice the predetermined time length.

[0008] In some exemplary embodiments of the present disclosure, the rising and falling edge signal generating circuit generates the rising edge of the rising edge signal according to the rising edge of the same-direction input signal, and the rising edge delay signal is fed back to the rising and falling edge signal generating circuit, and the rising and falling edge signal generating circuit then generates the rising edge of the falling edge signal according to the rising edge of the rising edge delay signal; the rising and falling edge signal generating circuit generates the falling edge of the falling edge signal according to the falling edge of the same-direction input signal, and the falling edge delay signal is fed back to the rising and falling edge signal generating circuit, and the rising and falling edge signal generating circuit then generates the falling edge of the rising edge signal according to the falling edge of the falling edge delay signal.

[0009] In some exemplary embodiments of the present disclosure, the rising and falling edge signal generating circuit includes a first NOR gate, a first NAND gate, a first RS trigger, a second RS trigger and a first combinational logic circuit; the first NOR gate receives the falling edge delay signal and the same-direction input signal, and is used to generate a first control signal according to the falling edge delay signal and the same-direction input signal; the first RS trigger receives the first control signal and the same-direction input signal, and is used to generate a first output result according to the first control signal and the same-direction input signal; the first NAND gate receives the rising edge delay signal and the same-direction input signal, and is used to generate a second control signal according to the rising edge delay signal and the same-direction input signal; the second RS trigger receives the second control signal and the same-direction input signal, and is used to generate a second output result according to the second control signal and the same-direction input signal; the first combinational logic circuit receives the first output result and the second output result, and is used to generate the falling edge signal and the rising edge signal according to the first output result and the second output result.

[0010] In some exemplary embodiments of the present disclosure, the first combinational logic circuit includes a second NOR gate and a second NAND gate; the second NOR gate receives the first output result and the second output result, and is used to generate the falling edge signal according to the first output result and the second output result; the second NAND gate receives the first output result and the second output result, and is used to generate the rising edge signal according to the first output result and the second output result.

[0011] In some exemplary embodiments of the present disclosure, the rising and falling edge signal generating circuit includes a first OR gate, a first AND gate, a first NOT gate, a third RS flip-flop, a fourth RS flip-flop and a second combinational logic circuit; the first OR gate receives the falling edge delay signal and the same-direction input signal, and is used to generate a third control signal according to the falling edge delay signal and the same-direction input signal; the first NOT gate receives the same-direction input signal, and is used to generate a fourth control signal according to the same-direction input signal; the third RS flip-flop receives the third control signal and the fourth control signal, and is used to generate a third output result according to the third control signal and the fourth control signal; the first AND gate receives the rising edge delay signal and the same-direction input signal, and is used to generate a fifth control signal according to the rising edge delay signal and the same-direction input signal; the fourth RS flip-flop receives the fourth control signal and the fifth control signal, and is used to generate a fourth output result according to the fourth control signal and the fifth control signal; the second combinational logic circuit receives the third output result and the fourth output result, and is used to generate the falling edge signal and the rising edge signal according to the third output result and the fourth output result.

[0012] In some exemplary embodiments of the present disclosure, the second combinational logic circuit includes a second AND gate and a second OR gate; the second AND gate receives the third output result and the fourth output result, and is used to generate the falling edge signal according to the third output result and the fourth output result; the second OR gate receives the third output result and the fourth output result, and is used to generate the rising edge signal according to the third output result and the fourth output result.

[0013] In some exemplary embodiments of the present disclosure, the output circuit includes a third combinational logic circuit and a fifth RS flip-flop; the third combinational logic circuit receives the same-direction input signal, the falling edge delay signal, the reverse input signal and the rising edge delay signal, and is used to generate a set signal according to the same-direction input signal and the falling edge delay signal, and to generate a reset signal according to the reverse input signal and the rising edge delay signal; the fifth RS flip-flop is used to receive the set signal and the reset signal, and is used to generate the output signal according to the set signal and the reset signal.

[0014] In some exemplary embodiments of the present disclosure, the third combinational logic circuit includes a third NAND gate, a fourth NAND gate and a second NAND gate; the third NAND gate receives the same-direction input signal and the falling edge delay signal, and is used to generate the set signal according to the same-direction input signal and the falling edge delay signal; the second NAND gate receives the rising edge delay signal, and is used to generate the reverse rising edge delay signal according to the rising edge delay signal; the fourth NAND gate receives the reverse input signal and the reverse rising edge delay signal, and is used to generate the reset signal according to the reverse input signal and the reverse rising edge delay signal.

[0015] In some exemplary embodiments of the present disclosure, the input circuit includes a fifth NAND gate and a third NOT gate; the fifth NAND gate receives the enable signal and the input signal, and is used to generate the inverted input signal based on the enable signal and the input signal; the third NOT gate receives the inverted input signal, and is used to generate the same-direction input signal based on the inverted input signal.

[0016] An embodiment of the present disclosure provides a glitch filtering method, comprising: receiving an enable signal and an input signal; generating a same-direction input signal and a reverse input signal according to the enable signal and the input signal; generating a falling edge signal and a rising edge signal according to a rising edge delay signal, a falling edge delay signal, and the same-direction input signal; generating a falling edge delay signal according to the falling edge signal and the enable signal, the falling edge delay signal being delayed by a predetermined time length compared to the falling edge signal; generating a rising edge delay signal according to the rising edge signal and the enable signal, the rising edge delay signal being delayed by the predetermined time length compared to the rising edge signal; generating an output signal according to the same-direction input signal, the reverse input signal, the falling edge delay signal, and the rising edge delay signal, the output signal filtering out glitches in the input signal whose width is less than or equal to twice the predetermined time length.

[0017] An embodiment of the present disclosure provides an electronic device, comprising any one of the glitch filtering circuits described above.

[0018] The glitch filtering circuit provided by the embodiment of the present disclosure delays the falling edge signal by a predetermined time length through a falling edge delay circuit to generate a falling edge delayed signal; delays the rising edge signal by a predetermined time length through a rising edge delay circuit to generate a rising edge delayed signal; the falling edge delayed signal and the rising edge delayed signal are then fed back to the rising and falling edge signal generating circuit, and the obtained falling edge signal and rising edge signal are then delayed by a predetermined time length through the falling edge delay circuit and the rising edge delay circuit. Thus, two delay units with a predetermined time length can be used to filter out glitches in the input signal with a width less than or equal to twice the predetermined time length, thereby saving the number of delay units, reducing the area occupied by the delay units, and thus saving costs.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0021] Figure 1 It is a schematic diagram of a glitch filtering circuit in the related art.

[0022] Figure 2 yes Figure 1 The glitch filtering circuit shown in the figure filters out the timing diagram of high-level glitches.

[0023] Figure 3 yes Figure 1 The glitch filtering circuit shown in the figure filters out the timing diagram of low-level glitches.

[0024] Figure 4 FIG. 4 is a schematic diagram of a glitch filtering circuit in an exemplary embodiment of the present disclosure.

[0025] Figure 5 is a schematic diagram of a glitch filtering circuit in another exemplary embodiment of the present disclosure.

[0026] Figure 6 yes Figure 5 The waveform diagram of the glitch filtering circuit filtering out high-level glitches is shown.

[0027] Figure 7 yes Figure 5 The waveform diagram of the glitch filtering circuit filtering out low-level glitches is shown.

[0028] Figure 8 FIG. 1 is a schematic diagram of a rising and falling edge signal generating circuit in yet another exemplary embodiment of the present disclosure.

[0029] Figure 9 is a flow chart of a burr filtering method in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0031] The features, structures or characteristics described in the present disclosure may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0032] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in at least one hardware module or integrated circuit, or in different networks and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all content and steps, nor must they be executed in the order described. For example, some steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0034] In addition, in the description of the present disclosure, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of at least one element or component; the terms "comprising", "including" and "having" are used to express open-ended inclusion and mean that additional elements or components may exist in addition to the listed elements or components; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0035] Figure 1 It is a schematic diagram of a glitch filtering circuit in the related art.

[0036] In the related art, reference Figure 1 EN is the enable signal. This glitch filtering circuit includes basic digital gates I1 to I9, of which I1, I3, I5, I6, I7, and I8 are NAND gates, I2, I4, and I9 are inverters, and DLY1R is a basic delay unit. Its primary function is to delay the rising edge of the input digital signal INP, but not the falling edge. IN_B2 is the output signal after delaying the rising edge of the input digital signal INP (IN_B) and not the falling edge. IN_B is the digital signal processed by I3 and I4 using the enable signal EN and the output signal of I1. IN_D2 is the output signal after delaying the rising edge of the input digital signal INP (IN_D) and not the falling edge. IN_D is the digital signal processed by I1 and I2 using the input signal IN and the enable signal EN. When the delay unit input RSTB is low, the delay unit output OUT is forced low. When the delay unit input RSTB is high, the delay function is not affected. The rising edge delay of the input digital signal INP is relatively long, with a delay time of T_DLY1R. The falling edge delay is the delay of several gate circuits, which is much shorter than T_DLY1R and can be ignored.

[0037] from Figure 1As can be seen from the figure, the glitch filtering circuit uses four DLY1R units. Assuming that the delay time T_DLY1R of the delay unit is 25ns (nanoseconds), the glitch filtering circuit can filter out glitches in high-level input signals or low-level input signals with a width of less than 50ns.

[0038] Figure 2 yes Figure 1 The glitch filtering circuit shown in the figure filters out the timing diagram of high-level glitches. Figure 3 yes Figure 1 The glitch filtering circuit shown in the figure filters out the timing diagram of low-level glitches.

[0039] refer to Figure 2 The input signal IN of the glitch filtering circuit has two high-level pulses, one with a width of TD1 and the other with a width of TD0. Assume that TD1 is greater than 50ns and TD0 is less than 50ns. For the sake of convenience, the digital gate delay is basically ignored in the timing diagram, and only the delay of the four delay units DLY1R is considered. Figure 2 It can be seen that in the output signal OUTPUT of the glitch filtering circuit, the high-level pulse with a width exceeding 50ns is retained and output delayed, while the high-level pulse with a width less than 50ns is filtered out.

[0040] Similarly, reference Figure 3 In the output signal OUTPUT of the glitch filtering circuit, low-level pulses with a width exceeding 50ns are retained and outputted with a delay, while low-level pulses with a width less than 50ns are filtered out.

[0041] However, in order to filter out glitches with a width of 50 ns in the above glitch filtering circuit, four delay units with a delay time of 25 ns need to be used, that is, double the number of delay units needs to be used, which increases the area occupied by the delay units.

[0042] In response to the technical problems existing in the above-mentioned related technologies, the embodiments of the present disclosure provide a burr filtering device to solve at least one or all of the above-mentioned technical problems.

[0043] Figure 4 FIG. 4 is a schematic diagram of a glitch filtering circuit in an exemplary embodiment of the present disclosure.

[0044] like Figure 4 As shown, the glitch filtering circuit 400 provided by the embodiment of the present disclosure includes an input circuit 401 , a rising and falling edge signal generating circuit 402 , a falling edge delay circuit 403 , a rising edge delay circuit 404 and an output circuit 405 .

[0045] In which, the input circuit 401 receives an enable signal EN and an input signal IN, wherein the input signal IN includes glitches; the input circuit 401 is used to generate a unidirectional input signal IN_D and an inverse input signal IN_B according to the enable signal EN and the input signal IN, wherein, when the enable signal EN is a first level (for example, a high level), the unidirectional input signal IN_D is the same as the input signal IN, and the inverse input signal IN_B is opposite to the input signal IN.

[0046] The rising and falling edge signal generating circuit 402 receives the rising edge delayed signal RS2_D, the falling edge delayed signal RS1_D and the same-direction input signal IN_D, wherein the rising edge delayed signal RS2_D is generated by the rising edge delay circuit 404 according to the delay of the rising edge signal RS2, and the falling edge delayed signal RS1_D is generated by the falling edge delay circuit 403 according to the delay of the falling edge signal RS1; the rising and falling edge signal generating circuit 402 generates the falling edge signal RS1 and the rising edge signal RS2 according to the rising edge delayed signal RS2_D, the falling edge delayed signal RS1_D and the same-direction input signal IN_D.

[0047] Specifically, the rising / falling edge signal generating circuit 402 may generate a rising edge of the rising edge signal RS2 according to a rising edge of the same-direction input signal IN_D, and generate a falling edge of the falling edge signal RS1 according to a falling edge of the same-direction input signal IN_D.

[0048] In summary, the rising and falling edge signal generating circuit 402 (not limited to the following Figure 5 or Figure 8 In the embodiment described above, the rising edge of the rising edge signal RS2 is generated based on the rising edge of the non-inverting input signal IN_D. The rising edge delayed signal RS2_D is then fed back to the rising and falling edge signal generating circuit 402, which then generates the rising edge of the falling edge signal RS1 based on the rising edge of the rising edge delayed signal RS2_D. Furthermore, the rising and falling edge signal generating circuit 402 generates the falling edge of the falling edge signal RS1 based on the falling edge of the non-inverting input signal IN_D. The falling edge delayed signal RS1_D is then fed back to the rising and falling edge signal generating circuit 402, which then generates the falling edge of the rising edge signal RS2 based on the falling edge of the falling edge delayed signal RS1_D. In this way, the rising edge of the falling edge delayed signal RS1_D is delayed by two times T_DLY1 relative to the rising edge of the non-inverting input signal IN_D, and the falling edge of the rising edge delayed signal RS2_D is delayed by two times T_DLY1 relative to the falling edge of the non-inverting input signal IN_D.

[0049] The falling edge delay circuit 403 receives the falling edge signal RS1 and the enable signal EN, and is configured to generate a falling edge delay signal RS1_D according to the falling edge signal RS1 and the enable signal EN, wherein the falling edge delay signal RS1_D is delayed by a predetermined time duration T_DLY1 compared to the falling edge signal RS1 .

[0050] The rising edge delay circuit 404 receives the rising edge signal RS2 and the enable signal EN, and is configured to generate a rising edge delay signal RS2_D according to the rising edge signal RS2 and the enable signal EN, wherein the rising edge delay signal RS2_D is delayed by a predetermined time duration T_DLY1 compared to the rising edge signal RS2 .

[0051] The output circuit 405 receives the same-direction input signal IN_D, the reverse input signal IN_B, the falling-edge delay signal RS1_D, and the rising-edge delay signal RS2_D, and is used to generate an output signal OUTPUT based on the same-direction input signal IN_D, the reverse input signal IN_B, the falling-edge delay signal RS1_D, and the rising-edge delay signal RS2_D. The output signal OUTPUT filters out glitches in the input signal IN whose width is less than or equal to twice the predetermined duration T_DLY1.

[0052] For example, the input signal IN includes a first pulse signal with a width greater than 50ns and a second pulse signal with a width less than or equal to 50ns, and the predetermined delay duration T_DLY1 of the above-mentioned delay circuit is 25ns. Then, the glitch filtering circuit provided in the embodiment of the present disclosure can filter out the second pulse signal with a width less than or equal to 50ns in the input signal IN, that is, the output signal OUTPUT does not include the second pulse signal.

[0053] The glitch filtering circuit provided by the embodiment of the present disclosure delays the falling edge signal by a predetermined time length through a falling edge delay circuit to generate a falling edge delayed signal; delays the rising edge signal by a predetermined time length through a rising edge delay circuit to generate a rising edge delayed signal; the falling edge delayed signal and the rising edge delayed signal are then fed back to the rising and falling edge signal generating circuit, and the obtained falling edge signal and rising edge signal are then delayed by a predetermined time length through the falling edge delay circuit and the rising edge delay circuit. Thus, two delay units with a predetermined time length can be used to filter out glitches in the input signal with a width less than or equal to twice the predetermined time length, thereby saving the number of delay units, reducing the area occupied by the delay units, and thus saving costs.

[0054] The glitch filtering circuit provided in the embodiment of the present disclosure can filter out glitches of the same width (for example, less than or equal to 50ns) by using two delay units of a predetermined time length (for example, 25ns). Compared with the related art that requires the use of four delay units of a predetermined time length, this saves half the number of delay units and reduces the area cost. Moreover, the wider the width of the glitch signal to be filtered, the more delay units are saved and the more the area cost is reduced.

[0055] Figure 5 is a schematic diagram of a glitch filtering circuit in another exemplary embodiment of the present disclosure, Figure 5 The schematic diagram of the specific structure of the input circuit 401, the rising and falling edge signal generating circuit 402, the falling edge delay circuit 403, the rising edge delay circuit 404 and the output circuit 405 in the glitch filtering circuit shown in FIG. Figure 5 As an example, the specific structures of the input circuit 401, the rising and falling edge signal generating circuit 402, the falling edge delay circuit 403, the rising edge delay circuit 404 and the output circuit 405 are described, but the present disclosure is not limited thereto.

[0056] like Figure 5 As shown, the rising and falling edge signal generating circuit 402 may include a first NOR gate I3, a first NAND gate I4, a first RS trigger 4021, a second RS trigger 4022 and a first combinational logic circuit 4023, wherein the first RS trigger 4021 may be an RS trigger composed of a NOR gate I7 and a NOR gate I8, and the second RS trigger 4022 may be an RS trigger composed of a NAND gate I6 and a NAND gate I5.

[0057] The first NOR gate I3 receives the falling edge delayed signal RS1_D and the in-direction input signal IN_D generated by the falling edge delay circuit 403 , and is configured to generate a first control signal according to the falling edge delayed signal RS1_D and the in-direction input signal IN_D.

[0058] The first RS trigger 4021 receives a first control signal and a same-direction input signal IN_D, and is used to generate a first output result RS1_B based on the first control signal and the same-direction input signal IN_D; specifically, the first control signal can serve as a reset signal of the first RS trigger 4021, and the same-direction input signal IN_D can serve as a set signal of the first RS trigger 4021 to output the first output result RS1_B.

[0059] The first NAND gate I4 receives the rising edge delayed signal RS2_D and the in-direction input signal IN_D generated by the rising edge delay circuit 404 and is configured to generate a second control signal according to the rising edge delayed signal RS2_D and the in-direction input signal IN_D.

[0060] The second RS trigger 4022 receives a second control signal and a same-direction input signal IN_D, and is used to generate a second output result RS2_B based on the second control signal and the same-direction input signal IN_D; specifically, the second control signal can serve as a reset signal of the second RS trigger 4022, and the same-direction input signal IN_D can serve as a set signal of the second RS trigger 4022 to output the second output result RS2_B.

[0061] The first combinational logic circuit 4023 receives the first output result RS1_B and the second output result RS2_B, and is configured to generate a falling edge signal RS1 and a rising edge signal RS2 according to the first output result RS1_B and the second output result RS2_B.

[0062] In an exemplary embodiment, the first combinational logic circuit 4023 may include a second NOR gate I9 and a second NAND gate I10; the second NOR gate I9 receives the first output result RS1_B and the second output result RS2_B, and is used to generate a falling edge signal RS1 based on the first output result RS1_B and the second output result RS2_B; the second NAND gate I10 receives the first output result RS1_B and the second output result RS2_B, and is used to generate a rising edge signal RS2 based on the first output result RS1_B and the second output result RS2_B.

[0063] It should be noted that, in practical applications, the first combinational logic circuit 4023 may also be implemented by other logic gate circuits, which is not limited in the present disclosure.

[0064] exist Figure 5 In the embodiment, both the falling edge delay unit 403 and the rising edge delay circuit 404 are basic delay units DLY1, whose function is to delay the output of the rising edge or falling edge of the input digital signal INP; when RSTB is low, the output OUT of DLY1 is forced to 0; when RSTB is high, the delay function is not affected, and the delay time of the input digital signal INP is one delay unit T_DLY1. It can be seen from this that Figure 5 The glitch filtering circuit of the embodiment only needs to use two basic delay units DLY1. For example, T_DLY1 is also 25ns. Then the glitch filtering circuit of the embodiment can also filter out glitches of high or low level input signal IN with a width of less than 50ns. Figure 1 The circuit can filter out pulse glitches of the same length and width, and uses half the basic delay unit DLY1, which reduces the area cost.

[0065] In an exemplary embodiment, the input circuit 401 may include a fifth NAND gate I1 and a third NOT gate I2; wherein the fifth NAND gate I1 receives an enable signal EN and an input signal IN, and is used to generate an inverted input signal IN_B according to the enable signal EN and the input signal IN; the third NOT gate I2 receives the inverted input signal IN_B, and is used to generate a non-inverting input signal IN_D according to the inverted input signal IN_B.

[0066] It should be noted that, in practical applications, the input circuit 401 may also be implemented by other logic gate circuits, which is not limited in the present disclosure.

[0067] In an exemplary embodiment, the output circuit 405 may include a third combinational logic circuit 4051 and a fifth RS flip-flop 4052; wherein the fifth RS flip-flop 4052 may be composed of a NAND gate I13 and a NAND gate I14; the third combinational logic circuit 4051 receives the same-direction input signal IN_D, the falling edge delay signal RS1_D, the reverse input signal IN_B and the rising edge delay signal RS2_D, and is used to generate a set signal SET_B according to the same-direction input signal IN_D and the falling edge delay signal RS1_D, and to generate a reset signal RST_B according to the reverse input signal IN_B and the rising edge delay signal RS2_D; the fifth RS flip-flop 4052 is used to receive the set signal SET_B and the reset signal RST_B, and is used to generate an output signal OUTPUT according to the set signal SET_B and the reset signal RST_B.

[0068] In an exemplary embodiment, the third combinational logic circuit 4051 may include a third NAND gate I11, a fourth NAND gate I12 and a second NAND gate I0; the third NAND gate I11 receives the same-direction input signal IN_D and the falling edge delay signal RS1_D, and is used to generate a set signal SET_B according to the same-direction input signal IN_D and the falling edge delay signal RS1_D; the second NAND gate I0 receives the rising edge delay signal RS2_D, and is used to generate a reverse rising edge delay signal according to the rising edge delay signal RS2_D; the fourth NAND gate I12 receives the reverse input signal IN_B and the reverse rising edge delay signal, and is used to generate a reset signal RST_B according to the reverse input signal IN_B and the reverse rising edge delay signal.

[0069] It should be noted that, in practical applications, the third combinational logic circuit 4051 may also be implemented by other logic gate circuits, which is not limited in the present disclosure.

[0070] Figure 6 yes Figure 5 The waveform diagram of the glitch filtering circuit filtering out high-level glitches is shown in FIG. Figure 7 yes Figure 5 The waveform diagram of the glitch filtering circuit filtering out low-level glitches is shown.

[0071] Combined with reference Figure 5 and Figure 6 The input signal IN consists of two high-level pulses. The first high-level pulse has a width of TD1, and the second high-level pulse has a width of TD0. Assume that TD1 is greater than 50ns and TD0 is less than 50ns. For ease of description, the timing diagram largely ignores the delay of basic digital gate circuits and only considers the delay of the two delay cells DLY1.

[0072] When the enable signal is at a first level (for example, a high level), when the input signal IN_D is at a low level, the falling edge signal RS1 is at a low level (through the NAND gate I6 and the NOR gate I9), and the value of the rising edge signal RS2 is determined according to the value of the falling edge delay signal RS1_D; when the input signal IN_D is at a high level, the rising edge signal RS2 is at a high level (through I7 and I10), and the value of the falling edge signal RS1 is determined according to the value of the rising edge delay signal RS2_D. The truth table of the rising and falling edge signal generating circuit is shown in Table 1.

[0073] Table 1

[0074]

[0075] Among them, X2 is the inverse of the latch value of RS1_B, and X1 is the inverse of the latch value of RS2_B.

[0076] refer to Figure 5 and Figure 6 , it can be seen that RS2_D is the delay of RS2, RS1_D is the delay of RS1, and the delay time is T_DLY1. The rising edge of IN_D determines the rising edge of RS2. The rising edge of RS2 is delayed by 1 T_DLY1, and then RS2_D is fed back to the "rising and falling edge signal generation circuit" to obtain the rising edge of RS1. The falling edge of RS1 is determined by the falling edge of IN_D. The rising edge of RS1 is delayed by 1 T_DLY1 through the delay unit to obtain RS1_D. At the same time, the falling edge of RS1 is delayed by 1 T_DLY1 through the delay unit to obtain RS1_D. The obtained RS1_D is then fed back to the "rising and falling edge signal generation circuit" to obtain the falling edge of RS2. The falling edge of RS2 is delayed by 1 T_DLY1 through the delay unit. As a result, the rising and falling edges of IN_D are delayed by 2 T_DLY1 respectively.

[0077] It can be seen that in the final output OUTPUT, the high-level pulse width exceeding 50ns is retained and output with a delay, while the high-level pulse width less than 50ns is filtered out.

[0078] Similarly, combined with reference Figure 5 and Figure 7, it can be seen that RS2_D is the delay of RS2, RS1_D is the delay of RS1, and the delay time is T_DLY1. The rising edge of IN_D determines the rising edge of RS2. The rising edge of RS2 is delayed by 1 T_DLY1, and then RS2_D is fed back to the "rising and falling edge signal generation circuit" to obtain the rising edge of RS1. The falling edge of RS1 is determined by the falling edge of IN_D. The rising edge of RS1 is delayed by 1 T_DLY1 through the delay unit to obtain RS1_D. At the same time, the falling edge of RS1 is delayed by 1 T_DLY1 through the delay unit to obtain RS1_D. The obtained RS1_D is then fed back to the "rising and falling edge signal generation circuit" to obtain the falling edge of RS2. The falling edge of RS2 is delayed by 1 T_DLY1 through the delay unit. As a result, the rising and falling edges of IN_D are delayed by 2 T_DLY1 respectively.

[0079] It can be seen that in the final output OUTPUT, low-level pulses with a width exceeding 50ns are retained and output delayed, while low-level pulses with a width less than 50ns are filtered out.

[0080] Figure 8 FIG. 1 is a schematic diagram of a rising and falling edge signal generating circuit in yet another exemplary embodiment of the present disclosure.

[0081] refer to Figure 8 The rising and falling edge signal generating circuit 401 may include a first OR gate I16, a first AND gate I18, a first NOT gate I20, a third RS trigger 4024, a fourth RS trigger 4025 and a second combinational logic circuit 4026; wherein the third RS trigger 4024 may be an RS trigger composed of two NAND gates, and the fourth RS trigger 4025 may be an RS trigger composed of two NOR gates.

[0082] The first OR gate I16 receives the falling edge delayed signal RS1_D and the same-direction input signal IN_D, and is used to generate a third control signal based on the falling edge delayed signal RS1_D and the same-direction input signal IN_D; the first NOT gate I20 receives the same-direction input signal IN_D, and generates a fourth control signal based on the same-direction input signal IN_D; the third RS flip-flop receives the third control signal and the fourth control signal, and is used to generate a third output result RS1_B based on the third control signal and the fourth control signal; the first AND gate I18 receives the rising edge delayed signal RS2_D and the same-direction input signal IN_D, and is used to generate a fifth control signal based on the rising edge delayed signal RS2_D and the same-direction input signal IN_D; the fourth RS flip-flop receives the fourth control signal and the fifth control signal, and is used to generate a fourth output result RS2_B based on the fourth control signal and the fifth control signal; the second combinational logic circuit 4026 receives the third output result RS1_B and the fourth output result RS2_B, and is used to generate a falling edge signal RS1 and a rising edge signal RS2 based on the third output result RS1_B and the fourth output result RS2_B.

[0083] In an exemplary embodiment, the second combinational logic circuit 4026 may include a second AND gate I17 and a second OR gate I19; the second AND gate I17 receives the third output result RS1_B and the fourth output result RS2_B, and is used to generate a falling edge signal RS1 based on the third output result RS1_B and the fourth output result RS2_B; the second OR gate I19 receives the third output result RS1_B and the fourth output result RS2_B, and is used to generate a rising edge signal RS2 based on the third output result RS1_B and the fourth output result RS2_B.

[0084] It should be noted that, in practical applications, the second combinational logic circuit 4026 may also be implemented by other logic gate circuits, which is not limited in the present disclosure.

[0085] Figure 9 is a flow chart of a burr filtering method in an exemplary embodiment of the present disclosure.

[0086] like Figure 9 As shown, an embodiment of the present disclosure provides a burr filtering method, which may include:

[0087] In step S910 , an enable signal and an input signal are received.

[0088] In step S920 , a positive direction input signal and a negative direction input signal are generated according to the enable signal and the input signal.

[0089] In step S930 , a falling edge signal and a rising edge signal are generated according to the rising edge delay signal, the falling edge delay signal, and the same-direction input signal.

[0090] In step S940 , a falling edge delay signal is generated according to the falling edge signal and the enable signal. The falling edge delay signal is delayed by a predetermined time period compared to the falling edge signal.

[0091] In step S950 , a rising edge delay signal is generated according to the rising edge signal and the enable signal. The rising edge delay signal is delayed by a predetermined time period compared to the rising edge signal.

[0092] In step S960 , an output signal is generated according to the same direction input signal, the reverse direction input signal, the falling edge delay signal and the rising edge delay signal. The output signal filters out glitches in the input signal whose width is less than or equal to twice the predetermined duration.

[0093] For details not disclosed in the method embodiments of the present disclosure, reference may be made to the above-mentioned circuit embodiments of the present disclosure, and the present disclosure will not elaborate on them here.

[0094] The present disclosure also provides an electronic device including the glitch filtering circuit described in any of the above embodiments. The electronic device can be any terminal device and / or server. The terminal device can be, for example, any one or more of a mobile phone, a tablet computer, a desktop computer, a laptop computer, a game console, a television, an in-vehicle terminal, a wearable smart device, and the like.

[0095] It should also be understood that the size of the sequence numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present disclosure.

[0096] It should be noted that the above figures are merely illustrative of the processes included in the methods according to exemplary embodiments of the present disclosure and are not intended to be limiting. It is readily understood that the processes illustrated in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0097] It should be understood that any number of elements in the drawings of the present disclosure is for illustration only and not for limitation, and any naming is only for distinction and does not have any limiting meaning.

[0098] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0099] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A glitch filtering circuit, characterized in that: include: An input circuit receives an enable signal and an input signal, and is configured to generate a same-direction input signal and a reverse input signal according to the enable signal and the input signal; a rising and falling edge signal generating circuit, receiving a rising edge delay signal, a falling edge delay signal and the same-direction input signal, and configured to generate a falling edge signal and a rising edge signal according to the rising edge delay signal, the falling edge delay signal and the same-direction input signal; a falling edge delay circuit, receiving the falling edge signal and the enable signal, and configured to generate a falling edge delay signal according to the falling edge signal and the enable signal, wherein the falling edge delay signal is delayed by a predetermined time length compared to the falling edge signal; a rising edge delay circuit, receiving the rising edge signal and the enable signal, and configured to generate a rising edge delay signal according to the rising edge signal and the enable signal, wherein the rising edge delay signal is delayed by the predetermined time length compared to the rising edge signal; An output circuit receives the same-direction input signal, the reverse input signal, the falling edge delay signal, and the rising edge delay signal, and is used to generate an output signal based on the same-direction input signal, the reverse input signal, the falling edge delay signal, and the rising edge delay signal, wherein the output signal filters out glitches in the input signal whose width is less than or equal to twice the predetermined duration.

2. The glitch filtering circuit according to claim 1, characterized in that: The rising and falling edge signal generating circuit generates the rising edge of the rising edge signal according to the rising edge of the same-direction input signal, and the rising edge delay signal is fed back to the rising and falling edge signal generating circuit, and the rising and falling edge signal generating circuit then generates the rising edge of the falling edge signal according to the rising edge of the rising edge delay signal; the rising and falling edge signal generating circuit generates the falling edge of the falling edge signal according to the falling edge of the same-direction input signal, and the falling edge delay signal is fed back to the rising and falling edge signal generating circuit, and the rising and falling edge signal generating circuit then generates the falling edge of the rising edge signal according to the falling edge of the falling edge delay signal.

3. The glitch filtering circuit according to claim 1, characterized in that: The rising and falling edge signal generating circuit includes a first NOR gate, a first NAND gate, a first RS trigger, a second RS trigger and a first combination logic circuit; The first NOR gate receives the falling edge delayed signal and the same-direction input signal, and is configured to generate a first control signal according to the falling edge delayed signal and the same-direction input signal; The first RS flip-flop receives the first control signal and the same-direction input signal, and is configured to generate a first output result according to the first control signal and the same-direction input signal; The first NAND gate receives the rising edge delayed signal and the same-direction input signal, and is configured to generate a second control signal according to the rising edge delayed signal and the same-direction input signal; The second RS flip-flop receives the second control signal and the same-direction input signal, and is configured to generate a second output result according to the second control signal and the same-direction input signal; The first combinational logic circuit receives the first output result and the second output result, and is configured to generate the falling edge signal and the rising edge signal according to the first output result and the second output result.

4. The glitch filtering circuit according to claim 3, characterized in that: The first combinational logic circuit includes a second NOR gate and a second NAND gate; The second NOR gate receives the first output result and the second output result, and is used to generate the falling edge signal according to the first output result and the second output result; The second NAND gate receives the first output result and the second output result, and is configured to generate the rising edge signal according to the first output result and the second output result.

5. The glitch filtering circuit according to claim 1, characterized in that: The rising and falling edge signal generating circuit includes a first OR gate, a first AND gate, a first NOT gate, a third RS flip-flop, a fourth RS flip-flop and a second combination logic circuit; The first OR gate receives the falling edge delayed signal and the same-direction input signal, and is configured to generate a third control signal according to the falling edge delayed signal and the same-direction input signal; The first NOT gate receives the same-direction input signal and generates a fourth control signal according to the same-direction input signal; The third RS flip-flop receives the third control signal and the fourth control signal, and is configured to generate a third output result according to the third control signal and the fourth control signal; The first AND gate receives the rising edge delayed signal and the same-direction input signal, and is configured to generate a fifth control signal according to the rising edge delayed signal and the same-direction input signal; The fourth RS flip-flop receives the fourth control signal and the fifth control signal, and is configured to generate a fourth output result according to the fourth control signal and the fifth control signal; The second combinational logic circuit receives the third output result and the fourth output result, and is configured to generate the falling edge signal and the rising edge signal according to the third output result and the fourth output result.

6. The glitch filtering circuit according to claim 5, characterized in that: The second combinational logic circuit includes a second AND gate and a second OR gate; The second AND gate receives the third output result and the fourth output result, and is configured to generate the falling edge signal according to the third output result and the fourth output result; The second OR gate receives the third output result and the fourth output result, and is configured to generate the rising edge signal according to the third output result and the fourth output result.

7. The glitch filtering circuit according to claim 1, characterized in that: The output circuit includes a third combinational logic circuit and a fifth RS flip-flop; The third combinational logic circuit receives the non-inverting input signal, the falling edge delayed signal, the inverting input signal, and the rising edge delayed signal, and is configured to generate a set signal according to the non-inverting input signal and the falling edge delayed signal, and to generate a reset signal according to the inverting input signal and the rising edge delayed signal; The fifth RS flip-flop is configured to receive the set signal and the reset signal, and to generate the output signal according to the set signal and the reset signal.

8. The glitch filtering circuit according to claim 7, characterized in that: The third combination logic circuit includes a third NAND gate, a fourth NAND gate and a second NOT gate; The third NAND gate receives the same-direction input signal and the falling-edge delayed signal, and is configured to generate the set signal according to the same-direction input signal and the falling-edge delayed signal; The second NOT gate receives the rising edge delay signal and is configured to generate a reverse rising edge delay signal according to the rising edge delay signal; The fourth NAND gate receives the inverted input signal and the inverted rising edge delayed signal, and is configured to generate the reset signal according to the inverted input signal and the inverted rising edge delayed signal.

9. The glitch filtering circuit according to claim 1, characterized in that: The input circuit includes a fifth NAND gate and a third NOT gate; The fifth NAND gate receives the enable signal and the input signal, and is configured to generate the inverted input signal according to the enable signal and the input signal; The third NOT gate receives the inverting input signal and is configured to generate the non-inverting input signal according to the inverting input signal.

10. A burr filtering method, characterized in that: include: receiving an enable signal and an input signal; generating a same-direction input signal and a reverse-direction input signal according to the enable signal and the input signal; Generate a falling edge signal and a rising edge signal according to the rising edge delay signal, the falling edge delay signal and the same-direction input signal; generating a falling edge delay signal according to the falling edge signal and the enable signal, wherein the falling edge delay signal is delayed by a predetermined time length compared with the falling edge signal; generating a rising edge delay signal according to the rising edge signal and the enable signal, wherein the rising edge delay signal is delayed by the predetermined time length compared with the rising edge signal; An output signal is generated according to the same-direction input signal, the reverse input signal, the falling edge delay signal, and the rising edge delay signal, wherein the output signal filters out glitches in the input signal whose width is less than or equal to twice the predetermined duration.

11. An electronic device, characterized in that: The method comprises the glitch filtering circuit according to any one of claims 1 to 9.

Images