A low-power, high-speed level shifting circuit with a current mirror architecture

Abstract

The present invention discloses a low-power, high-speed level shift circuit of a current mirror architecture, which belongs to the field of integrated circuits, and includes a low-voltage domain input pair module, a low-voltage to high-voltage isolation module, and a high-voltage basin module. The input signal PWM is divided into two fast-response narrow pulse signals V_r and V_f and two maintenance signals PWM_p and PWM_n through the low-voltage domain input pair module, and then the voltage signal is converted into current signals I1 and I2. During the time period of the narrow pulse signals V_r and V_f, the circuit working current I1 will be relatively large, but this has avoided the high current situation of the traditional level shift circuit in the whole process; after the narrow pulse ends, the voltage of each node in the circuit is maintained through PWM_p, PWM_n and a small current I2; the left and right current mirror branches input the current signals I1 and I2 into the high-voltage basin module for current mirror comparison; the compared differential signals Vo_p and Vo_n are passed through a shaping latch module, and the final signal OUT is shaped and output.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-power, high-speed level shift circuit of a current mirror architecture. Background Art

[0002] The mainstream trend of electronic products is high power density, green energy saving and ultra-long standby. This indicator is reflected in the circuit as high frequency and low power consumption. High frequency also means high speed and low latency. The most effective strategy for low power consumption is to reduce the operating current. In the high-side gate drive circuit of the switching power supply and bridge motor drive, level shift circuits are often required to realize the logic transition from the low voltage domain to the high voltage domain, such as Figure 1 As shown. In order to meet high frequency and low power consumption, the two most important indicators of the level shift circuit are delay time and operating current; and these two indicators are often contradictory. The traditional level shift circuit structure is as follows Figure 2 As shown, Figure 2 In (a), the voltage-mode level shift circuit with a resistor as the load converts the control signal V1 into a voltage drop (V drop =Ia×Ra), thereby raising the output signal V2 to the floating power rail (V2 = VDD_H - V drop ). The subsequent circuit detects V drop And V2 is shaped into a logic signal V3 for output. In contrast, Figure 2 In (b), the current-mode level shift circuit with a current mirror as the load compares the currents in the output branches MH4 and MH5 by checking whether the input pair of tubes MH2 and MH3 are turned on or off.

[0003] exist Figure 2 (a) Charging time of V2 voltage:

[0004]

[0005] τ=R×C (2)

[0006] VDD_H and VSS_H represent the high and low level values ​​of the high voltage domain, respectively. Vt represents the flip threshold voltage of the subsequent inverter. τ represents the time constant. R and C represent the parasitic resistance and capacitance of the node, respectively. Figure 2 (a), R is Ra, C is the parasitic capacitance Coss_a of MH1 leakage; Figure 2 (b), R is the input impedance of the current mirror 1 / g m , g m is the transconductance of the current mirror, and C is the parasitic capacitance Coss_b at the drain of MH3.

[0007] Discharge time:

[0008]

[0009] Ic represents the discharge current on capacitor C, and its magnitude is related to the internal resistance of MH1. Usually, the internal resistance of MH1 is small, so Ic is large and Δt2 is small. The total delay time: Δt=Δt1+Δt2. Since Δt2 is small, Δt1 is generally the main factor, and only the charging delay time needs to be considered.

[0010] From equation (1), we can see that in order to speed up the conversion, R and C must be minimized. Since the parasitic capacitance C is an inherent characteristic of the device itself, it is difficult to change it from the circuit. drop =I×R, when V drop When R is constant, reducing R means increasing the current I and the power consumption of the circuit will increase. Summary of the invention

[0011] The object of the present invention is to provide a low-power and high-speed level shift circuit with a current mirror architecture to solve the conflicting problem between speed and power consumption in the existing level shift circuit.

[0012] In order to solve the above technical problems, the present invention provides a low-power and high-speed level shift circuit with a current mirror architecture, comprising:

[0013] The low-voltage domain input pair module divides the input logic signal PWM into two fast-response narrow pulse signals V_r and V_f and two maintenance signals PWM_p and PWM_n;

[0014] Low voltage to high voltage isolation module, plays the role of high and low voltage isolation protection;

[0015] The high-voltage basin module converts the voltage signal in the low-voltage domain into a current signal in the high-voltage basin, outputs it through the current mirror comparator, and is shaped and latched as the final output signal.

[0016] In one embodiment, the low-voltage domain input pair tube module includes a pulse generation module, a first inverter, a second inverter, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a transient current limiting resistor and a steady-state current maintaining resistor;

[0017] The input terminal of the pulse generating module is connected to the input signal PWM, and outputs two narrow pulse signals V_r and V_f, which are connected to the gate terminal of the first NMOS tube and the gate terminal of the second NMOS tube respectively; the input terminal of the first inverter is connected to the input signal PWM, and the output of the first inverter is connected to the input terminal of the second inverter and the gate terminal of the fourth NMOS tube; the output terminal of the second inverter is connected to the gate terminal of the third NMOS tube;

[0018] One end of the transient current limiting resistor is connected to the ground VSS_L of the low voltage domain, and the other end is connected to the source end of the first NMOS tube and the source end of the second NMOS tube; one end of the steady-state current maintaining resistor is connected to the ground VSS_L of the low voltage domain, and the other end is connected to the source end of the third NMOS tube and the source end of the fourth NMOS tube;

[0019] The gate terminal of the first NMOS tube is connected to the narrow pulse signal V_r, the source terminal is connected to the steady-state current maintaining resistor, and the drain terminal is connected to the drain terminal of the third NMOS tube; the gate terminal of the second NMOS tube is connected to the narrow pulse signal V_f, the source terminal is connected to the transient current limiting resistor, and the drain terminal is connected to the drain terminal of the fourth NMOS tube; the gate terminal of the third NMOS tube is connected to the output PWM_p of the second inverter, the drain terminal is connected to the drain terminal of the first NMOS tube, and the source terminal is connected to the steady-state current maintaining resistor and the source terminal of the fourth NMOS tube; the gate terminal of the fourth NMOS tube is connected to the output PWM_n of the first inverter, the drain terminal is connected to the drain terminal of the second NMOS tube, and the source terminal is connected to the steady-state current maintaining resistor and the source terminal of the third NMOS tube.

[0020] In one embodiment, the low-voltage to high-voltage isolation module includes two fifth high-voltage tubes and a sixth high-voltage tube, and a first gate clamping protection diode and a second gate clamping protection diode; the gate end of the fifth high-voltage tube is connected to the power supply VDD_L of the low-voltage domain, the source end of the fifth high-voltage tube is connected to the drain end of the first NMOS tube and the drain end of the third NMOS tube, and the drain end of the fifth high-voltage tube is connected to the high-voltage basin module;

[0021] The gate end of the sixth high-voltage tube is connected to the power supply VDD_L of the low-voltage domain, the source end of the sixth high-voltage tube is connected to the drain end of the second NMOS tube and the drain end of the fourth NMOS tube, and the drain end of the sixth high-voltage tube is connected to the high-voltage basin module;

[0022] The P end of the first gate clamping protection diode is connected to the source end of the fifth high-voltage tube, and the N end is connected to the gate end of the fifth high-voltage tube; the P end of the second gate clamping protection diode is connected to the source end of the sixth high-voltage tube, and the N end is connected to the gate end of the sixth high-voltage tube.

[0023] In one embodiment, the high voltage basin module includes two left and right current mirror comparators, a shaping latch module, a positive feedback cross-coupling load, a first clamping protection diode and a second clamping protection diode; wherein,

[0024] The left current mirror comparator is composed of the first PMOS tube, the sixth PMOS tube, the seventh NMOS tube, the tenth NMOS tube, and the eighth PMOS tube; the right current mirror comparator is composed of the second PMOS tube, the seventh PMOS tube, the ninth NMOS tube, the eighth NMOS tube, and the fifth PMOS tube; the shaping latch module includes the first Schmitt inverter and the second Schmitt inverter, the third inverter and the fourth inverter, and the RS trigger; the source end of the first PMOS tube is connected to the power supply VDD_H of the high-voltage basin, and the gate end of the first PMOS tube is connected to its own drain end and the drain end of the fifth NMOS tube at the same time; The source end of the sixth PMOS tube is connected to the power supply VDD_H of the high-voltage basin, the gate end of the sixth PMOS tube is connected to the gate end of the first PMOS tube, and the drain end of the sixth PMOS tube is connected to the drain end of the seventh NMOS tube; the source end of the seventh NMOS tube is connected to the ground VSS_H of the high-voltage basin, and the gate end is connected to the gate end of the tenth NMOS tube; the gate end and the drain end of the tenth NMOS tube are short-circuited, and are connected to the drain end of the eighth PMOS tube at the same time, and the source end of the tenth NMOS tube is connected to the ground VSS_H of the high-voltage basin; the source end of the eighth PMOS tube is connected to the power supply VDD_H of the high-voltage basin, and the gate is connected to the gate end of the second PMOS tube;

[0025] The source end of the second PMOS tube is connected to the power supply VDD_H of the high-voltage basin, the gate end of the second PMOS tube is connected to its own drain end, and is also connected to the drain end of the sixth NMOS tube; the source end of the seventh PMOS tube is connected to the power supply VDD_H of the high-voltage basin, the gate end of the seventh PMOS tube is connected to the gate end of the first PMOS tube, the drain end of the seventh PMOS tube is connected to the drain end of the ninth NMOS tube, the source end of the ninth NMOS tube is connected to the ground VSS_H of the high-voltage basin, the gate end is connected to the gate end of the eighth NMOS tube, the gate end and the drain end of the eighth NMOS tube are short-circuited, and are also connected to the drain end of the fifth PMOS tube, and the source end of the eighth NMOS tube is connected to the ground VSS_H of the high-voltage basin; the source end of the fifth PMOS tube is connected to the power supply VDD_H of the high-voltage basin, and the gate end is connected to the gate end of the first PMOS tube;

[0026] The positive feedback cross-coupling load is a third PMOS tube and a fourth PMOS tube, the source end of the third PMOS tube and the source end of the fourth PMOS tube are connected to the power supply VDD_H of the high voltage basin, the gate end of the third PMOS tube is connected to the gate end of the first PMOS tube, and the drain end of the third PMOS tube is connected to the drain end of the second PMOS tube; the gate end of the fourth PMOS tube is connected to the gate end of the second PMOS tube, and the drain end of the fourth PMOS tube is connected to the drain end of the first PMOS tube;

[0027] The N-end of the first embedded protection diode and the N-end of the second embedded protection diode are connected to the power supply VDD_H of the high-voltage basin, the P-end of the first embedded protection diode is connected to the drain end of the first PMOS tube, and the P-end of the second embedded protection diode is connected to the drain end of the second PMOS tube;

[0028] The input end of the first Schmitt inverter is connected to the drain end of the sixth PMOS tube, and the output end is connected to the input end of the third inverter, and the output end of the third inverter is connected to the S end of the RS trigger; the input end of the second Schmitt inverter is connected to the drain end of the seventh PMOS tube, and the output end is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the R end of the RS trigger; the output end Q of the RS trigger serves as the final output signal OUT.

[0029] The present invention provides a low-power and high-speed level shift circuit with a current mirror architecture, which ensures that the operating current and power consumption of the circuit in a steady state can be effectively reduced by time-sharing control of the left and right current mirror currents without affecting the speed, thereby achieving low-power and high-reliability output; and can be particularly applied to high-speed and low-power DCDC converters, motor drivers, and gate drivers. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the level shift circuit application.

[0031] Figure 2 This is a schematic diagram of a traditional level shift circuit.

[0032] Figure 3 It is a schematic diagram of a low-power and high-speed level shift circuit structure of a current mirror architecture provided by the present invention.

[0033] Figure 4 It is a schematic diagram of the timing sequence of signals of each main node of the present invention. DETAILED DESCRIPTION

[0034] The following is a further detailed description of a low-power, high-speed level shift circuit of a current mirror architecture proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] The present invention provides a low-power and high-speed level shift circuit with a current mirror architecture, such as Figure 3 As shown, the input signal PWM in the low voltage domain is converted into the output signal OUT in the high voltage domain. The circuit of the present invention comprises a low voltage domain input pair module 1, a low voltage to high voltage isolation module 2, and a high voltage basin module 3; wherein the low voltage domain power rail is a ground signal VSS_L-power signal VDD_L, and the high voltage domain power rail is a ground signal VSS_H-power signal VDD_H.

[0036] Please continue reading Figure 1In the low-voltage input pair module 1, the input signal PWM passes through the pulse generator module Pulse Generator to output two narrow pulse signals V_r and V_f. The specific timing waveform is shown in Figure 4 The V_r and V_f voltage waveforms in the figure. The pulse width tp can be adjusted by itself and is generally set at around 20nS. The two narrow pulse signals V_r and V_f control the opening of the pair of tubes NM1 and NM2 respectively. When NM1 is turned on, the diode-connected PMOS tube PM1 in the high-voltage basin module 3 and the high-voltage tube NM5 in the low-voltage to high-voltage isolation module 2, the NMOS tube NM1 in the low-voltage domain input pair of tube module 1 and the resistor R1 form a current loop, and the current flows from the power supply VDD_H in the high-voltage domain to VSS_L in the low-voltage domain.

[0037] The resistance value of resistor R1 is usually small, and it mainly starts the current limiting function to prevent the circuit current from being too large and burning the device when the NMOS tube NM1 is turned on. Figure 2 According to the analysis in, the current I1 on the resistor R1 directly affects the switching delay of this branch. The larger the current, the faster the switching, but the greater the power consumption. In order to reduce power consumption, a narrow pulse drive is used to turn on the NMOS tube NM1 for a very short time tp, as long as the signal of the subsequent current comparator is established. The same is true for the opening of the NMOS tube NM2. The input signal PWM also passes through the inverter INV1 and outputs the PWM_n signal. The PWM_n signal passes through the inverter INV2 and outputs the PWM_p signal. The specific timing waveform is shown in Figure 4 PWM_n and PWM_p voltage waveforms in the figure. PWM_n and PWM_p signals control the opening of the pair of tubes NM3 and NM4. When the NMOS tube NM3 is turned on, the diode-connected PMOS tube PM1 in the high-voltage basin module 3 and the high-voltage tube NM5 in the low-voltage to high-voltage isolation module 2, the NMOS tube NM3 in the low-voltage domain input pair tube module 1 and the resistor R2 form a current loop, and the current flows from the power supply VDD_H in the high-voltage domain to VSS_L in the low-voltage domain. The resistance value of resistor R2 is usually relatively large, so the current I2 on resistor R2 is very small. The function of this small current is mainly to maintain the state of each node in the circuit and prevent noise interference. The setting of resistance and current in the circuit, R2>>R1, I2< <I1。

[0038] In the low-voltage to high-voltage isolation module 2, NMOS tubes NM5 and NM6 are turned on to isolate the high voltage and play a role of clamping protection. The gate terminals of NMOS tubes NM5 and NM6 are connected to the power supply VDD_L of the low-voltage domain. Under normal circumstances, NMOS tubes NM5 and NM6 are always kept in the turned-on state. Both currents I1 and I2 can pass normally. In abnormal circumstances, when the source voltage of NMOS tube NM5 is higher than the gate voltage by a diode drop, the gate clamping protection diode D1 is turned on to protect the gate-source voltage of NMOS tube NM5. The gate clamping protection diode D2 also acts in the same way.

[0039] In the high-voltage basin module 3, the PMOS diode connections PM1 and PM2 are current mirror sampling tubes of their respective current loops, which are equivalent to Figure 1 The current mirror load on the right side. PMOS tube PM1, PMOS tube PM6, NMOS tube NM7, NMOS tube NM10, and PMOS tube PM8 form a current mirror comparator of the left current branch, and output a signal Vo_p. PMOS tube PM2, PMOS tube PM7, NMOS tube NM9, NMOS tube NM8, and PMOS tube PM5 form a current mirror comparator of the right current branch, and output a signal Vo_n. The shaping latch module 31 is composed of Schmidt inverters SIMT1 and SIMT2, inverters INV3 and INV4, and RS trigger RS_trigger. The differential output signals Vo_p and Vo_n are shaped by Schmidt and inverters to obtain V_S and V_R, respectively. V_S is used as the set 1S end of the RS trigger, and V_R is used as the set 0R end of the RS trigger. The output end Q of the RS trigger is used as the final output end, and the OUT signal is output. Positive feedback cross-couples loads PM3 and PM4 to improve the anti-interference ability of the left and right current branches in differential input conditions and enhance circuit reliability. Clamp protection diodes DZ1 and DZ2 are used to protect the gate-source voltage of PMOS tubes PM1 and PM2, respectively, to prevent excessive current during narrow pulse periods and gate-source breakdown of PMOS tubes PM1 and PM2.

[0040] The working principle of the present invention is mainly to divide the input signal PWM into two fast-response narrow pulse signals V_r, V_f and two maintenance signals PWM_p, PWM_n through the low-voltage domain input to the tube module 1, and then convert the voltage signal into current signals I1 and I2. During the time period of the narrow pulse signals V_r and V_f, the circuit working current I1 will be relatively large, but this has avoided the high current situation of the traditional level shift circuit in the whole process. After the narrow pulse ends, the voltage of each node in the circuit is maintained by PWM_p, PWM_n and a small current I2. The left and right current mirror branches input the current signals I1 and I2 into the high-voltage basin module 3 for current mirror comparison; the compared differential signals Vo_p and Vo_n are passed through the shaping latch module 31, and the final signal OUT is shaped and output.

[0041] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A low-power, high-speed level shift circuit with a current mirror architecture, characterized in that: include: The low-voltage domain input pair module divides the input logic signal PWM into two fast-response narrow pulse signals V_r and V_f and two maintenance signals PWM_p and PWM_n; Low voltage to high voltage isolation module, plays the role of high and low voltage isolation protection; The high-voltage basin module converts the voltage signal in the low-voltage domain into a current signal in the high-voltage basin, outputs it through the current mirror comparator, and is shaped and latched as the final output signal; The low-voltage domain input pair tube module includes a pulse generation module, a first inverter, a second inverter, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a transient current limiting resistor and a steady-state current maintaining resistor; The input terminal of the pulse generating module is connected to the input signal PWM, and outputs two narrow pulse signals V_r and V_f, which are connected to the gate terminal of the first NMOS tube and the gate terminal of the second NMOS tube respectively; the input terminal of the first inverter is connected to the input signal PWM, and the output of the first inverter is connected to the input terminal of the second inverter and the gate terminal of the fourth NMOS tube; the output terminal of the second inverter is connected to the gate terminal of the third NMOS tube; One end of the transient current limiting resistor is connected to the ground VSS_L of the low voltage domain, and the other end is connected to the source end of the first NMOS tube and the source end of the second NMOS tube; one end of the steady-state current maintaining resistor is connected to the ground VSS_L of the low voltage domain, and the other end is connected to the source end of the third NMOS tube and the source end of the fourth NMOS tube; The gate terminal of the first NMOS tube is connected to the narrow pulse signal V_r, the source terminal is connected to the transient current limiting resistor, and the drain terminal is connected to the drain terminal of the third NMOS tube; the gate terminal of the second NMOS tube is connected to the narrow pulse signal V_f, the source terminal is connected to the transient current limiting resistor, and the drain terminal is connected to the drain terminal of the fourth NMOS tube; the gate terminal of the third NMOS tube is connected to the output PWM_p of the second inverter, the drain terminal is connected to the drain terminal of the first NMOS tube, and the source terminal is connected to the steady-state current maintaining resistor and the source terminal of the fourth NMOS tube; the gate terminal of the fourth NMOS tube is connected to the output PWM_n of the first inverter, the drain terminal is connected to the drain terminal of the second NMOS tube, and the source terminal is connected to the steady-state current maintaining resistor and the source terminal of the third NMOS tube.

2. The low power consumption and high speed level shift circuit of the current mirror architecture as claimed in claim 1, characterized in that: The low-voltage to high-voltage isolation module includes two fifth high-voltage tubes and a sixth high-voltage tube, and a first gate clamping protection diode and a second gate clamping protection diode; the gate end of the fifth high-voltage tube is connected to the power supply VDD_L of the low-voltage domain, the source end of the fifth high-voltage tube is connected to the drain end of the first NMOS tube and the drain end of the third NMOS tube, and the drain end of the fifth high-voltage tube is connected to the high-voltage basin module; The gate end of the sixth high-voltage tube is connected to the power supply VDD_L of the low-voltage domain, the source end of the sixth high-voltage tube is connected to the drain end of the second NMOS tube and the drain end of the fourth NMOS tube, and the drain end of the sixth high-voltage tube is connected to the high-voltage basin module; The P end of the first gate clamping protection diode is connected to the source end of the fifth high-voltage tube, and the N end is connected to the gate end of the fifth high-voltage tube; the P end of the second gate clamping protection diode is connected to the source end of the sixth high-voltage tube, and the N end is connected to the gate end of the sixth high-voltage tube.

3. The low power consumption and high speed level shift circuit of the current mirror architecture as claimed in claim 1, characterized in that: The high voltage basin module includes two left and right current mirror comparators, a shaping latch module, a positive feedback cross-coupling load, a first clamping protection diode and a second clamping protection diode; wherein, The left current mirror comparator is composed of the first PMOS tube, the sixth PMOS tube, the seventh NMOS tube, the tenth NMOS tube, and the eighth PMOS tube; the right current mirror comparator is composed of the second PMOS tube, the seventh PMOS tube, the ninth NMOS tube, the eighth NMOS tube, and the fifth PMOS tube; the shaping latch module includes the first Schmitt inverter and the second Schmitt inverter, the third inverter and the fourth inverter, and the RS trigger; the source end of the first PMOS tube is connected to the power supply VDD_H of the high-voltage basin, and the gate end of the first PMOS tube is connected to its own drain end and the drain end of the fifth NMOS tube at the same time; The source end of the sixth PMOS tube is connected to the power supply VDD_H of the high-voltage basin, the gate end of the sixth PMOS tube is connected to the gate end of the first PMOS tube, and the drain end of the sixth PMOS tube is connected to the drain end of the seventh NMOS tube; the source end of the seventh NMOS tube is connected to the ground VSS_H of the high-voltage basin, and the gate end is connected to the gate end of the tenth NMOS tube; the gate end and the drain end of the tenth NMOS tube are short-circuited, and are connected to the drain end of the eighth PMOS tube at the same time, and the source end of the tenth NMOS tube is connected to the ground VSS_H of the high-voltage basin; the source end of the eighth PMOS tube is connected to the power supply VDD_H of the high-voltage basin, and the gate is connected to the gate end of the second PMOS tube; The source end of the second PMOS tube is connected to the power supply VDD_H of the high-voltage basin, the gate end of the second PMOS tube is connected to its own drain end, and is also connected to the drain end of the sixth NMOS tube; the source end of the seventh PMOS tube is connected to the power supply VDD_H of the high-voltage basin, the gate end of the seventh PMOS tube is connected to the gate end of the second PMOS tube, the drain end of the seventh PMOS tube is connected to the drain end of the ninth NMOS tube, the source end of the ninth NMOS tube is connected to the ground VSS_H of the high-voltage basin, the gate end is connected to the gate end of the eighth NMOS tube, the gate end and the drain end of the eighth NMOS tube are short-circuited, and are also connected to the drain end of the fifth PMOS tube, and the source end of the eighth NMOS tube is connected to the ground VSS_H of the high-voltage basin; the source end of the fifth PMOS tube is connected to the power supply VDD_H of the high-voltage basin, and the gate end is connected to the gate end of the first PMOS tube; The positive feedback cross-coupling load is a third PMOS tube and a fourth PMOS tube, the source end of the third PMOS tube and the source end of the fourth PMOS tube are connected to the power supply VDD_H of the high voltage basin, the gate end of the third PMOS tube is connected to the gate end of the first PMOS tube, and the drain end of the third PMOS tube is connected to the drain end of the second PMOS tube; the gate end of the fourth PMOS tube is connected to the gate end of the second PMOS tube, and the drain end of the fourth PMOS tube is connected to the drain end of the first PMOS tube; The N-end of the first embedded protection diode and the N-end of the second embedded protection diode are connected to the power supply VDD_H of the high-voltage basin, the P-end of the first embedded protection diode is connected to the drain end of the first PMOS tube, and the P-end of the second embedded protection diode is connected to the drain end of the second PMOS tube; The input end of the first Schmitt inverter is connected to the drain end of the sixth PMOS tube, and the output end is connected to the input end of the third inverter, and the output end of the third inverter is connected to the S end of the RS trigger; the input end of the second Schmitt inverter is connected to the drain end of the seventh PMOS tube, and the output end is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the R end of the RS trigger; the output end Q of the RS trigger serves as the final output signal OUT.

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