A method and system for optimizing impedance of power distribution network of digital system

Abstract

The present invention discloses a method and system for optimizing the impedance of a digital system power distribution network, and relates to the technical field of power distribution networks. The method for optimizing the impedance of a digital system power distribution network matches a PDN decoupling solution set based on the parasitic parameters of the digital system power supply; uses the PDN decoupling solution set to decouple the mounted PCB and microsystem substrate of the digital system power supply, and determines the PDN decoupling solution with the best PDN decoupling effect as the benchmark PDN decoupling solution; matches the benchmark PDN decoupling solution to obtain an optimization solution set; uses the matched optimization solution set to optimize the benchmark PDN decoupling solution to obtain the optimal PDN decoupling solution. The PDN decoupling solution set and the optimization solution set obtained by matching take into account the parasitic parameters of the digital system power supply, the decoupling requirements of the mounted PCB and the microsystem substrate, and solves the contradiction between the limited internal space of the microsystem and the large demand for decoupling capacitors.

Description

Technical Field

[0001] The present invention relates to the technical field of power distribution networks, and in particular to a method and system for optimizing impedance of a power distribution network of a digital system. Background Art

[0002] The information industry is one of the important industries that promote industrial development. With the continuous development of the electronics industry, the requirements for the performance of electronic products such as volume and response speed are increasing. In recent years, new packaging structures and packaging processes have emerged in an endless stream, chip manufacturing technology has continued to advance, and the trend of increasing internal integration of packaging has made microsystems an emerging product form. At the same time, the development of microsystems also has trends such as increased signal frequency, increased device integration, increased operating current and reduced operating voltage. These trends have put forward higher requirements for the design of power integrity (PI). Power distribution network (PDN) impedance simulation and optimization is an important part of power integrity design, and plays an increasingly important role in the design of substrates or PCBs.

[0003] With the development of chip manufacturing technology and packaging technology, the device integration and signal speed inside electronic products are continuously improving, and microsystems have become an emerging form, which has led to the continuous improvement of the requirements for power integrity. Unreasonable power integrity design will cause great interference to the power quality and signal quality, and even cause the system to crash.

[0004] Adding decoupling capacitors is currently the most important design idea for power integrity. Since capacitors can filter out noise interference, adding decoupling capacitors with different capacitance values ​​can optimize the resonance and impedance of the system, thereby ensuring power integrity. Adding decoupling capacitors is an empirical work, and there is no absolutely fixed method. Therefore, some designers have proposed using algorithms to reasonably arrange decoupling capacitors, and have achieved good results. However, the increasing requirements for device size have made the method of adding decoupling capacitors more and more restrictive. Simply considering the decoupling capacitors inside the microsystem can no longer meet the actual optimization needs. Summary of the invention

[0005] In view of the deficiencies of the prior art, the present invention provides a method and system for optimizing the impedance of a power distribution network of a digital system, which solves the contradiction between the limited space inside the microsystem and the large demand for decoupling capacitors, and ensures the power integrity of the microsystem.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a method for optimizing the impedance of a digital system power distribution network, comprising the following steps: matching a PDN decoupling scheme set for distributing the network impedance based on the acquired parasitic parameters of the digital system power supply, the PDN decoupling scheme set including several PDN decoupling schemes for distributing the network impedance; using the matched PDN decoupling scheme set to decouple the mounted PCB and the microsystem substrate of the digital system power supply respectively, and determining the PDN decoupling scheme with the best decoupling effect in the PDN decoupling scheme set as the benchmark PDN decoupling scheme; matching the effect of the digital system power distribution network impedance based on the benchmark PDN decoupling scheme to obtain an optimization scheme set, the optimization scheme set including several decoupling optimization schemes for optimizing the benchmark PDN decoupling scheme; optimizing the benchmark PDN decoupling scheme using the matched optimization scheme set to obtain the optimal PDN decoupling scheme.

[0007] Furthermore, the parasitic parameters of the digital system power supply include parasitic inductance, parasitic resistance and parasitic capacitance. The process of matching the PDN decoupling scheme set for allocating network impedance based on the acquired parasitic parameters of the digital system power supply is as follows: obtaining the parasitic matching parameters of the digital system power supply stored in the decoupling scheme database, the parasitic matching parameters of the digital system power supply include parasitic matching inductance, parasitic matching resistance and parasitic matching capacitance; calculating the decoupling scheme matching coefficient based on the parasitic matching parameters and the parasitic parameters; comparing the decoupling scheme matching coefficient with the decoupling scheme coefficient matching interval stored in the decoupling scheme database one by one; and obtaining the PDN decoupling scheme set corresponding to the decoupling scheme coefficient matching interval that has been successfully compared.

[0008] Furthermore, the calculation formula of the decoupling scheme matching coefficient is as follows: Wherein, DsC is the matching coefficient of the decoupling scheme, Jg is the parasitic inductance, CJg is the parasitic matching inductance, ΔDG is the allowable deviation value of inductance matching, Jr is the parasitic capacitance, CJr is the parasitic matching capacitance, ΔDR is the allowable deviation value of capacitance matching, Jz is the parasitic resistance, CJz is the parasitic matching resistance, ΔDZ is the allowable deviation value of resistance matching, α1 is the parasitic inductance matching weight factor, α2 is the parasitic capacitance matching weight factor, α3 is the parasitic resistance matching weight factor, and α1+α2+α3=1.

[0009] Furthermore, the matched PDN decoupling scheme set is used to decouple the mounted PCB and microsystem substrate of the digital system power supply, and the process of determining the PDN decoupling scheme with the best decoupling effect in the PDN decoupling scheme set as the benchmark PDN decoupling scheme is as follows: each PDN decoupling scheme in the PDN decoupling scheme set is applied to the ADS software to decouple the digital system power supply established in the ADS software; the mounted PCB decoupling index and the microsystem substrate decoupling index are obtained respectively, and the mounted PCB decoupling index is used to quantify the effect of the PDN decoupling scheme on the decoupling of the mounted PCB of the digital system power supply The decoupling effect of the PDN decoupling scheme is quantified by the microsystem substrate decoupling index, which is used to quantify the decoupling effect of the PDN decoupling scheme on the microsystem substrate of the digital system power supply. The obtained mounted PCB decoupling index and the microsystem substrate decoupling index are fused and calculated to obtain the PDN decoupling index, which is used to quantify the effect of each PDN decoupling scheme in the PDN decoupling scheme set on the impedance of the digital system power distribution network, and is used as a basis for matching the optimized scheme set. The PDN decoupling scheme corresponding to the maximum PDN decoupling index among the calculated PDN decoupling indexes is marked as the benchmark PDN decoupling scheme.

[0010] Furthermore, the process of respectively obtaining the mounted PCB decoupling index and the microsystem substrate decoupling index is as follows: based on the set requirements, the mounted PCB impedance requirement curve and the microsystem substrate impedance requirement curve after the digital system power supply is decoupled are obtained; according to each PDN decoupling scheme in the PDN decoupling scheme set and the parasitic parameters of the digital system power supply, the mounted PCB impedance expected curve and the microsystem substrate impedance expected curve after the digital system power supply is decoupled and stored in the decoupling scheme database are obtained; the mounted PCB impedance actual curve and the microsystem substrate impedance actual curve are obtained after each PDN decoupling scheme in the PDN decoupling scheme set is applied to the ADS software to decouple the digital system power supply established in the ADS software; the mounted PCB impedance requirement curve, the mounted PCB impedance expected curve and the mounted PCB impedance actual curve are analyzed to obtain the mounted PCB decoupling index; the microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve are analyzed to obtain the microsystem substrate decoupling index.

[0011] Furthermore, the process of analyzing the PCB impedance requirement curve, the PCB impedance expected curve and the PCB impedance actual curve to obtain the PCB decoupling index is as follows: intercepting several sections of the PCB impedance requirement curve, sampling each section of the requirement curve, and obtaining the PCB required impedance of each sampling point; obtaining the PCB expected impedance and the PCB actual impedance obtained on the PCB impedance expected curve and the PCB impedance actual curve for each sampling point of the required impedance; fusing the PCB required impedance, the PCB expected impedance and the PCB actual impedance to obtain the PCB decoupling index.

[0012] Furthermore, the microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve are analyzed to obtain the microsystem substrate decoupling index: several sections of the microsystem substrate impedance requirement curve are intercepted, each section of the requirement curve is sampled, and the microsystem substrate required impedance of each sampling point is obtained; for each sampling point of the required impedance, the microsystem substrate expected impedance and the microsystem substrate actual impedance obtained on the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve are obtained respectively; the microsystem substrate required impedance, the microsystem substrate expected impedance and the microsystem substrate actual impedance are fused to obtain the microsystem substrate decoupling index.

[0013] Furthermore, the benchmark PDN decoupling scheme is optimized by using the optimization scheme set obtained by matching, and the process of obtaining the optimal PDN decoupling scheme is as follows: on the basis of the benchmark PDN decoupling scheme, each decoupling optimization scheme in the optimization scheme set is applied to the ADS software to optimize the decoupling of the digital system power supply established in the ADS software; the mounting PCB optimization decoupling index and the microsystem substrate optimization decoupling index are respectively obtained, the mounting PCB optimization decoupling index is used to quantify the decoupling effect of the mounting PCB of the digital system power supply after the decoupling optimization scheme optimizes the benchmark PDN decoupling scheme, and the microsystem substrate optimization decoupling index is used to quantify the decoupling effect of the microsystem substrate of the digital system power supply after the decoupling optimization scheme optimizes the benchmark PDN decoupling scheme; the mounting PCB optimization decoupling index and the microsystem substrate optimization decoupling index are processed to obtain the optimization scheme evaluation index, and the optimization scheme evaluation index is used to quantify the decoupling effect of each decoupling optimization scheme on the digital system power supply after optimizing the benchmark PDN decoupling scheme; the decoupling optimization scheme corresponding to the maximum optimization scheme evaluation index among the calculated optimization scheme evaluation indexes is marked as the optimal PDN decoupling scheme.

[0014] Furthermore, the calculation formula of the optimization scheme evaluation index is as follows: OsE=β1*SOD+β2*MSO; wherein OsE is the optimization scheme evaluation index, SOD is the PCB mounting optimization decoupling index, MSO is the microsystem substrate optimization decoupling index, β1 is the weight factor of the PCB mounting optimization decoupling index, β2 is the weight factor of the microsystem substrate optimization decoupling index, and β1+β2=1.

[0015] A digital system power distribution network impedance optimization system comprises a decoupling scheme matching module, a reference scheme determination module, an optimization scheme matching module and an optimal decoupling scheme determination module, wherein: the decoupling scheme matching module is used to match a PDN decoupling scheme set for distributing network impedance based on the acquired parasitic parameters of the digital system power supply, and the PDN decoupling scheme set includes a plurality of PDN decoupling schemes for distributing network impedance; the reference scheme determination module is used to use the matched PDN decoupling scheme set to respectively decouple the mounted PCB and microsystem substrate of the digital system power supply, and determine the PDN decoupling scheme with the best decoupling effect in the PDN decoupling scheme set as the reference PDN decoupling scheme; the optimization scheme matching module is used to obtain an optimization scheme set based on the effect of the reference PDN decoupling scheme on the digital system power distribution network impedance, and the optimization scheme set includes a plurality of primary decoupling optimization schemes for optimizing the reference PDN decoupling scheme; the optimal decoupling scheme determination module is used to optimize the reference PDN decoupling scheme using the matched primary optimization scheme set to obtain the optimal PDN decoupling scheme.

[0016] The present invention has the following beneficial effects:

[0017] (1) The optimization method of the impedance of the power distribution network of the digital system comprehensively considers the parasitic parameters of the digital system power supply, the decoupling requirements of the mounted PCB and the microsystem substrate by matching the obtained PDN decoupling scheme set and the optimization scheme set, thereby providing a comprehensive optimization scheme. The substrate and PCB decoupling capacitor network are used for collaborative decoupling, which solves the contradiction between the limited internal space of the microsystem and the large demand for decoupling capacitors, and helps to achieve effective management of power integrity in a limited space.

[0018] (2) The optimization method of the impedance of the power distribution network of the digital system adopts a series of quantitative methods to evaluate and optimize the decoupling scheme by matching the matching coefficient, decoupling index and optimization scheme evaluation index, which makes the whole optimization process more scientific and controllable. Through the optimized decoupling scheme, especially the optimization on the mounting PCB and microsystem substrate, the impedance matching and power integrity of the power distribution network of the digital system are effectively improved, which helps to reduce power noise and improve system performance.

[0019] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a flow chart of the method for optimizing the impedance of a power distribution network of a digital system according to the present invention.

[0021] Figure 2 This is a system flow chart for optimizing the impedance of the power distribution network of the digital system of the present invention. DETAILED DESCRIPTION

[0022] The embodiment of the present application optimizes the PDN impedance by using a method and system for optimizing the impedance of a power distribution network of a digital system, thereby optimizing the PDN impedance by using a collaborative decoupling method of a substrate and a PCB decoupling capacitor network, thereby resolving the contradiction between the limited space inside the microsystem and the large demand for decoupling capacitors, and ensuring the power integrity of the microsystem.

[0023] The overall idea of ​​the problem in the embodiment of this application is as follows:

[0024] First, the parasitic parameters of the digital system power supply need to be obtained. This includes the inductance, resistance, capacitance and other parameters of various power supply components and lines. Based on the obtained parasitic parameters of the digital system power supply, a PDN decoupling solution set is matched. This solution set includes multiple decoupling solutions for distributing network impedance. Each decoupling solution involves arranging different numbers and types of decoupling capacitors on the substrate and PCB.

[0025] The matched PDN decoupling solution set is used to decouple the substrate and PCB of the microsystem respectively, which involves placing decoupling capacitors at appropriate locations to reduce power supply noise and improve the signal integrity and timing of the system. By evaluating the effects of different PDN decoupling solutions, the best solution in the PDN decoupling solution set is determined as the benchmark PDN decoupling solution, which can be evaluated by simulation, emulation or actual testing.

[0026] Based on the benchmark PDN decoupling solution, an optimization solution set for the impedance effect of the digital system power distribution network is established, including optimization of the type, quantity, and layout of decoupling capacitors. The pros and cons of the benchmark PDN decoupling solution on the impedance effect of the digital system power distribution network are quantified into a numerical value, and the quantified benchmark PDN decoupling solution effect is matched with the numerical range stored in the pre-established decoupling solution database to find the optimization solution set corresponding to the successfully matched numerical range.

[0027] The benchmark PDN decoupling solution is optimized using the matched optimization solution set, which involves adjusting the layout, type, and number of decoupling capacitors to further improve power integrity. After optimization, the optimal PDN decoupling solution is determined, which achieves the best power distribution network impedance effect in a limited space and solves the problem of balancing the space limitations and decoupling capacitor requirements within the microsystem.

[0028] See also Figure 1 The embodiment of the present invention provides a technical solution: a method for optimizing the impedance of a digital system power distribution network, comprising the following steps: matching a PDN decoupling scheme set for distributing the network impedance based on the acquired parasitic parameters of the digital system power supply, the PDN decoupling scheme set including several PDN decoupling schemes for distributing the network impedance; using the matched PDN decoupling scheme set to decouple the mounted PCB and the microsystem substrate of the digital system power supply respectively, and determining the PDN decoupling scheme with the best decoupling effect in the PDN decoupling scheme set as the benchmark PDN decoupling scheme; matching the effect of the benchmark PDN decoupling scheme on the impedance of the digital system power distribution network to obtain an optimization scheme set, the optimization scheme set including several decoupling optimization schemes for optimizing the benchmark PDN decoupling scheme; the effect of the benchmark PDN decoupling scheme on the impedance of the digital system power distribution network can be quantified as a numerical value, and the given numerical value is matched one by one with the numerical interval stored in the decoupling scheme database to obtain the optimization scheme set corresponding to the numerical interval with successful matching.

[0029] The benchmark PDN decoupling solution is optimized by using the optimized solution set obtained by matching to obtain the optimal PDN decoupling solution.

[0030] A collaborative PDN optimization method based on decoupling capacitors on microsystem substrates and mounted PCBs is adopted. First, the parasitic parameters in each level of PDN in each power network are extracted using design software, and then the power distribution network composed of VRM, PCB, microsystem and chip is modeled with equivalent circuits, where VRM and microsystem are both located on the PCB. A decoupling capacitor combination scheme is designed for this microsystem, and decoupling capacitors of different schemes are added to the mounted PCB and microsystem substrate respectively. The results are compared to find a relatively better decoupling capacitor optimization scheme, and finally the selected decoupling capacitor combination scheme is optimized again to obtain the final decoupling capacitor optimization scheme.

[0031] Advanced Design System (ADS) is a mainstream software in digital system design, with powerful functions, rich templates, and support for efficient and accurate simulation capabilities. In this article, the simulation and optimization of the PDN impedance of the microsystem are all carried out in ADS software. Taking the 1V power supply network as an example, the PDN model of the 1V network is constructed using the parasitic parameters in the above table. The values ​​of the parasitic parameters of each part of the model can be obtained by calculating the theoretical value, extracting the parasitic parameters by software, and consulting the device manual, and then substituting them into the constructed PDN model. By building the PDN model of the digital system in ADS, the impedance values ​​at different frequencies can be simulated. The impedance curve is generally displayed on a log axis, so the data is sparse in the low frequency range and dense in the high frequency range. Therefore, when setting the simulation parameters, the frequency scan is divided into two sections. The first section is 1MHzˉ100MHz with a step size of 0.5MHz, and the second section is 100MHzˉ3GHz with a step size of 5MHz.

[0032] In the design, the locations where decoupling capacitors can be added include PCB and substrate. Since different locations of decoupling capacitors will produce different decoupling effects, the impact of single capacitors with different capacitance values ​​on the PCB and microsystem substrate on the impedance curve of the network PDN is first analyzed. According to the resonant point position of each capacitor, several capacitors with capacitance values ​​in the range of 22pFˉ47uF are selected, and they are respectively connected to the PCB and substrate of the model built in ADS. The impedance curve after connection is simulated. The large-capacitance decoupling capacitor has a significant regulating effect on the low-frequency range, and can reduce the resonance amplitude, making the impedance curve smoother overall; while the small-capacitance decoupling capacitor can play a regulating role in the high-frequency range.

[0033] Due to the limited internal space of the microsystem, it is necessary to arrange as few decoupling capacitors as possible inside. In order to maximize the effect of the decoupling capacitor network on the mounted PCB, the decoupling capacitor optimization scheme added on the mounted PCB is first designed, and based on this, the decoupling capacitor network is added on the microsystem substrate. Based on the above ideas, several decoupling capacitor optimization schemes for mounted PCB are designed. Each scheme is based on the previous scheme and further adds several decoupling capacitors based on the impedance simulation results.

[0034] Specifically, the parasitic parameters of the digital system power supply include parasitic inductance, parasitic resistance and parasitic capacitance. The process of matching the PDN decoupling scheme set for allocating network impedance based on the obtained parasitic parameters of the digital system power supply is as follows: obtaining the parasitic matching parameters of the digital system power supply stored in the decoupling scheme database, the parasitic matching parameters of the digital system power supply include parasitic matching inductance, parasitic matching resistance and parasitic matching capacitance; calculating the decoupling scheme matching coefficient based on the parasitic matching parameters and the parasitic parameters; comparing the decoupling scheme matching coefficient with the decoupling scheme coefficient matching interval stored in the decoupling scheme database one by one; and obtaining the PDN decoupling scheme set corresponding to the decoupling scheme coefficient matching interval that has been successfully compared.

[0035] The parasitic parameters and parasitic matching parameters of the actual digital system power supply are obtained. Based on the parasitic matching parameters and parasitic parameters, the matching coefficient of the decoupling scheme is calculated, the characteristics of the actual system are considered, and the matching degree between the decoupling scheme and the actual system is expressed in numerical form. The calculated decoupling scheme matching coefficient is compared with the matching coefficient stored in the database to determine the decoupling scheme with a high matching degree. By comparing the successful decoupling scheme coefficient matching interval, the adapted PDN decoupling scheme set is obtained.

[0036] By obtaining parasitic matching parameters, the characteristics of the actual system can be simulated more accurately, which helps to ensure that the decoupling solution better adapts to the parasitic parameters of the digital system and improves the accuracy of optimization. Considering the matching of multiple parasitic elements such as parasitic inductance, parasitic resistance and parasitic capacitance makes the system optimization more comprehensive and can adapt to different types of interference and power supply noise.

[0037] The calculation formula of the decoupling scheme matching coefficient is as follows: Wherein, DsC is the matching coefficient of the decoupling scheme, Jg is the parasitic inductance, CJg is the parasitic matching inductance, ΔDG is the allowable deviation value of inductance matching, Jr is the parasitic capacitance, CJr is the parasitic matching capacitance, ΔDR is the allowable deviation value of capacitance matching, Jz is the parasitic resistance, CJz is the parasitic matching resistance, ΔDZ is the allowable deviation value of resistance matching, α1 is the parasitic inductance matching weight factor, α2 is the parasitic capacitance matching weight factor, α3 is the parasitic resistance matching weight factor, and α1+α2+α3=1.

[0038] In this implementation, three parasitic elements, namely parasitic inductance, parasitic capacitance and parasitic resistance, are considered to make the calculation more comprehensive and adaptable to different types of system interference. By calculating the deviation between each parasitic element and its matching element and multiplying it by the corresponding weight factor, the matching coefficient is obtained, which reflects the contribution of each parasitic element to the overall matching degree. A quantitative indicator is provided to accurately represent the matching degree between the decoupling scheme and the actual system parasitic parameters.

[0039] The allowable deviation values ​​of inductance, capacitance and resistance matching are introduced to make the matching degree calculation more flexible, take into account certain deviations of parameters that may exist in the actual system, and be able to tolerate certain parameter deviations that may exist in the actual system, thereby improving the robustness of the method.

[0040] Specifically, the matched PDN decoupling scheme set is used to decouple the mounted PCB and microsystem substrate of the digital system power supply, and the process of determining the PDN decoupling scheme with the best decoupling effect in the PDN decoupling scheme set as the benchmark PDN decoupling scheme is as follows: each PDN decoupling scheme in the PDN decoupling scheme set is applied to the ADS software to decouple the digital system power supply established in the ADS software; the mounted PCB decoupling index and the microsystem substrate decoupling index are obtained respectively, and the mounted PCB decoupling index is used to quantify the effect of the PDN decoupling scheme on the mounted PCB of the digital system power supply Decoupling effect: The microsystem substrate decoupling index is used to quantify the decoupling effect of the PDN decoupling scheme on the microsystem substrate of the digital system power supply. The obtained mounted PCB decoupling index and the microsystem substrate decoupling index are fused and calculated to obtain the PDN decoupling index. The PDN decoupling index is used to quantify the effect of each PDN decoupling scheme in the PDN decoupling scheme set on the impedance of the digital system power distribution network, and is used as the basis for matching the optimized scheme set. The PDN decoupling scheme corresponding to the maximum PDN decoupling index among the calculated PDN decoupling indexes is marked as the benchmark PDN decoupling scheme.

[0041] The calculation formula of PDN decoupling index is: PdQ=ν1*DI+ν2*WI, where PdQ is the PDN decoupling index, DI is the PCB decoupling index, WI is the microsystem substrate decoupling index, ν1 is the weight factor of the PCB decoupling index, and ν2 is the weight factor of the microsystem substrate decoupling index.

[0042] In this implementation, the digital system power supply is decoupled by applying each solution in the PDN decoupling solution set to the ADS software. This step ensures that each solution is simulated and can obtain quantitative indicators of the decoupling effect. For each system to which the PDN decoupling solution is applied, the mounting PCB decoupling index and the microsystem substrate decoupling index are obtained respectively. These indices are used to quantify the decoupling effect of the PDN decoupling solution on the mounting PCB and microsystem substrate of the digital system power supply.

[0043] The PDN decoupling index is obtained by merging the mounted PCB decoupling index and the microsystem substrate decoupling index. This calculation may take into account the trade-off relationship between the various indexes to comprehensively reflect the overall decoupling effect. The PDN decoupling scheme corresponding to the maximum PDN decoupling index among the calculated PDN decoupling indexes is marked as the benchmark PDN decoupling scheme.

[0044] By using the Mounting PCB Decoupling Index and the Microsystem Substrate Decoupling Index, the system takes full account of the decoupling effect of the digital system power supply, helping to ensure good decoupling at both the mounting and microsystem substrate levels.

[0045] Specifically, the process of respectively obtaining the mounted PCB decoupling index and the microsystem substrate decoupling index is as follows: based on the set requirements, the mounted PCB impedance requirement curve and the microsystem substrate impedance requirement curve after the digital system power supply is decoupled are obtained; according to each PDN decoupling scheme in the PDN decoupling scheme set and the parasitic parameters of the digital system power supply, the mounted PCB impedance expected curve and the microsystem substrate impedance expected curve after the digital system power supply is decoupled and stored in the decoupling scheme database are obtained; each PDN decoupling scheme in the PDN decoupling scheme set is applied to the ADS software to decouple the digital system power supply established in the ADS software, and the mounted PCB impedance actual curve and the microsystem substrate impedance actual curve are obtained; the mounted PCB impedance requirement curve, the mounted PCB impedance expected curve and the mounted PCB impedance actual curve are analyzed to obtain the mounted PCB decoupling index; the microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve are analyzed to obtain the microsystem substrate decoupling index.

[0046] In this implementation scheme, the required impedance curve of the mounted PCB and the required impedance curve of the microsystem substrate after the digital system power supply is decoupled are set. These curves are the expected requirements for the system impedance performance, taking into account aspects such as frequency response and impedance matching. For each PDN decoupling scheme in the PDN decoupling scheme set and the parasitic parameters of the digital system power supply, the expected impedance curve of the mounted PCB and the expected impedance curve of the microsystem substrate after the digital system power supply is decoupled are obtained from the decoupling scheme database, which is the expected effect obtained based on theoretical calculation or simulation.

[0047] Each PDN decoupling solution in the PDN decoupling solution set is applied to the ADS software, and the digital system power supply established in the ADS software is decoupled to obtain the actual impedance curve of the mounted PCB and the actual impedance curve of the microsystem substrate. This is the decoupling effect obtained based on actual simulation.

[0048] The mount PCB impedance requirement curve, the mount PCB impedance expected curve and the mount PCB impedance actual curve are compared and analyzed to obtain the mount PCB decoupling index. Similarly, a similar comparison and analysis is performed on the microsystem substrate to obtain the microsystem substrate decoupling index.

[0049] By comparing the actual and expected curves, we can fully understand the decoupling effect of the PDN decoupling solution on the mounted PCB and microsystem substrate, which helps to determine the actual performance of the solution. By analyzing the actual curve, we can more realistically evaluate the performance of the PDN decoupling solution in the actual system, which is very important for actual engineering applications. By comparing and analyzing the curves, we can calculate the mounted PCB decoupling index and the microsystem substrate decoupling index, providing a quantitative way to measure the effect of the decoupling solution in different parts.

[0050] Specifically, the process of analyzing the required impedance curve of the mounted PCB, the expected impedance curve of the mounted PCB, and the actual impedance curve of the mounted PCB to obtain the decoupling index of the mounted PCB is as follows: intercepting several sections of the required curve on the required impedance curve of the mounted PCB, sampling each section of the required curve, and obtaining the required impedance of the mounted PCB at each sampling point; obtaining the expected impedance of the mounted PCB and the actual impedance of the mounted PCB obtained on the expected impedance curve of the mounted PCB and the actual impedance curve of the mounted PCB for each sampling point of the required impedance; fusing the required impedance of the mounted PCB, the expected impedance of the mounted PCB, and the actual impedance of the mounted PCB to obtain the decoupling index of the mounted PCB. The required impedance curve of the mounted PCB, the expected impedance curve of the mounted PCB, and the actual impedance curve of the mounted PCB are all obtained through the ADS software.

[0051] The calculation formula for the mounting PCB decoupling index is: Where i is the number of the required curve, i = 1, 2, 3, ..., n, n is the total number of segments of the required curve, j is the number of sampling points in each required curve, j = 1, 2, 3, ..., m, m is the total number of sampling points in each required curve, Psz ij Pyz is the actual impedance of the mounted PCB at the jth sampling point in the i-th segment requirement curve, ij is the required impedance of the mounted PCB corresponding to the actual impedance of the mounted PCB at the jth sampling point in the i-th segment requirement curve, Pqz ij is the expected impedance of the mounted PCB corresponding to the actual impedance of the mounted PCB at the jth sampling point in the i-th requirement curve. The difference between the expected impedance of the mounted PCB and the actual impedance of the mounted PCB represents the degree of difference between the actual impedance and the expected impedance. The difference between the actual impedance of the mounted PCB and the required impedance of the mounted PCB represents the degree of difference between the actual impedance and the required impedance. δ1 is the weight factor of the difference between the actual impedance of the mounted PCB and the required impedance of the mounted PCB. δ2 is the weight factor of the difference between the expected impedance of the mounted PCB and the actual impedance of the mounted PCB.

[0052] In this embodiment, first, several segments are selected from the mounting PCB impedance requirement curve, which can be a critical frequency range or a specific area to ensure attention to system performance. For each selected requirement curve, sampling is performed to obtain the mounting PCB required impedance of each sampling point. This step is to discretize the requirement curve for subsequent comparison and calculation.

[0053] Using ADS software, the expected and actual curves of the PCB impedance corresponding to each sampling point are obtained. These curves represent the system performance obtained by simulation. The PCB impedance requirement curve, the expected PCB impedance curve and the actual PCB impedance curve are compared and fused, and the PCB decoupling index is calculated, which integrates the difference between the actual impedance and the expected impedance.

[0054] The calculated PCB decoupling index can quantitatively evaluate the decoupling effect of the PDN decoupling solution on the PCB, providing a numerical indicator for easy comparison of different solutions. By comparing the PCB impedance requirement curve, the PCB impedance expected curve, and the PCB impedance actual curve, the PCB decoupling index combines the difference between the actual performance and the expected performance, making it possible to fully understand the system performance. By introducing the weight factor, the weight of the difference can be adjusted according to specific needs.

[0055] By processing each sampling point, the decoupling effects of multiple frequency points are integrated, rather than just considering the performance of a single frequency point, which helps to fully understand the performance of the system in different frequency ranges. As a comprehensive performance indicator, the PCB decoupling index provides a clear basis for subsequent optimization and can be used to select the best PDN decoupling solution to meet the impedance requirements of the PCB.

[0056] Specifically, the microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve are analyzed to obtain the microsystem substrate decoupling index: several sections of the microsystem substrate impedance requirement curve are intercepted, each section of the requirement curve is sampled, and the microsystem substrate required impedance of each sampling point is obtained; for each sampling point of the required impedance, the microsystem substrate expected impedance and the microsystem substrate actual impedance obtained on the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve are obtained respectively; the microsystem substrate required impedance, the microsystem substrate expected impedance and the microsystem substrate actual impedance are fused to obtain the microsystem substrate decoupling index. The microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve are all obtained through ADS software.

[0057] The calculation formula of microsystem substrate decoupling index is:

[0058]

[0059] Where a is the number of the required curve, a = 1, 2, 3, ..., A, A is the total number of segments of the required curve, b is the number of sampling points in each required curve, b = 1, 2, 3, ..., B, B is the total number of sampling points in each required curve, Wsz ab is the actual impedance of the microsystem substrate at the bth sampling point in the ath segment requirement curve, Wyz ab is the required impedance of the microsystem substrate corresponding to the actual impedance of the microsystem substrate at the bth sampling point in the ath segment requirement curve, Wqz ab is the expected impedance of the microsystem substrate corresponding to the actual impedance of the microsystem substrate at the bth sampling point in the ath section requirement curve, the difference between the expected impedance of the microsystem substrate and the actual impedance of the microsystem substrate represents the degree of difference between the actual impedance and the expected impedance, the difference between the actual impedance of the microsystem substrate and the required impedance of the microsystem substrate represents the degree of difference between the actual impedance and the required impedance, γ1 is the weight factor of the difference between the actual impedance of the microsystem substrate and the required impedance of the microsystem substrate, and γ2 is the weight factor of the difference between the impedance of the microsystem substrate and the actual impedance of the microsystem substrate.

[0060] In this implementation, similar to the analysis of mounted PCB, several segments are first selected from the microsystem substrate impedance requirement curve to meet specific areas of concern for system performance. For each selected requirement curve, sampling is performed to obtain the microsystem substrate required impedance at each sampling point. This step is to discretize the requirement curve to facilitate subsequent comparison and calculation.

[0061] Using ADS software, the expected and actual curves of the microsystem substrate impedance corresponding to each sampling point are obtained, which represent the system performance obtained by simulation. The microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve, and the microsystem substrate impedance actual curve are compared and fused. The microsystem substrate decoupling index is calculated, which integrates the degree of difference between the actual impedance and the expected impedance.

[0062] By calculating the microsystem substrate decoupling index, the decoupling effect of the PDN decoupling solution on the microsystem substrate can be quantitatively evaluated, providing a numerical indicator for easy comparison of different solutions. By comparing the microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve, and the microsystem substrate impedance actual curve, the microsystem substrate decoupling index combines the difference between actual performance and expected performance, making it possible to fully understand the system performance.

[0063] Specifically, the benchmark PDN decoupling scheme is optimized by using the matched optimization scheme set to obtain the process of the optimal PDN decoupling scheme as follows: on the basis of the benchmark PDN decoupling scheme, each decoupling optimization scheme in the optimization scheme set is applied to the ADS software to optimize the decoupling of the digital system power supply established in the ADS software; the mounting PCB optimization decoupling index and the microsystem substrate optimization decoupling index are respectively obtained, the mounting PCB optimization decoupling index is used to quantify the decoupling effect of the mounting PCB of the digital system power supply after the decoupling optimization scheme optimizes the benchmark PDN decoupling scheme, and the microsystem substrate optimization decoupling index is used to quantify the decoupling effect of the microsystem substrate of the digital system power supply after the decoupling optimization scheme optimizes the benchmark PDN decoupling scheme; the mounting PCB optimization decoupling index and the microsystem substrate optimization decoupling index are processed to obtain the optimization scheme evaluation index, and the optimization scheme evaluation index is used to quantify the decoupling effect of each decoupling optimization scheme on the digital system power supply after optimizing the benchmark PDN decoupling scheme; the decoupling optimization scheme corresponding to the maximum optimization scheme evaluation index among the calculated optimization scheme evaluation indexes is marked as the optimal PDN decoupling scheme.

[0064] The calculation formula of the optimization scheme evaluation index is as follows: OsE=β1*SOD+β2*MSO; where OsE is the optimization scheme evaluation index, SOD is the PCB mounting optimization decoupling index, MSO is the microsystem substrate optimization decoupling index, β1 is the weight factor of the PCB mounting optimization decoupling index, β2 is the weight factor of the microsystem substrate optimization decoupling index, and β1+β2=1.

[0065] In this implementation, each decoupling optimization solution in the optimization solution set is applied to the benchmark PDN decoupling solution one by one, which means improving the benchmark solution in the hope of obtaining better performance. Using ADS software, the established digital system power supply is optimized for decoupling simulation, including adjusting the component values, layout or connections in the power distribution network to achieve a better decoupling effect.

[0066] The optimized decoupling indexes of the optimized mounting PCB and microsystem substrate are obtained respectively to quantify the decoupling effect of the decoupling optimization scheme on the mounting PCB and microsystem substrate of the digital system power supply. By comparing the maximum values ​​of the evaluation indexes of each optimization scheme calculated, the corresponding decoupling optimization scheme is found and marked as the optimal PDN decoupling scheme.

[0067] The calculated optimization scheme evaluation index can be used to quantitatively evaluate the improvement effect of each optimization scheme on the baseline PDN decoupling scheme. By introducing the weight factor, the weight of the optimization effects of both the mounted PCB and the microsystem substrate in the overall evaluation can be adjusted according to specific needs, thereby improving the applicability of the method.

[0068] Specifically, the calculation process of the optimized decoupling index of the mounted PCB is as follows: the actual impedance curve after optimization of the mounted PCB and the impedance requirement curve of the mounted PCB are obtained, and several segments of the optimized actual impedance curve in the actual impedance curve after optimization of the mounted PCB are intercepted in the same way as the calculation of the decoupling index of the mounted PCB. The optimized actual impedance of several sampling points is obtained in each segment of the optimized actual impedance curve. The mounted PCB impedance requirement curve is sampled with reference to the sampling points of the optimized actual impedance, and the mounted PCB required impedance corresponding to the optimized actual impedance is obtained. The calculation formula is: c is the number of the actual impedance curve segment after optimization, c = 1, 2, 3, ..., C, C is the total number of the actual impedance curve segment after optimization, d is the number of the sampling points in each segment of the actual impedance curve after optimization, d = 1, 2, 3, ..., D, D is the total number of sampling points in each segment of the actual impedance curve after optimization, Ypz cd is the optimized actual impedance of the dth sampling point in the cth segment of the optimized actual impedance curve, Qpz cd is the required impedance of the mounted PCB corresponding to the optimized actual impedance of the dth sampling point in the cth segment of the actual impedance curve after optimization, and ΔYQ is the allowable deviation between the optimized actual impedance and the required impedance of the mounted PCB.

[0069] In this embodiment, after optimization, the actual impedance curve of the mounted PCB and the impedance requirement curve are obtained, and these two curves reflect the difference between the actual impedance and the design requirement. Similar to the previous process, several segments of the actual impedance curve after optimization are selected to meet specific areas of system performance concern, which helps to focus on the performance within the critical frequency range.

[0070] For each selected section of the actual impedance curve after optimization, sampling is performed to obtain the actual impedance after optimization at several sampling points. This step is to discretize the actual impedance curve to facilitate subsequent comparison and calculation. The impedance requirement curve is sampled with reference to the sampling points of the actual impedance after optimization to obtain the required impedance of the mounted PCB corresponding to the actual impedance after optimization. This step is to compare the difference between the actual impedance and the design requirement.

[0071] The sampling points are compared and fused. The optimized decoupling index of the mounted PCB is calculated, which combines the difference between the actual impedance and the design requirements. The calculated optimized decoupling index of the mounted PCB can quantitatively evaluate the difference between the optimized mounted PCB impedance curve and the design requirements, that is, the improvement of the decoupling effect. By processing each sampling point, the decoupling effects of multiple frequency points are combined, rather than just considering the performance of a single frequency point, which helps to fully understand the performance of the system in different frequency ranges.

[0072] Specifically, the calculation process of the microsystem substrate optimization decoupling index is as follows: obtain the actual impedance curve of the microsystem substrate after optimization and the impedance requirement curve of the microsystem substrate, and use the same method as the calculation of the microsystem substrate decoupling index to intercept several segments of the optimized actual impedance curve in the microsystem substrate after optimization, obtain the optimized actual impedance of several sampling points in each optimized actual impedance curve segment, sample the microsystem substrate impedance requirement curve with reference to the sampling points of the optimized actual impedance, and obtain the microsystem substrate required impedance corresponding to the optimized actual impedance. The calculation formula is: Where, e is the number of the actual impedance curve segment after optimization, e = 1, 2, 3, ..., E, E is the total number of the actual impedance curve segment after optimization, f is the number of the sampling points in each segment of the actual impedance curve after optimization, f = 1, 2, 3, ..., F, F is the total number of sampling points in each segment of the actual impedance curve after optimization, Ypw ef is the optimized actual impedance of the fth sampling point in the eth segment of the optimized actual impedance curve, Qpw ef is the required impedance of the mounted PCB corresponding to the optimized actual impedance of the fth sampling point in the eth segment of the actual impedance curve after optimization, and ΔYQw is the allowable deviation between the optimized actual impedance and the required impedance of the microsystem substrate.

[0073] In this embodiment, after optimization, the actual impedance curve and the impedance requirement curve of the microsystem substrate are obtained, and the two curves reflect the difference between the actual impedance and the design requirement. Similar to the previous process, several segments of the actual impedance curve after optimization are selected to meet specific areas of system performance concern, which helps to focus on the performance within the critical frequency range.

[0074] For each selected section of the actual impedance curve after optimization, sampling is performed to obtain the actual impedance after optimization at several sampling points. This step is to discretize the actual impedance curve to facilitate subsequent comparison and calculation. The impedance requirement curve is sampled with reference to the sampling points of the actual impedance after optimization to obtain the required impedance of the microsystem substrate corresponding to the actual impedance after optimization. This step is to compare the difference between the actual impedance and the design requirement.

[0075] The sampling points are compared and fused. The microsystem substrate optimization decoupling index is calculated, which integrates the degree of difference between the actual impedance and the design requirements. The calculated microsystem substrate optimization decoupling index can quantitatively evaluate the difference between the optimized microsystem substrate impedance curve and the design requirements, that is, the improvement of the decoupling effect. By adjusting ΔYQw, the allowable range of the difference between the actual impedance and the design requirements can be adjusted according to specific needs, which improves the applicability of the method.

[0076] An optimization system for the impedance of a power distribution network in a digital system, such as Figure 2 As shown, it includes a decoupling scheme matching module, a benchmark scheme determination module, an optimization scheme matching module and an optimal decoupling scheme determination module, wherein: the decoupling scheme matching module is used to match a PDN decoupling scheme set for distributing network impedance based on the acquired parasitic parameters of the digital system power supply, and the PDN decoupling scheme set includes several PDN decoupling schemes for distributing network impedance; the benchmark scheme determination module is used to use the matched PDN decoupling scheme set to decouple the mounted PCB and the microsystem substrate of the digital system power supply respectively, and determine the PDN decoupling scheme with the best decoupling effect in the PDN decoupling scheme set as the benchmark PDN decoupling scheme; the optimization scheme matching module is used to obtain an optimization scheme set based on the effect of the benchmark PDN decoupling scheme on the digital system power distribution network impedance, and the optimization scheme set includes several initial decoupling optimization schemes for optimizing the benchmark PDN decoupling scheme; the optimal decoupling scheme determination module is used to optimize the benchmark PDN decoupling scheme using the matched initial optimization scheme set to obtain the optimal PDN decoupling scheme.

[0077] In this implementation, the decoupling scheme matching module obtains the parasitic parameters of the digital system power supply. Based on the matching principle, this module constructs a PDN decoupling scheme set. These schemes are matched according to the parasitic parameters of the digital system power supply to meet the network impedance distribution requirements, providing a basis for the subsequent determination and optimization of the benchmark scheme.

[0078] The benchmark scheme determination module uses the PDN decoupling scheme set obtained by the decoupling scheme matching module and applies them to the mounted PCB and microsystem substrate of the digital system power supply, evaluates the decoupling effect, and determines the best PDN decoupling scheme as the benchmark PDN decoupling scheme. Through practical application and evaluation, the benchmark PDN decoupling scheme with the best performance in the actual system is found, providing a reference for subsequent optimization.

[0079] Based on the benchmark PDN decoupling scheme, the optimization scheme matching module constructs a set of initial decoupling optimization schemes through matching and optimization, aiming to further improve the performance based on the benchmark PDN decoupling scheme. It provides a series of initial decoupling optimization schemes, which are expected to achieve better performance and make the system more stable through further matching and adjustment based on the benchmark PDN decoupling scheme.

[0080] The optimal decoupling solution determination module uses the initial optimization solution set obtained through matching to further optimize the benchmark PDN decoupling solution and finally determines the optimal PDN decoupling solution. Through iterative optimization, the PDN decoupling solution with the best performance in all aspects is found, thereby improving the overall performance of the impedance of the digital system power distribution network.

[0081] An electronic device comprises: a processor; and a memory, wherein computer program instructions are stored in the memory, and when the computer program instructions are executed by the processor, the processor executes the above-mentioned method for optimizing the impedance of a power distribution network of a digital system.

[0082] A computer-readable storage medium is used to store a program, and when the program is executed by a processor, the above-mentioned method for optimizing the impedance of a power distribution network of a digital system is implemented.

[0083] In summary, this application has at least the following effects:

[0084] By matching the obtained PDN decoupling solution set and optimization solution set, the parasitic parameters of the digital system power supply, the decoupling requirements of the mounted PCB and the microsystem substrate are comprehensively considered, thus providing a comprehensive optimization solution. The collaborative decoupling method of the substrate and PCB decoupling capacitor network is adopted to solve the contradiction between the limited internal space of the microsystem and the large demand for decoupling capacitors, which helps to achieve effective management of power integrity in a limited space.

[0085] Through the matching coefficient, decoupling index and optimization scheme evaluation index obtained by matching, a series of quantitative methods are used to evaluate and optimize the decoupling scheme, which makes the entire optimization process more scientific and controllable. Through the optimized decoupling scheme, especially the optimization on the mounting PCB and microsystem substrate, the impedance matching and power integrity of the digital system power distribution network are effectively improved, which helps to reduce power noise and improve system performance.

[0086] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] The present invention is described with reference to flowcharts and / or block diagrams of systems, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1A device that provides the functions specified in a block or multiple blocks.

[0088] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0089] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0090] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0091] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for optimizing impedance of a power distribution network of a digital system, characterized in that: The following steps are involved: Matching a PDN decoupling scheme set for distributing network impedance based on the acquired parasitic parameters of the digital system power supply, wherein the PDN decoupling scheme set includes a plurality of PDN decoupling schemes for distributing network impedance; The matched PDN decoupling scheme set is used to decouple the mounting PCB and microsystem substrate of the digital system power supply respectively, and the PDN decoupling scheme with the best decoupling effect in the PDN decoupling scheme set is determined as the benchmark PDN decoupling scheme; An optimization solution set is obtained based on the effect matching of the benchmark PDN decoupling solution on the impedance of the digital system power distribution network, wherein the optimization solution set includes a plurality of decoupling optimization solutions for optimizing the benchmark PDN decoupling solution; The benchmark PDN decoupling solution is optimized by using the optimized solution set obtained by matching to obtain the optimal PDN decoupling solution; The process of using the matched PDN decoupling solution set to decouple the mounted PCB and the microsystem substrate of the digital system power supply and determining the PDN decoupling solution with the best decoupling effect in the PDN decoupling solution set as the benchmark PDN decoupling solution is as follows: Apply each PDN decoupling solution in the PDN decoupling solution set to the ADS software to decouple the digital system power supply established in the ADS software; Respectively obtain a mounted PCB decoupling index and a microsystem substrate decoupling index, wherein the mounted PCB decoupling index is used to quantify the decoupling effect of the PDN decoupling scheme on the mounted PCB of the digital system power supply, and the microsystem substrate decoupling index is used to quantify the decoupling effect of the PDN decoupling scheme on the microsystem substrate of the digital system power supply; The obtained mounted PCB decoupling index and microsystem substrate decoupling index are fused and calculated to obtain a PDN decoupling index, which is used to quantify the effect of each PDN decoupling scheme in the PDN decoupling scheme set on the impedance of the digital system power distribution network, and is used as a basis for matching to obtain an optimized scheme set; The PDN decoupling scheme corresponding to the maximum PDN decoupling indicator among the calculated PDN decoupling indicators is marked as the benchmark PDN decoupling scheme.

2. The method for optimizing the impedance of a digital system power distribution network according to claim 1, characterized in that: The parasitic parameters of the digital system power supply include parasitic inductance, parasitic resistance and parasitic capacitance. The process of matching the PDN decoupling solution set for allocating network impedance based on the acquired parasitic parameters of the digital system power supply is as follows: Acquire parasitic matching parameters of a digital system power supply stored in a decoupling solution database, wherein the parasitic matching parameters of the digital system power supply include parasitic matching inductance, parasitic matching resistance, and parasitic matching capacitance; The decoupling scheme matching coefficient is obtained based on the parasitic matching parameters and parasitic parameter calculations; Compare the decoupling scheme matching coefficients with the decoupling scheme coefficient matching intervals stored in the decoupling scheme database one by one; Obtain the PDN decoupling solution set corresponding to the successfully matched decoupling solution coefficient matching interval.

3. The method for optimizing the impedance of a digital system power distribution network according to claim 2, characterized in that: The calculation formula of the decoupling scheme matching coefficient is as follows: Wherein, DsC is the matching coefficient of the decoupling scheme, Jg is the parasitic inductance, CJg is the parasitic matching inductance, ΔDG is the allowable deviation value of inductance matching, Jr is the parasitic capacitance, CJr is the parasitic matching capacitance, ΔDR is the allowable deviation value of capacitance matching, Jz is the parasitic resistance, CJz is the parasitic matching resistance, ΔDZ is the allowable deviation value of resistance matching, α1 is the parasitic inductance matching weight factor, α2 is the parasitic capacitance matching weight factor, α3 is the parasitic resistance matching weight factor, and α1+α2+α3=1.

4. The method for optimizing impedance of a digital system power distribution network according to claim 1, characterized in that: The process of obtaining the mounted PCB decoupling index and the microsystem substrate decoupling index is as follows: Based on the set requirements, obtain the impedance requirement curve of the mounted PCB after the digital system power supply is decoupled and the impedance requirement curve of the microsystem substrate; According to each PDN decoupling scheme in the PDN decoupling scheme set and the parasitic parameters of the digital system power supply, an expected impedance curve of the mounted PCB and an expected impedance curve of the microsystem substrate after decoupling of the digital system power supply stored in the decoupling scheme database are obtained; Obtaining an actual impedance curve of a mounted PCB and an actual impedance curve of a microsystem substrate after each PDN decoupling scheme in a PDN decoupling scheme set is applied in the ADS software to decouple a digital system power supply established in the ADS software; Analyze the PCB impedance requirement curve, PCB impedance expected curve and PCB impedance actual curve to obtain the PCB decoupling index; The microsystem substrate decoupling index is obtained by analyzing the microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve.

5. The method for optimizing the impedance of a digital system power distribution network according to claim 4, characterized in that: The process of analyzing the required impedance curve of the mounted PCB, the expected impedance curve of the mounted PCB, and the actual impedance curve of the mounted PCB to obtain the decoupling index of the mounted PCB is as follows: Intercept several sections of the PCB impedance requirement curve, sample each section of the requirement curve, and obtain the PCB impedance requirement at each sampling point; For each sampling point where impedance is required, respectively obtain the expected impedance of the mounted PCB and the actual impedance of the mounted PCB; The required impedance of the mounted PCB, the expected impedance of the mounted PCB and the actual impedance of the mounted PCB are integrated to obtain the decoupling index of the mounted PCB.

6. The method for optimizing impedance of a digital system power distribution network according to claim 4, characterized in that: Analyze the microsystem substrate impedance requirement curve, the microsystem substrate impedance expected curve and the microsystem substrate impedance actual curve to obtain the microsystem substrate decoupling index: intercepting several sections of the microsystem substrate impedance requirement curve, sampling each section of the requirement curve, and obtaining the microsystem substrate required impedance at each sampling point; For each sampling point where impedance is required, respectively obtaining an expected impedance curve of a microsystem substrate and an actual impedance curve of a microsystem substrate to obtain an expected impedance of the microsystem substrate and an actual impedance of the microsystem substrate; The microsystem substrate required impedance, the microsystem substrate expected impedance and the microsystem substrate actual impedance are fused to obtain the microsystem substrate decoupling index.

7. The method for optimizing impedance of a digital system power distribution network according to claim 1, characterized in that: The process of optimizing the benchmark PDN decoupling solution by using the matched optimization solution set to obtain the optimal PDN decoupling solution is as follows: Based on the baseline PDN decoupling solution, each decoupling optimization solution in the optimization solution set is applied to the ADS software to optimize the decoupling of the digital system power supply established in the ADS software; Obtaining a mounted PCB optimization decoupling index and a microsystem substrate optimization decoupling index respectively, wherein the mounted PCB optimization decoupling index is used to quantify the decoupling effect of the mounted PCB of the digital system power supply after the decoupling optimization scheme optimizes the benchmark PDN decoupling scheme, and the microsystem substrate optimization decoupling index is used to quantify the decoupling effect of the microsystem substrate of the digital system power supply after the decoupling optimization scheme optimizes the benchmark PDN decoupling scheme; The mounted PCB optimization decoupling index and the microsystem substrate optimization decoupling index are processed to obtain an optimization scheme evaluation index, which is used to quantify the decoupling effect of each decoupling optimization scheme on the digital system power supply after optimizing the benchmark PDN decoupling scheme; The decoupling optimization scheme corresponding to the maximum optimization scheme evaluation index among the calculated optimization scheme evaluation indexes is marked as the optimal PDN decoupling scheme.

8. The method for optimizing impedance of a digital system power distribution network according to claim 7, characterized in that: The calculation formula of the optimization scheme evaluation index is as follows: OsE=β1*SOD+β2*MSO; Wherein, OsE is the optimization scheme evaluation index, SOD is the PCB mounting optimization decoupling index, MSO is the microsystem substrate optimization decoupling index, β1 is the weight factor of the PCB mounting optimization decoupling index, β2 is the weight factor of the microsystem substrate optimization decoupling index, and β1+β2=1.

9. A system using the method for optimizing the impedance of a power distribution network of a digital system as claimed in any one of claims 1 to 8, characterized in that: It includes a decoupling scheme matching module, a benchmark scheme determination module, an optimization scheme matching module and an optimal decoupling scheme determination module, wherein: The decoupling scheme matching module is used to match a PDN decoupling scheme set for distributing network impedance based on the acquired parasitic parameters of the digital system power supply, and the PDN decoupling scheme set includes a plurality of PDN decoupling schemes for distributing network impedance; The benchmark solution determination module is used to use the matched PDN decoupling solution set to decouple the mounted PCB and the microsystem substrate of the digital system power supply respectively, and determine the PDN decoupling solution with the best decoupling effect in the PDN decoupling solution set as the benchmark PDN decoupling solution; The optimization scheme matching module is used to obtain an optimization scheme set based on the effect matching of the benchmark PDN decoupling scheme on the impedance of the digital system power distribution network, and the optimization scheme set includes several primary decoupling optimization schemes for optimizing the benchmark PDN decoupling scheme; the optimal decoupling scheme determination module is used to optimize the benchmark PDN decoupling scheme by using the primary optimization scheme set obtained by matching to obtain the optimal PDN decoupling scheme.

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