Verification method and verification circuit for display driving circuit

Abstract

The present application provides a verification method and a verification circuit for a display driving circuit. The verification method for the display driving circuit, in response to receiving image data to be verified, outputs multiple parallel sub-pixel data based on the received image data; based on the bit order of each parallel sub-pixel data, converts each parallel sub-pixel data into serial sub-pixel data; based on a preset bit width, splices multiple serial sub-pixel data into multiple groups of parallel verification data; obtains a timing signal, and sends each group of parallel verification data to a logic analyzer based on the timing signal for data verification. The technical solution provided by the present application can use a relatively small number of pins to fully verify the digital circuit of each sub-pixel, effectively reducing the verification cost and verification difficulty, improving the verification efficiency, and improving the user experience.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a verification method and a verification circuit for a display driving circuit. Background Art

[0002] The source driver circuit is a circuit that converts the multi-bit digital signal corresponding to the sub-pixel into an analog signal and outputs it to the display panel. It is also called a column driver circuit or a data driver circuit. It is an indispensable part of the display driver circuit of an LCD panel or an OLED panel. In the display industry, there are different peripheral circuit solutions for different types of panels and panels with different resolutions. The source driver circuit may be independent of the timing control circuit and the gate driver circuit, or the three may be integrated together to form a DDIC (Display Driver Integrated Circuit).

[0003] In the process of conceiving and realizing the present application, the inventors found that there are at least the following problems: during the verification of the source driver circuit, since the number of DACs in the source driver circuit is usually in the order of hundreds to thousands depending on the size of the panel it is facing, it is necessary to observe so many groups of multi-bit signals, and the verification cost is too high; and signal observation tools such as logic analyzers are difficult to observe parallel signals of such a magnitude, the verification for verifiers is difficult and the verification efficiency is low, which often results in incomplete verification of the circuit, easy omissions, and difficulty in fault location when problems are encountered. Summary of the invention

[0004] In order to alleviate the above problems, the present application provides a verification method for a display driving circuit, comprising:

[0005] In response to receiving image data to be verified, outputting multiple parallel sub-pixel data based on the received image data;

[0006] Based on the bit order of each parallel sub-pixel data, convert each parallel sub-pixel data into serial sub-pixel data;

[0007] Based on a preset bit width, multiple channels of serial sub-pixel data are spliced ​​into multiple groups of parallel verification data;

[0008] A timing signal is acquired, and each group of parallel verification data is sent to a logic analyzer based on the timing signal to perform data verification.

[0009] Optionally, in response to receiving image data to be verified, in the process of outputting multiple channels of parallel sub-pixel data based on the received image data, the image data is collected after the input sub-pixel data is updated and remains stable.

[0010] Optionally, in the process of converting each parallel sub-pixel data into serial sub-pixel data based on the bit order of each parallel sub-pixel data, a set of identical multi-bit reference information is also input to combine the pixel information and the reference information to perform a parallel-to-serial operation.

[0011] Optionally, the process of splicing multiple channels of serial sub-pixel data into multiple groups of parallel verification data based on a preset bit width includes: obtaining the number of groups of parallel verification data according to the total number of pixels of the image data to be verified and the bit width of each group of input data.

[0012] Optionally, a timing signal is acquired, and in the process of sending each set of parallel verification data to a logic analyzer based on the timing signal, different verification data groups are cyclically switched when a single set of serial sub-pixel data is not missing, so as to completely display all image data within one line of time.

[0013] Optionally, the timing signal is generated based on register configuration data, or the timing signal is generated based on a timing control circuit.

[0014] Optionally, the timing signal is generated based on a counter in a process of being generated based on a timing control circuit according to a clock frequency, an image line frequency, a sub-pixel data bit width and a data bit width of reference information.

[0015] Optionally, the display driving circuit verification method further includes:

[0016] According to the requirements of the data bridge chip, the image data is converted into corresponding timing output, so that the data bridge chip transmits the data to the display screen.

[0017] The present application also provides a verification circuit of a display driving circuit, which is used to implement the verification method of the display driving circuit as described above, and the verification circuit of the display driving circuit includes:

[0018] A source control circuit outputs multiple parallel sub-pixel data based on received image data;

[0019] A plurality of parallel-to-serial circuits, each of which receives one channel of parallel sub-pixel data respectively, so as to convert each channel of parallel sub-pixel data into serial sub-pixel data;

[0020] A splicing circuit splices multiple serial sub-pixel data into multiple sets of parallel verification data based on a preset bit width;

[0021] The first data selector circuit receives multiple groups of parallel verification data and sends each group of parallel verification data to a logic analyzer for data verification based on a timing signal.

[0022] Optionally, the verification circuit of the display driving circuit also includes a second data selector circuit, a first input end of the second data selector circuit is connected to a register, a second input end of the second data selector circuit is connected to a timing control circuit, and a third input end of the second data selector circuit is connected to the first data selector circuit to output the timing signal.

[0023] The verification method and verification circuit of the display driving circuit provided in the present application respond to receiving image data to be verified, output multiple parallel sub-pixel data based on the received image data; convert each parallel sub-pixel data into serial sub-pixel data based on the bit sequence of each parallel sub-pixel data; splice the multiple serial sub-pixel data into multiple groups of parallel verification data based on a preset bit width; obtain a timing signal, and send each group of parallel verification data to a logic analyzer based on the timing signal for data verification; and can use a smaller number of pins to fully verify the digital circuit of each sub-pixel, effectively reducing the verification cost and verification difficulty, improving the verification efficiency, and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0025] Figure 1 This is a flow chart of a verification method for a display driving circuit according to an embodiment of the present application.

[0026] Figure 2 FIG. 4 is a block diagram of a verification circuit of a display driving circuit according to an embodiment of the present application.

[0027] Figure 3 This is a schematic diagram of the connection of a verification circuit according to an embodiment of the present application.

[0028] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0029] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0030] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0031] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0032] First embodiment

[0033] In one aspect, the present application provides a verification method for a display driving circuit. Figure 1 This is a flow chart of a verification method for a display driving circuit according to an embodiment of the present application.

[0034] like Figure 1 As shown, in one embodiment, a verification method of a display driving circuit includes:

[0035] S10: In response to receiving image data to be verified, outputting multiple channels of parallel sub-pixel data based on the received image data.

[0036] In the verification of the source drive circuit, one digital-to-analog conversion circuit corresponds to the digital-to-analog conversion of one sub-pixel data. Here, the input digital signal is a parallel signal, and its bit width may be 8, 10 or 12 bits, etc. The number of digital-to-analog conversions required in the source drive circuit is usually on the order of hundreds to thousands depending on the size of the panel it is facing.

[0037] S20: Convert each path of parallel sub-pixel data into serial sub-pixel data based on the bit sequence of each path of parallel sub-pixel data.

[0038] The input and output data of the source driving circuit will only be updated once in each line of the image display, so the time margin between data updates is very large. For example, a parallel-to-serial circuit is used in the FPGA equivalent circuit for processing.

[0039] S30: Based on a preset bit width, splice multiple channels of serial sub-pixel data into multiple groups of parallel verification data.

[0040] Exemplarily, a plurality of serial data may be assembled into a group of parallel data, and the data bit width is determined according to actual conditions, such as 32, 48 or 64.

[0041] S40: Acquire a timing signal, and send each group of parallel verification data to a logic analyzer based on the timing signal to perform data verification.

[0042] A logic analyzer is an instrument for analyzing the logical relationships of digital systems. A logic analyzer is a type of bus analyzer that belongs to the category of data domain test instruments. That is, an instrument that is based on the concept of a bus (multi-line) and simultaneously observes and tests the data streams on multiple data lines. This instrument is very effective for testing and analyzing complex digital systems. A logic analyzer is an instrument that uses a clock to collect and display digital signals from a test device. Its main function is to determine the timing. For example, by observing each set of parallel data signals with a logic analyzer and verifying and analyzing the effect of the source drive circuit, the need to observe large orders of magnitude of parallel signals can be realized in sequence according to the timing signals.

[0043] The verification method and verification circuit of the display driving circuit provided in the present application respond to receiving image data to be verified, output multiple parallel sub-pixel data based on the received image data; convert each parallel sub-pixel data into serial sub-pixel data based on the bit sequence of each parallel sub-pixel data; splice the multiple serial sub-pixel data into multiple groups of parallel verification data based on a preset bit width; obtain a timing signal, and send each group of parallel verification data to a logic analyzer based on the timing signal for data verification; and can use a smaller number of pins to fully verify the digital circuit of each sub-pixel, effectively reducing the verification cost and verification difficulty, improving the verification efficiency, and improving the user experience.

[0044] Optionally, in response to receiving image data to be verified, in the process of outputting multiple channels of parallel sub-pixel data based on the received image data, the image data is collected after the input sub-pixel data is updated and remains stable.

[0045] Exemplarily, in the parallel-to-serial circuit, the input sub-pixel data is collected into the register after being updated and kept stable.

[0046] Optionally, in the process of converting each parallel sub-pixel data into serial sub-pixel data based on the bit order of each parallel sub-pixel data, a set of identical multi-bit reference information is also input to combine the pixel information and the reference information to perform a parallel-to-serial operation.

[0047] Exemplarily, the register output and the input reference information data are spliced ​​together and input into a shift register array for serial output, so as to obtain the serial output data of a single sub-pixel source.

[0048] Optionally, the process of splicing multiple channels of serial sub-pixel data into multiple groups of parallel verification data based on a preset bit width includes: obtaining the number of groups of parallel verification data according to the total number of pixels of the image data to be verified and the bit width of each group of input data.

[0049] Each group of input data can correspond to a data channel of the data selector. Exemplarily, multiple serial data are assembled into a group of parallel data, and the data bit width can be determined according to the actual situation, such as 32, 48 or 64, etc., and connected to the input end of the data selector. The number of input channels of the data selector can be obtained by dividing the total number of sources to be verified by the bit width of each group of input data.

[0050] Optionally, a timing signal is acquired, and in the process of sending each set of parallel verification data to a logic analyzer based on the timing signal, different verification data groups are cyclically switched when a single set of serial sub-pixel data is not missing, so as to completely display all image data within one line of time.

[0051] Since the input and output data of the source driver are only updated once in each line of the image display, the time margin between data updates is very large. Exemplarily, the selection signal is passed through a set of timing control circuits to cyclically switch different data paths without missing a single set of source driver serial signals, so as to achieve the purpose of fully displaying all source driver signal data within one line of time. The selection signal can also be configured and selected through a register.

[0052] Optionally, the timing signal is generated based on register configuration data, or the timing signal is generated based on a timing control circuit.

[0053] Exemplarily, during the process of the data selector selecting multiple groups of input data to be output to the data analyzer, the selection control terminal of the data selector is connected to the output terminal of another two-selection data selector, that is, the output selection of the source drive signal data can be achieved in two ways, one is that the verification personnel actively configures the selection through the host computer, and the other is through the timing control circuit.

[0054] Optionally, the timing signal is generated based on a counter in a process of being generated based on a timing control circuit according to a clock frequency, an image line frequency, a sub-pixel data bit width and a data bit width of reference information.

[0055] Exemplarily, the timing control circuit generates a control signal based on a counter according to information such as clock frequency, image line frequency, sub-pixel data bit width, and reference information data bit width, so as to switch the source output data.

[0056] Optionally, the display driving circuit verification method further includes:

[0057] According to the requirements of the data bridge chip, the image data is converted into corresponding timing output, so that the data bridge chip transmits the data to the display screen.

[0058] For example, when using an FPGA chip for signal processing conversion, an image data bridge chip can be built outside the FPGA chip to the display driver chip and then to the screen point screen system. The data bridge chip supports the conversion of input image data of multiple simple protocols into data output that meets the protocol required by the subsequent display driver chip. Therefore, a timing conversion circuit can be added to the FPGA to configure the input image data timing of the source control circuit to meet the protocol timing of the bridge chip input, thus completing the image display. The digital signal on the logic analyzer corresponds to the screen image in real time for analysis and verification.

[0059] Second embodiment

[0060] The present application also provides a verification circuit for a display driving circuit, which is used to implement the verification method for the display driving circuit as described above. Figure 2 FIG. 4 is a block diagram of a verification circuit of a display driving circuit according to an embodiment of the present application.

[0061] like Figure 2 As shown, in one embodiment, the verification circuit of the display driving circuit includes:

[0062] A source control circuit 1 outputs multiple parallel sub-pixel data based on received image data;

[0063] A plurality of parallel-to-serial circuits 2, each of which receives one channel of parallel sub-pixel data respectively, so as to convert each channel of parallel sub-pixel data into serial sub-pixel data;

[0064] A splicing circuit 3 splices multiple serial sub-pixel data into multiple sets of parallel verification data based on a preset bit width;

[0065] The first data selector circuit 4 receives multiple groups of parallel verification data, and sends each group of parallel verification data to the logic analyzer for data verification based on the timing signal.

[0066] For example, because the input and output data of the source (source driver) will only be updated once in each row of the image display, the time margin between data updates is very large. Therefore, in order to save the number of FPGA pins and reduce the high cost of selecting a high-performance FPGA, in this application, the DAC (digital-to-analog converter) is replaced with a parallel-to-serial circuit in the FPGA equivalent circuit.

[0067] Although the number of signals after parallel-to-serial conversion is significantly reduced, there will still be hundreds or thousands of signal outputs depending on the source drive circuits of different resolution panels. Therefore, a data selector is added to the back stage of the parallel-to-serial circuit, and the bit width of the selector data path is determined according to the actual verification environment. The selector's selection signal is passed through a set of timing control circuits to cyclically switch different data paths without missing a single set of source serial signals, so as to achieve the purpose of fully displaying all source data within one line of time. The selection signal can also be configured and selected through a register.

[0068] When there is sufficient time margin, in order to improve the comprehensiveness of the observation information and the efficiency of problem solving, in addition to the corresponding sub-pixel data, the input of each parallel-to-serial circuit can also input a set of identical multi-bit reference information according to the requirements of the verifier, and the pixel information and reference information are pieced together in the parallel-to-serial circuit to perform parallel-to-serial operations.

[0069] Based on the observation of signals using an external logic analyzer, the present invention converts the input image data of the source control circuit into corresponding timing output according to the requirements of the downstream data bridge chip, and sends it to the data bridge chip on the FPGA development board. The bridge chip then transmits the data to the panel driver chip, and finally displays the image on the screen. Verification personnel can conduct comprehensive multi-dimensional analysis and verification through the logic analyzer and the real image.

[0070] Please continue to refer to Figure 2 Optionally, the verification circuit of the display driving circuit also includes a second data selector circuit 5, the first input end of the second data selector circuit 2 is connected to the register, the second input end of the second data selector circuit is connected to the timing control circuit, and the third input end of the second data selector circuit is connected to the first data selector circuit 4 to output the timing signal.

[0071] Exemplarily, the selection control end of the first data selector is connected to the output end of another second data selector, that is, the output selection of the source can be realized in two ways, one is that the verification personnel actively configures the selection through the host computer, and the other is through the timing control circuit. The timing control circuit generates a control signal based on the counter according to information such as the clock frequency, the image line frequency, the sub-pixel data bit width, and the reference information data bit width, so as to realize the switching of the source output data.

[0072] Figure 3 This is a schematic diagram of the connection of a verification circuit according to an embodiment of the present application.

[0073] like Figure 3 As shown, exemplarily, the verification circuit includes a parallel-to-serial circuit, a timing control circuit, a multiplexer for source serial output data, a timing conversion circuit, and a data point screen system supporting the FPGA peripheral.

[0074] In the parallel-to-serial circuit, the input sub-pixel data is first collected into the register after being updated and kept stable, and then the register output and the input reference information data are spliced ​​together and input into the parallel-input-serial-output shift register array to obtain the serial output data of a single sub-pixel source.

[0075] Multiple serial data are assembled into a group of parallel data. The data bit width is determined according to the actual situation, such as 32, 48 or 64, and connected to the input end of the data selector. The number of input channels of the data selector can be obtained by dividing the total number of sources to be verified by the bit width of each group of input data.

[0076] The selection control end of the data selector is connected to the output end of another data selector that selects one of two options. That is, the output selection of the source can be realized in two ways. One is that the verification personnel actively configures the selection through the host computer, and the other is through the timing control circuit. The timing control circuit generates a control signal based on the counter according to the clock frequency, image line frequency, sub-pixel data bit width, and reference information data bit width, so as to realize the switching of the source output data.

[0077] The image data bridge chip is built outside the FPGA chip to the display driver chip and then to the screen point screen system. The data bridge chip supports the conversion of input image data of multiple simple protocols into data output that meets the protocol requirements of the subsequent display driver chip. Therefore, a timing conversion circuit is added to the FPGA to configure the input image data timing of the source control circuit to meet the protocol timing of the bridge chip input, thus completing the image display. The digital signal on the logic analyzer corresponds to the screen image in real time for analysis and verification.

[0078] In this embodiment, in the FPGA verification of the source driving circuit, the DAC is replaced by a parallel-to-serial circuit, and the circuit input contains additional reference information in addition to the sub-pixel data. The output of the parallel-to-serial circuit is automatically switched by the MUX cycle through the timing control circuit.

[0079] In this embodiment, in the FPGA verification of the source driving circuit, the display of multiple information (including all source data and additional reference data) on the logic analyzer and the verification of multiple dimensions (logic analyzer displays digital signals and screen displays images) at the same time are realized.

[0080] The verification method and verification circuit of the display driving circuit provided in the present application respond to receiving image data to be verified, output multiple parallel sub-pixel data based on the received image data; convert each parallel sub-pixel data into serial sub-pixel data based on the bit sequence of each parallel sub-pixel data; splice the multiple serial sub-pixel data into multiple groups of parallel verification data based on a preset bit width; obtain a timing signal, and send each group of parallel verification data to a logic analyzer based on the timing signal for data verification; and can use a smaller number of pins to fully verify the digital circuit of each sub-pixel, effectively reducing the verification cost and verification difficulty, improving the verification efficiency, and improving the user experience.

[0081] It is understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, it is known to those skilled in the art that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0082] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0083] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0084] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0085] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.

[0086] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0088] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for verifying a display driving circuit, characterized in that: include: In response to receiving image data to be verified, outputting multiple parallel sub-pixel data based on the received image data; Based on the bit order of each parallel sub-pixel data, convert each parallel sub-pixel data into serial sub-pixel data; Based on a preset bit width, multiple channels of serial sub-pixel data are spliced ​​into multiple groups of parallel verification data; Acquire a timing signal, and send each set of parallel verification data to a logic analyzer based on the timing signal for data verification; The process of splicing multiple serial sub-pixel data into multiple groups of parallel verification data based on the preset bit width includes: obtaining the number of groups of parallel verification data according to the total number of pixels of the image data to be verified and the bit width of each group of input data.

2. A display driving circuit verification method according to claim 1, characterized in that: In response to receiving the image data to be verified, in the process of outputting multiple channels of parallel sub-pixel data based on the received image data, the image data is collected after the input sub-pixel data is updated and remains stable.

3. The display driving circuit verification method according to claim 1, characterized in that: In the process of converting each parallel sub-pixel data into serial sub-pixel data based on the bit order of each parallel sub-pixel data, a set of identical multi-bit reference information is also input to combine the pixel information and the reference information to perform a parallel-to-serial operation.

4. The display driving circuit verification method according to claim 1, characterized in that: A timing signal is obtained, and in the process of sending each group of parallel verification data to a logic analyzer based on the timing signal, different verification data groups are cyclically switched when a single group of serial sub-pixel data is not missing, so as to completely display all image data within one line of time.

5. The display driving circuit verification method according to claim 1, characterized in that: The timing signal is generated based on register configuration data, or the timing signal is generated based on a timing control circuit.

6. A display driving circuit verification method according to claim 5, characterized in that: The timing signal is generated based on a counter in a process in which the timing control circuit generates the timing signal according to the clock frequency, the image line frequency, the sub-pixel data bit width and the data bit width of the reference information.

7. A display driving circuit verification method according to any one of claims 1 to 6, characterized in that: The verification method of the display driving circuit further includes: According to the requirements of the data bridge chip, the image data is converted into corresponding timing output, so that the data bridge chip transmits the data to the display screen.

8. A verification circuit for a display driving circuit, characterized in that: Used to implement the verification method of the display driving circuit according to any one of claims 1 to 7, the verification circuit of the display driving circuit comprises: A source control circuit outputs multiple parallel sub-pixel data based on received image data; A plurality of parallel-to-serial circuits, each of which receives one channel of parallel sub-pixel data respectively, so as to convert each channel of parallel sub-pixel data into serial sub-pixel data; A splicing circuit splices multiple serial sub-pixel data into multiple sets of parallel verification data based on a preset bit width; The first data selector circuit receives multiple groups of parallel verification data and sends each group of parallel verification data to a logic analyzer for data verification based on a timing signal.

9. The verification circuit of the display driving circuit according to claim 8, characterized in that: The verification circuit of the display driving circuit also includes a second data selector circuit, a first input end of the second data selector circuit is connected to a register, a second input end of the second data selector circuit is connected to a timing control circuit, and a third input end of the second data selector circuit is connected to the first data selector circuit to output the timing signal.

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