Fully Differential Class-AB Operational Amplifier Circuits and Systems

Abstract

The present invention provides a fully differential Class-AB operational amplifier circuit and system, wherein the error amplification module is used to receive the first common-mode level signal sent by the fully differential Class-AB output module, compare it with a preset reference signal, and output a comparison result; the bias voltage generation module is used to receive the comparison result, amplify it, and output a bias voltage signal; the fully differential Class-AB output module is used to receive the bias voltage signal to determine the differential output voltage of the fully differential Class-AB operational amplifier, and then determine the second common-mode level signal, and send the second common-mode level signal to the error amplification module to replace the first common-mode level signal. The circuit only needs one common-mode level signal feedback loop to achieve the stability of the common-mode level signal, which reduces power consumption, does not affect the stability of other differential mode loops, and ensures the common-mode response speed and accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fully differential Class-AB operational amplifier circuit and system. Background Art

[0002] For a fully differential high-gain amplifier, any slight current mismatch at its high-impedance output node can cause the output voltage to deviate toward the power supply or ground, completely disrupting the op amp's quiescent operating point and rendering it inoperable. Therefore, a common-mode feedback loop is required to stabilize the output common-mode level, ensuring the op amp's output has an optimal swing range. In the related art, there are generally two methods for achieving a satisfactory common-mode level. The first is to implement a common-mode feedback loop at each stage to ensure a normal common-mode level. This method requires multiple common-mode loops and error amplifiers, consumes significant power, and the large number of loops can easily affect the stability of other differential-mode loops. The second method is to reduce the gain of the common-mode feedback loop, moving the dominant pole closer to the origin to ensure a relatively good phase margin. However, this method sacrifices loop gain, Gain Band Width (GBW), and common-mode level offset, reducing the feedback speed and accuracy of the common-mode loop. Consequently, the related art lacks an effective solution for achieving a satisfactory common-mode level. Summary of the Invention

[0003] The present invention aims to provide a fully differential Class-AB operational amplifier circuit and system to achieve common-mode level signal stability, reduce power consumption, and not affect the stability of other differential-mode loops, while ensuring common-mode response speed and accuracy.

[0004] The present invention provides a fully differential Class-AB operational amplifier circuit, which includes: an error amplification module, configured to receive a first common-mode level signal sent by a fully differential Class-AB output module, compare the first common-mode level signal with a preset reference signal, and output a comparison result; a bias voltage generation module, configured to receive the comparison result, amplify the comparison result, and output a bias voltage signal; and a fully differential Class-AB output module, configured to receive the bias voltage signal, determine a differential output voltage of the fully differential Class-AB operational amplifier based on the bias voltage signal, determine a second common-mode level signal based on the differential output voltage, and send the second common-mode level signal to the error amplification module to replace the first common-mode level signal.

[0005] Furthermore, the error amplification module includes:

[0006] an error amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a preset reference signal, the second input terminal receives a first common-mode level signal sent by the fully differential Class-AB output module, and the error amplifier is configured to compare the first common-mode level signal with the preset reference signal and output a first result;

[0007] a first resistor having a first end and a second end, wherein the first end of the first resistor is connected to the output end of the error amplifier;

[0008] a first capacitor having a first end and a second end, the first end of the first capacitor being connected to the second end of the first resistor, and the second end of the first capacitor being connected to a power supply voltage;

[0009] The first resistor and the first capacitor are used to perform zero-pole compensation on the first result to obtain a comparison result.

[0010] Furthermore, the bias voltage generating module includes:

[0011] The first switch tube has a gate, a source, and a drain, wherein the source of the first switch tube is connected to the power supply voltage; and the gate of the first switch tube is connected to the output end of the error amplifier;

[0012] A second switch tube has a gate, a source, and a drain, the source of the second switch tube is connected to the power supply voltage, and the gate of the second switch tube is connected to the output end of the error amplifier;

[0013] a third switching tube having a gate, a source, and a drain, wherein the source of the third switching tube is connected to the drain of the first switching tube and the first output terminal of the previous stage circuit respectively; and the gate of the third switching tube receives a first bias signal provided by an external circuit;

[0014] a fourth switching transistor, comprising a gate, a source, and a drain, wherein the gate of the fourth switching transistor is connected to the gate of the third switching transistor, and the source of the fourth switching transistor is respectively connected to the drain of the second switching transistor and the second output terminal of the previous stage circuit; the first output terminal and the second output terminal of the previous stage circuit are used to output the differential signal output by the previous stage circuit;

[0015] a fifth switching tube having a gate, a source, and a drain, wherein the source of the fifth switching tube is connected to the drain of the third switching tube, and the gate of the fifth switching tube is connected to a second bias signal provided by an external circuit;

[0016] a sixth switching tube having a gate, a source, and a drain, wherein the drain of the sixth switching tube is connected to the source of the fifth switching tube, and the gate of the sixth switching tube is connected to a third bias signal provided by an external circuit;

[0017] A first current source has a first end and a second end, the first end of the first current source being connected to the drain of the fifth switching tube and the source of the sixth switching tube respectively; the second end of the first current source being grounded;

[0018] a seventh switching tube having a gate, a source, and a drain, wherein the source of the seventh switching tube is connected to the drain of the fourth switching tube, and the gate of the seventh switching tube is connected to the second bias signal;

[0019] an eighth switching tube having a gate, a source, and a drain, the drain of the eighth switching tube being connected to the source of the seventh switching tube, and the gate of the eighth switching tube being connected to the third bias signal;

[0020] The second current source has a first end and a second end. The first end of the second current source is connected to the drain of the seventh switch tube and the source of the eighth switch tube respectively; the second end of the second current source is grounded.

[0021] Furthermore, the fully differential Class-AB output module includes:

[0022] a ninth switching tube having a gate, a source, and a drain, wherein the source of the ninth switching tube is connected to the power supply voltage; and the gate of the ninth switching tube is connected to the drain of the third switching tube;

[0023] a tenth switching transistor, having a gate, a source, and a drain, wherein the drain of the tenth switching transistor is respectively connected to the drain of the ninth switching transistor and the first output terminal of the fully differential Class-AB output module, the gate of the tenth switching transistor is connected to the first terminal of the first current source, and the source of the tenth switching transistor is grounded;

[0024] a first RC unit having a first end and a second end, wherein the first end of the first RC unit is connected to the drain of the ninth switch tube, and the second end of the first RC unit is connected to the second input end of the error amplifier;

[0025] an eleventh switching tube having a gate, a source, and a drain, wherein the source of the eleventh switching tube is connected to a power supply voltage; and the gate of the eleventh switching tube is connected to the drain of the fourth switching tube;

[0026] a twelfth switching tube, comprising a gate, a source, and a drain, wherein the drain of the twelfth switching tube is respectively connected to the drain of the eleventh switching tube and the second output terminal of the fully differential Class-AB output module, the gate of the twelfth switching tube is connected to the first terminal of the second current source, and the source of the twelfth switching tube is grounded;

[0027] The second RC unit has a first end and a second end. The first end of the second RC unit is connected to the drain of the eleventh switch tube, and the second end of the second RC unit is connected to the second input end of the error amplifier.

[0028] Furthermore, the first resistance-capacitance unit includes:

[0029] a second resistor having a first end and a second end, the first end of the second resistor being connected to the drain of the ninth switch tube, and the second end of the second resistor being connected to the second input end of the error amplifier;

[0030] The second capacitor has a first end and a second end. The first end of the second capacitor is connected to the drain of the ninth switch tube, and the second end of the second capacitor is connected to the second input end of the error amplifier.

[0031] Furthermore, the second resistance-capacitance unit includes:

[0032] a third resistor having a first end and a second end, the first end of the third resistor being connected to the drain of the eleventh switch tube, and the second end of the third resistor being connected to the second input end of the error amplifier;

[0033] The third capacitor has a first end and a second end. The first end of the third capacitor is connected to the drain of the eleventh switch tube, and the second end of the third capacitor is connected to the second input end of the error amplifier.

[0034] Furthermore, the resistance value of the second resistor is the same as the resistance value of the third resistor.

[0035] Furthermore, the fully differential Class-AB output module includes:

[0036] a fourth resistor having a first end and a second end, wherein the first end of the fourth resistor is connected to the gate of the ninth switch tube;

[0037] a fourth capacitor having a first end and a second end, the first end of the fourth capacitor being connected to the second end of the fourth resistor, and the second end of the fourth capacitor being connected to the first output end of the fully differential Class-AB output module;

[0038] a fifth resistor having a first end and a second end, wherein the first end of the fifth resistor is connected to the gate of the eleventh switch tube;

[0039] The fifth capacitor has a first end and a second end, the first end of the fifth capacitor is connected to the second end of the fifth resistor, and the second end of the fifth capacitor is connected to the second output end of the fully differential Class-AB output module.

[0040] Furthermore, the error amplifier includes:

[0041] a thirteenth switching tube having a gate, a source, and a drain, the source of the thirteenth switching tube being connected to a power supply voltage, and the gate of the thirteenth switching tube being connected to the drain of the thirteenth switching tube;

[0042] a fourteenth switching tube having a gate, a source, and a drain, the source of the fourteenth switching tube being connected to a power supply voltage, and the gate of the fourteenth switching tube being connected to the gate of the thirteenth switching tube;

[0043] A fifteenth switching tube has a gate, a source, and a drain, the drain of the fifteenth switching tube being connected to the drain of the thirteenth switching tube; the gate of the fifteenth switching tube being connected to the first input terminal of the error amplifier;

[0044] A sixteenth switching tube has a gate, a source, and a drain, the drain of the sixteenth switching tube being connected to the drain of the fourteenth switching tube; the gate of the sixteenth switching tube being connected to the second input terminal of the error amplifier;

[0045] The third current source has a first end and a second end. The first end of the third current source is connected to the source of the fifteenth switch tube and the source of the sixteenth switch tube respectively; the second end of the third current source is grounded.

[0046] The present invention provides a fully differential Class-AB operational amplifier system, which includes: any one of the above-mentioned fully differential Class-AB operational amplifier circuits.

[0047] The fully differential Class-AB operational amplifier circuit and system provided by the present invention includes an error amplification module for receiving a first common-mode level signal sent by a fully differential Class-AB output module, comparing it with a preset reference signal, and outputting a comparison result. A bias voltage generation module is used to receive the comparison result, amplify it, and output a bias voltage signal. The fully differential Class-AB output module is used to receive the bias voltage signal to determine the differential output voltage of the fully differential Class-AB operational amplifier, thereby determining a second common-mode level signal. This second common-mode level signal is sent to the error amplification module to replace the first common-mode level signal. This circuit only requires a single common-mode level signal feedback loop to achieve common-mode level signal stability, reducing power consumption without affecting the stability of other differential-mode loops, while ensuring common-mode response speed and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 A schematic diagram of a fully differential Class-AB operational amplifier circuit provided by an embodiment of the present invention;

[0050] Figure 2 A schematic diagram of a fully differential Class-AB operational amplifier circuit provided by an embodiment of the present invention;

[0051] Figure 3 A circuit diagram of an error amplifier provided by an embodiment of the present invention.

[0052] Icons: 10-error amplifier module; 11-bias voltage generation module; 12-fully differential Class-AB output module; M5-first switch tube; M6-second switch tube; M7-third switch tube; M8-fourth switch tube; M9-fifth switch tube; M11-sixth switch tube; M10-seventh switch tube; M12-eighth switch tube; M1-ninth switch tube; M2-tenth switch tube; M3-eleventh switch tube; M4-twelfth switch tube; M13-thirteenth switch tube; M14-fourteenth switch tube; M15-fifteenth switch tube; M16-sixteenth switch tube; OP-error amplifier; R1-first resistor; C1-first capacitor; R2-second resistor; C2-second capacitor; R3-third resistor; C3-third capacitor; R4-fourth resistor; C4-fourth capacitor; R5-fifth resistor; C5-fifth capacitor; IB1-first current source; IB2-second current source; IB3-third current source. DETAILED DESCRIPTION

[0053] The technical solutions of the present invention are described clearly and completely below with reference to the embodiments. It is obvious that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0054] With advancements in CMOS process technology, reducing circuit power consumption has become a key focus of chip design research. Fully differential Class-AB amplifiers, whose dynamic current is not limited by their static current, can achieve high dynamic current while maintaining low power consumption, resulting in high performance. Consequently, they have attracted significant attention from chip front-end designers.

[0055] Full differential has many advantages, such as suppressing even harmonics and increasing output swing, but for high-gain amplifiers with a fully differential structure, any slight current mismatch at the high-impedance output node will cause the output voltage to deviate from the power supply or ground, completely destroying the static operating point of the op amp and making it unable to work properly. Therefore, a common-mode feedback loop is needed to stabilize the output common-mode level so that the output of the operational amplifier has the best swing range. Therefore, the stability and response speed of the common-mode feedback loop are crucial for fully differential operational amplifiers. Since the two-stage Class-AB output fully differential operational amplifier with floating current source bias has a high gain, the related technology lacks an effective solution in obtaining a common-mode level that meets the requirements. Based on this, an embodiment of the present invention provides a fully differential Class-AB operational amplifier circuit and system, which can be applied to applications that require common-mode feedback of Class-AB operational amplifiers, as well as other circuit applications that require common-mode feedback.

[0056] To facilitate understanding of this embodiment, a fully differential Class-AB operational amplifier circuit disclosed in an embodiment of the present invention is first introduced. Figure 1 As shown, the circuit includes: an error amplification module 10, a bias voltage generation module 11 and a fully differential Class-AB output module 12; the error amplification module 10 is used to receive a first common-mode level signal sent by the fully differential Class-AB output module, compare the first common-mode level signal with a preset reference signal, and output a comparison result; the bias voltage generation module 11 is used to receive the comparison result, amplify the comparison result, and output a bias voltage signal; the fully differential Class-AB output module 12 is used to receive the bias voltage signal, determine the differential output voltage of the fully differential Class-AB operational amplifier according to the bias voltage signal, determine a second common-mode level signal based on the differential output voltage, and send the second common-mode level signal to the error amplification module 10 to replace the first common-mode level signal.

[0057] The above-mentioned preset reference signal can be set according to actual needs. For example, the reference signal can be half of the power supply voltage VDD; the above-mentioned first common-mode level signal and the second common-mode level signal may be the same or different; in actual implementation, the above-mentioned error amplification module can be implemented based on the error amplifier, etc. The error amplification module can compare the first common-mode level signal fed back by the fully differential Class-AB output module with the preset reference signal to obtain a comparison result. For example, the comparison result can be used to indicate that the first common-mode level signal is greater than, less than or equal to the preset reference signal, etc.; the error amplification module can realize the first-stage amplification function; the comparison result is sent to the bias voltage generation module, and the bias voltage generation module performs a second-stage amplification on the comparison result, and can output a bias voltage signal and send it to the fully differential Class-AB output module. The fully differential Class-AB output module is divided into two parts. The bias voltage signal can provide a bias voltage for the switching tube in the fully differential Class-AB output module, thereby outputting the differential output voltage of the fully differential Class-AB operational amplifier through the fully differential Class-AB output module. The fully differential Class-AB output module can determine a second common-mode level signal based on the differential output voltage and feed it back to the error amplification module, that is, updating the first common-mode level signal originally received by the error amplification module to a new second common-mode level signal. The error amplification module 10, the bias voltage generation module 11 and the fully differential Class-AB output module together form a common-mode level signal feedback loop. The above process can be repeated to continuously update the common-mode level signal, thereby obtaining a more stable common-mode level signal.

[0058] The fully differential Class-AB operational amplifier circuit described above only requires one common-mode level signal feedback loop to achieve common-mode level signal stability, reducing power consumption without affecting the stability of other differential-mode loops, while ensuring common-mode response speed and accuracy.

[0059] See also Figure 2 The schematic diagram of a fully differential Class-AB operational amplifier circuit is shown, wherein the error amplification module 10 includes:

[0060] The error amplifier OP has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a preset reference signal VREF, and the second input terminal receives a first common-mode level signal VCM sent by the fully differential Class-AB output module 12. The error amplifier OP is used to compare the first common-mode level signal VCM with the preset reference signal VREF and output a first result.

[0061] The first input terminal can be a non-inverting input terminal, and the second input terminal can be an inverting input terminal. The first input terminal of the error amplifier OP receives a reference signal VREF (such as VDD / 2) provided by an external circuit, and the second input terminal receives a first common-mode level signal VCM fed back by the fully differential Class-AB output module. The error amplifier OP compares the first common-mode level signal VCM with the reference signal VREF, outputs a first result, and realizes the first stage of amplification.

[0062] A first resistor R1 has a first end and a second end, wherein the first end of the first resistor R1 is connected to the output end of the error amplifier OP;

[0063] A first capacitor C1 has a first end and a second end, the first end of the first capacitor C1 is connected to the second end of the first resistor R1, and the second end of the first capacitor C1 is connected to the power supply voltage VDD;

[0064] The first resistor R1 and the first capacitor C1 are used to perform zero-pole compensation on the first result to obtain a comparison result. Figure 2 As shown, since its common-mode level signal feedback loop has a high gain, additional zero-pole compensation technology is required to ensure the stability of the common-mode level signal feedback loop. Node A (i.e., the gate connection point of the first switch tube M5 and the second switch tube M6) will provide a main pole. The larger the first capacitor C1, the lower the main pole. This requires the value of the first capacitor C1 to be a compromise between the area and the phase margin of the common-mode level signal feedback loop. Since the addition of the first capacitor C1 will generate a zero point in the right half plane, a first resistor R1 is also required to move the zero point to the left half plane. The first comparison result is subjected to zero-pole compensation by the first resistor R1 and the first capacitor C1 to obtain a comparison result.

[0065] Furthermore, the bias voltage generating module 11 includes:

[0066] The first switch tube M5 has a gate, a source, and a drain. The source of the first switch tube M5 is connected to the power supply voltage VDD. The gate of the first switch tube M5 is connected to the output end of the error amplifier OP.

[0067] The second switch tube M6 has a gate, a source, and a drain. The source of the second switch tube M6 is connected to the power supply voltage VDD, and the gate of the second switch tube M6 is connected to the output end of the error amplifier OP.

[0068] The third switch tube M7 has a gate, a source, and a drain. The source of the third switch tube M7 is connected to the drain of the first switch tube M5 and the first output terminal of the previous stage circuit respectively. The gate of the third switch tube M7 receives a first bias signal vb1 provided by an external circuit.

[0069] The fourth switching transistor M8 has a gate, a source, and a drain. The gate of the fourth switching transistor M8 is connected to the gate of the third switching transistor M7, and the source of the fourth switching transistor M8 is respectively connected to the drain of the second switching transistor M6 and the second output terminal of the previous stage circuit. The first output terminal and the second output terminal of the previous stage circuit are used to output the differential signals Iin+ and Iin- output by the previous stage circuit.

[0070] a fifth switch tube M9 having a gate, a source, and a drain, wherein the source of the fifth switch tube M9 is connected to the drain of the third switch tube M7, and the gate of the fifth switch tube M9 is connected to a second bias signal VBP provided by an external circuit;

[0071] a sixth switch tube M11 having a gate, a source, and a drain, wherein the drain of the sixth switch tube M11 is connected to the source of the fifth switch tube M9, and the gate of the sixth switch tube M11 is connected to a third bias signal VBN provided by an external circuit;

[0072] A first current source IB1 has a first end and a second end, wherein the first end of the first current source IB1 is connected to the drain of the fifth switch tube M9 and the source of the sixth switch tube M11 respectively; and the second end of the first current source IB1 is grounded;

[0073] a seventh switch tube M10 having a gate, a source, and a drain, wherein the source of the seventh switch tube M10 is connected to the drain of the fourth switch tube M8, and the gate of the seventh switch tube M10 is connected to the second bias signal VBP;

[0074] an eighth switch tube M12 having a gate, a source, and a drain, wherein the drain of the eighth switch tube M12 is connected to the source of the seventh switch tube M10, and the gate of the eighth switch tube M12 is connected to the third bias signal VBN;

[0075] The second current source IB2 has a first end and a second end. The first end of the second current source IB2 is respectively connected to the drain of the seventh switch tube M10 and the source of the eighth switch tube M12; the second end of the second current source IB2 is grounded.

[0076] like Figure 2 As shown, the first switch M5, second switch M6, third switch M7, and fourth switch M8 can be implemented using MOS transistors. These four switches form a cascode current source load, which can be used to enhance amplifier performance and stability. The gate bias voltage vb1 of the third switch M7 and the fourth switch M8 can be provided by an external circuit. The previous stage circuit (not shown) can output differential signals Iin+ and Iin- through the first and second output terminals of the previous stage circuit. Iin+ is input to the cascode current source load through the common node of the first switch M5 and the third switch M7, and Iin- is input to the cascode current source load through the common node of the second switch M6 and the fourth switch M8. The comparison result output by the error amplification module is input to the gates of the first switch M5 and the second switch M6, turning on the first and second switches M5 and M6.

[0077] The floating current source composed of the fifth switch tube M9, the sixth switch tube M11, the seventh switch tube M10 and the eighth switch tube M12 biases the output stage of the fully differential Class-AB operational amplifier; the second bias signal VBP and the third bias signal VBN are biases for the floating current sources NMOS and PMOS, and are both generated externally. The first current source IB1 and the second current source IB2 are tail current sources. When the first switch tube M5 and the second switch tube M6 are turned on, the bias voltage generation module can output a bias voltage signal, such as Figure 2 As shown, the required bias voltage signal can be derived through the drain of the third switch tube M7, the drain of the fourth switch tube M8, the first end of the first current source and the first end of the second current source.

[0078] like Figure 2 As shown in Figure 1, the fully differential Class-AB output module includes:

[0079] The ninth switch tube M1 has a gate, a source, and a drain. The source of the ninth switch tube M1 is connected to the power supply voltage VDD; the gate of the ninth switch tube M1 is connected to the drain of the third switch tube M7;

[0080] a tenth switching transistor M2 having a gate, a source, and a drain, wherein the drain of the tenth switching transistor M2 is respectively connected to the drain of the ninth switching transistor M1 and the first output terminal VON of the fully differential Class-AB output module, the gate of the tenth switching transistor M2 is connected to the first terminal of the first current source IB1, and the source of the tenth switching transistor M2 is grounded;

[0081] a first RC unit having a first end and a second end, wherein the first end of the first RC unit is connected to the drain of the ninth switch tube M1 , and the second end of the first RC unit is connected to the second input end VOP of the error amplifier OP;

[0082] The eleventh switch tube M3 has a gate, a source, and a drain. The source of the eleventh switch tube M3 is connected to the power supply voltage VDD; the gate of the eleventh switch tube M3 is connected to the drain of the fourth switch tube M8;

[0083] a twelfth switch M4 having a gate, a source, and a drain, wherein the drain of the twelfth switch M4 is respectively connected to the drain of the eleventh switch M3 and the second output terminal of the fully differential Class-AB output module, the gate of the twelfth switch M4 is connected to the first terminal of the second current source IB2, and the source of the twelfth switch M4 is grounded;

[0084] The second RC unit has a first end and a second end. The first end of the second RC unit is connected to the drain of the eleventh switch tube M3 , and the second end of the second RC unit is connected to the second input end of the error amplifier OP.

[0085] like Figure 2 As shown, the ninth switch transistor M1, the tenth switch transistor M2, the eleventh switch transistor M3, and the twelfth switch transistor M4 can be implemented using MOS transistors. These four switch transistors constitute the output stage of the Class-AB operational amplifier. One end of the floating current source formed by the fifth switch transistor M9 and the sixth switch transistor M11 is connected to the gate of the ninth switch transistor M1 in the fully differential Class-AB output module, and the other end is connected to the gate of the tenth switch transistor M2. One end of the floating current source formed by the seventh switch transistor M10 and the eighth switch transistor M12 is connected to the gate of the eleventh switch transistor M3, and the other end is connected to the gate of the twelfth switch transistor M4. After the third-stage amplification, the signal output from the first output terminal VON and the signal output from the second output terminal VOP of the fully differential Class-AB output module pass through the first RC unit and the second RC unit, and then the common-mode level is detected and fed back to the inverting input terminal of the error amplifier OP, forming a closed common-mode level signal feedback loop.

[0086] like Figure 2 As shown, the first resistance-capacitance unit includes:

[0087] a second resistor R2 having a first end and a second end, wherein the first end of the second resistor R2 is connected to the drain of the ninth switch tube M1 , and the second end of the second resistor R2 is connected to the second input end of the error amplifier OP;

[0088] The second capacitor C2 has a first end and a second end. The first end of the second capacitor C2 is connected to the drain of the ninth switch tube M1, and the second end of the second capacitor C2 is connected to the second input end of the error amplifier OP. The second resistor-capacitor unit includes:

[0089] a third resistor R3 having a first end and a second end, wherein the first end of the third resistor R3 is connected to the drain of the eleventh switch tube M3 , and the second end of the third resistor R3 is connected to the second input end of the error amplifier OP;

[0090] The third capacitor C3 has a first end and a second end. The first end of the third capacitor C3 is connected to the drain of the eleventh switch tube M3 , and the second end of the third capacitor C3 is connected to the second input end of the error amplifier OP.

[0091] The second resistor R2 is connected to the first output terminal VON of the fully differential Class-AB output module, and the third resistor R3 is connected to the second output terminal VOP of the fully differential Class-AB output module. It can be used to detect the common-mode level signal and send it to the inverting input terminal of the error amplifier OP. The second capacitor C2 and the third capacitor C3 are used for output stage pole compensation.

[0092] Combine Figure 2 As can be seen, this common-mode level signal feedback loop has three stages, resulting in high gain and GBW, but its stability is relatively poor, requiring an additional zero-pole compensation solution. Here, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the first resistor R1 are used to compensate for the zeros and poles of the first and third stages of the common-mode loop. This achieves good common-mode stability and response speed without introducing new zeros and poles or sacrificing differential-mode performance.

[0093] In practical applications, in order to further improve the accuracy of the detected common-mode level signal, the second resistor R2 and the third resistor R3 are usually designed to have the same resistance value.

[0094] like Figure 2 As shown, the fully differential Class-AB output module 12 includes:

[0095] A fourth resistor R4 has a first end and a second end, and the first end of the fourth resistor R4 is connected to the gate of the ninth switch tube M1;

[0096] a fourth capacitor C4 having a first end and a second end, wherein the first end of the fourth capacitor C4 is connected to the second end of the fourth resistor R4, and the second end of the fourth capacitor C4 is connected to the first output end VON of the fully differential Class-AB output module;

[0097] A fifth resistor R5 has a first end and a second end, and the first end of the fifth resistor R5 is connected to the gate of the eleventh switch tube M3;

[0098] The fifth capacitor C5 has a first end and a second end. The first end of the fifth capacitor C5 is connected to the second end of the fifth resistor R5 , and the second end of the fifth capacitor C5 is connected to the second output end VOP of the fully differential Class-AB output module.

[0099] The fourth capacitor C4 and the fifth capacitor C5 are Maitreya compensation capacitors, and the fourth resistor R4 and the fifth resistor R5 are zero adjustment resistors; the fourth capacitor C4, the fifth capacitor C5 and the fourth resistor R4, the fifth resistor R5 can improve the stability of the common-mode level signal feedback loop, but they are more sensitive to the differential mode loop, which will affect the performance of the circuit. The first and third stage zeros and poles of the common mode loop are compensated by the aforementioned first capacitor C1, the second capacitor C2, the third capacitor C3 and the first resistor R1, without introducing new zeros and poles and without sacrificing differential mode performance, while achieving better common-mode stability and response speed.

[0100] like Figure 3 FIG. 1 is a circuit diagram of an error amplifier, wherein the error amplifier OP includes:

[0101] a thirteenth switch tube M13 having a gate, a source, and a drain, wherein the source of the thirteenth switch tube M13 is connected to the power supply voltage VDD, and the gate of the thirteenth switch tube M13 is connected to the drain of the thirteenth switch tube M13;

[0102] A fourteenth switch tube M14 has a gate, a source, and a drain. The source of the fourteenth switch tube M14 is connected to the power supply voltage VDD, and the gate of the fourteenth switch tube M14 is connected to the gate of the thirteenth switch tube M13.

[0103] A fifteenth switch tube M15 has a gate, a source, and a drain, wherein the drain of the fifteenth switch tube M15 is connected to the drain of the thirteenth switch tube M13; and the gate of the fifteenth switch tube M15 is connected to the first input terminal of the error amplifier OP;

[0104] The sixteenth switch tube M16 has a gate, a source, and a drain, wherein the drain of the sixteenth switch tube M16 is connected to the drain of the fourteenth switch tube M14; the gate of the sixteenth switch tube M16 is connected to the second input terminal of the error amplifier OP;

[0105] The third current source IB3 has a first end and a second end. The first end of the third current source IB3 is respectively connected to the source of the fifteenth switch tube M15 and the source of the sixteenth switch tube M16; the second end of the third current source IB3 is grounded.

[0106] The error amplifier OP of the common-mode level signal feedback loop is an operational amplifier structure with differential input and single-ended output. It can be implemented with a simple five-transistor OTA (Operational Transconductance Amplifier, transconductance operational amplifier), as shown in the attached figure. Figure 3 As shown, the fifteenth switch tube M15 and the sixteenth switch tube M16 serve as input pairs, the thirteenth switch tube M13 and the fourteenth switch tube M14 serve as current source loads, and the third current source IB3 serves as a tail current source; Vin+ corresponds to the non-inverting input terminal of the error amplifier OP, which is used to connect Figure 2 The reference signal VREF in the circuit, Vin- corresponds to the inverting input terminal of the error amplifier OP, which is used to receive the common-mode level signal sent by the fully differential Class-AB output module; Vout corresponds to the output terminal of the error amplifier OP.

[0107] The following combination Figure 2 The operating principle of the fully differential Class-AB operational amplifier circuit is explained below: The resistor divider formed by the second and third resistors R2 and R3 performs common-mode detection at the differential output, resulting in VCM = (VOP * R2 + VON * R3) / (R2 + R3). In the design, R2 = R3 and is relatively large relative to the output impedance, resulting in VCM = (VOP + VON) / 2. VCM and the reference signal VREF then serve as the differential inputs of the error amplifier OP. The output is connected to a cascode structure consisting of the first and third switches M5 and M7, and the second and fourth switches M6 and M8. The gain is gm5 * gm7ro7ro5, where gm5 is the low-frequency transconductance gm of the first switch M5; gm7 is the low-frequency transconductance gm of the third switch M7; ro7 is the small-signal resistance of the third switch M7; and ro5 is the small-signal resistance of the first switch M5.

[0108] Then, the ninth switch tube M1 and the eleventh switch tube M3 are output, and the common-mode level signal is detected at the output end and then fed back to the inverting input end of the error amplifier OP. Therefore, the loop gain of the common-mode level signal feedback loop is:

[0109] A V =A OP *g m5，6 *(g m7，8 r o7，8 *r o5，6 )*(g m1 *r o1 );

[0110] Wherein, Aop is the open-loop gain of the error amplifier OP; gm5,6 is the low-frequency transconductance gm of the first switch tube M5 or the second switch tube M6; gm7,8 is the low-frequency transconductance gm of the third switch tube M7 or the fourth switch tube M8; ro7,8 is the small-signal resistance of the third switch tube M7 and the fourth switch tube M8, ro5,6 is the small-signal resistance of the first switch tube M5 and the second switch tube M6; gm1 is the low-frequency transconductance gm of the ninth switch tube M1; ro1 is the small-signal resistance of the ninth switch tube M1.

[0111] In this embodiment, due to the differential structure, the first switch tube M5 is the same as the second switch tube M6 , the third switch tube M7 is the same as the fourth switch tube M8 , and the ninth switch tube M1 is the same as the eleventh switch tube M3 .

[0112] Its larger gain results in a higher GBW and makes the output common-mode level signal VCM closer to VREF more accurately, so that the circuit has an optimal swing range.

[0113] Since the common-mode level signal feedback loop has a high gain, additional zero-pole compensation technology is required to ensure the stability of the common-mode level signal feedback loop. Figure 2 , node A will provide a main pole. Without the first resistor R1 and the first capacitor C1, the pole is:

[0114]

[0115] Among them, R A represents the resistance of node A to ground, C A is the capacitance to ground of node A, Rout,op represents the resistance to ground of the output terminal of the error amplifier OP viewed from node A; Cout,op represents the capacitance to ground of the output terminal of the error amplifier OP viewed from node A; Cgg5 is the sum of Cgs, Cgd and Cgb (capacitance between the gate and substrate) of the first switch tube M5; Cgg6 is the sum of Cgs, Cgd and Cgb (capacitance between the gate and substrate) of the second switch tube M6.

[0116] After adding the first capacitor C1, the pole becomes:

[0117]

[0118] It can be seen that the frequency of the main pole decreases and approaches the origin. The larger the first capacitor C1, the lower the main pole. This requires a compromise between the area and the phase margin of the common-mode level signal feedback loop when selecting the value of the first capacitor C1. Since the addition of the first capacitor C1 will produce a zero point in the right half plane, a first resistor R1 is also required to move the zero point to the left half plane. In addition, if Figure 2As shown, there is a second capacitor C2 at the output node D for compensation, and the appropriate values ​​of the first resistor R1 and the second capacitor C2 are adjusted so that the sub-pole generated at the node D and the zero point in the circuit are offset, thereby improving the stability of the loop; similarly, there is a third capacitor C3 at the output node E for compensation, and the appropriate values ​​of the first resistor R1 and the third capacitor C3 are adjusted so that the sub-pole generated at the node E and the zero point in the circuit are offset, thereby improving the stability of the loop.

[0119] This common-mode signal feedback scheme and zero-pole compensation method for a fully differential operational amplifier with Class-AB output and floating current source bias has almost no effect on the differential-mode performance of the circuit, while significantly improving the stability of the common-mode signal loop.

[0120] The above-mentioned fully differential Class-AB operational amplifier circuit based on floating current source bias proposes a novel common-mode level signal feedback loop scheme and zero-pole compensation method. A single common-mode level signal feedback loop can achieve common-mode level signal stability, extremely low power consumption, and excellent common-mode response speed and accuracy. This scheme has no effect on the differential-mode loop of the op amp, allowing the fully differential op amp to have low power consumption and high performance while also having good common-mode response. The common-mode feedback scheme of this two-stage Class-AB output fully differential operational amplifier based on floating current source bias is simple and easy to implement. While maintaining good differential-mode performance, it also has good common-mode stability, good common-mode response speed and accuracy, thereby ensuring the normal static operating point of the circuit and excellent circuit performance.

[0121] An embodiment of the present invention provides a fully differential Class-AB operational amplifier system, which includes: any one of the above-mentioned fully differential Class-AB operational amplifier circuits.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully differential Class-AB operational amplifier circuit, characterized in that: The circuit comprises: an error amplification module, configured to receive a first common-mode level signal sent by the fully differential Class-AB output module, compare the first common-mode level signal with a preset reference signal, and output a comparison result; A bias voltage generating module, used for receiving the comparison result, amplifying the comparison result, and outputting a bias voltage signal; a fully differential Class-AB output module, configured to receive the bias voltage signal, determine a differential output voltage of the fully differential Class-AB operational amplifier according to the bias voltage signal, determine a second common-mode level signal based on the differential output voltage, and send the second common-mode level signal to the error amplification module to replace the first common-mode level signal; the first common-mode level signal is the same as or different from the second common-mode level signal; The error amplification module comprises: An error amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a preset reference signal, the second input terminal receives a first common-mode level signal sent by the fully differential Class-AB output module, and the error amplifier is used to compare the first common-mode level signal with the preset reference signal and output a first result; A first resistor having a first end and a second end, wherein the first end of the first resistor is connected to the output end of the error amplifier; A first capacitor having a first end and a second end, wherein the first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is connected to a power supply voltage; wherein the larger the first capacitor is, the lower the main pole is; and the main pole is a gate connection point of a first switch tube and a second switch tube in the bias voltage generating module; The first resistor and the first capacitor are used to perform zero-pole compensation on the first result to obtain a comparison result.

2. The circuit according to claim 1, characterized in that The bias voltage generating module comprises: A first switch tube has a gate, a source and a drain, wherein the source of the first switch tube is connected to a power supply voltage; and the gate of the first switch tube is connected to an output end of the error amplifier; A second switch tube has a gate, a source and a drain, the source of the second switch tube is connected to the power supply voltage, and the gate of the second switch tube is connected to the output end of the error amplifier; a third switch tube, having a gate, a source and a drain, wherein the source of the third switch tube is respectively connected to the drain of the first switch tube and the first output end of the previous stage circuit; and the gate of the third switch tube receives a first bias signal provided by an external circuit; a fourth switch tube, having a gate, a source and a drain, wherein the gate of the fourth switch tube is connected to the gate of the third switch tube, and the source of the fourth switch tube is respectively connected to the drain of the second switch tube and the second output end of the previous stage circuit; the first output end and the second output end of the previous stage circuit are used to output the differential signal output by the previous stage circuit; a fifth switch tube, comprising a gate, a source and a drain, wherein the source of the fifth switch tube is connected to the drain of the third switch tube, and the gate of the fifth switch tube is connected to a second bias signal provided by an external circuit; a sixth switch tube, comprising a gate, a source and a drain, wherein the drain of the sixth switch tube is connected to the source of the fifth switch tube, and the gate of the sixth switch tube is connected to a third bias signal provided by an external circuit; A first current source has a first end and a second end, wherein the first end of the first current source is respectively connected to the drain of the fifth switch tube and the source of the sixth switch tube; and the second end of the first current source is grounded; a seventh switch tube, comprising a gate, a source and a drain, wherein the source of the seventh switch tube is connected to the drain of the fourth switch tube, and the gate of the seventh switch tube is connected to the second bias signal; an eighth switch tube, comprising a gate, a source and a drain, the drain of the eighth switch tube being connected to the source of the seventh switch tube, and the gate of the eighth switch tube being connected to the third bias signal; The second current source has a first end and a second end, wherein the first end of the second current source is respectively connected to the drain of the seventh switch tube and the source of the eighth switch tube; and the second end of the second current source is grounded.

3. The circuit according to claim 2, characterized in that The fully differential Class-AB output module includes: A ninth switch tube, comprising a gate, a source and a drain, wherein the source of the ninth switch tube is connected to a power supply voltage; and the gate of the ninth switch tube is connected to the drain of the third switch tube; a tenth switch tube, having a gate, a source and a drain, the drain of the tenth switch tube being respectively connected to the drain of the ninth switch tube and the first output end of the fully differential Class-AB output module, the gate of the tenth switch tube being connected to the first end of the first current source, and the source of the tenth switch tube being grounded; A first resistor-capacitor unit has a first end and a second end, wherein the first end of the first resistor-capacitor unit is connected to the drain of the ninth switch tube, and the second end of the first resistor-capacitor unit is connected to the second input end of the error amplifier; an eleventh switch tube, comprising a gate, a source and a drain, wherein the source of the eleventh switch tube is connected to the power supply voltage; and the gate of the eleventh switch tube is connected to the drain of the fourth switch tube; a twelfth switch tube, having a gate, a source and a drain, the drain of the twelfth switch tube being respectively connected to the drain of the eleventh switch tube and the second output end of the fully differential Class-AB output module, the gate of the twelfth switch tube being connected to the first end of the second current source, and the source of the twelfth switch tube being grounded; The second RC unit has a first end and a second end. The first end of the second RC unit is connected to the drain of the eleventh switch tube, and the second end of the second RC unit is connected to the second input end of the error amplifier.

4. The circuit according to claim 3, characterized in that The first resistance-capacitance unit comprises: A second resistor having a first end and a second end, the first end of the second resistor being connected to the drain of the ninth switch tube, and the second end of the second resistor being connected to the second input end of the error amplifier; The second capacitor has a first end and a second end, the first end of the second capacitor is connected to the drain of the ninth switch tube, and the second end of the second capacitor is connected to the second input end of the error amplifier.

5. The circuit according to claim 4, characterized in that The second resistance-capacitance unit comprises: A third resistor has a first end and a second end, the first end of the third resistor is connected to the drain of the eleventh switch tube, and the second end of the third resistor is connected to the second input end of the error amplifier; The third capacitor has a first end and a second end. The first end of the third capacitor is connected to the drain of the eleventh switch tube, and the second end of the third capacitor is connected to the second input end of the error amplifier.

6. The circuit according to claim 5, characterized in that The resistance value of the second resistor is the same as the resistance value of the third resistor.

7. The circuit according to claim 3, characterized in that The fully differential Class-AB output module includes: a fourth resistor, having a first end and a second end, wherein the first end of the fourth resistor is connected to the gate of the ninth switch tube; a fourth capacitor having a first end and a second end, wherein the first end of the fourth capacitor is connected to the second end of the fourth resistor, and the second end of the fourth capacitor is connected to the first output end of the fully differential Class-AB output module; a fifth resistor, having a first end and a second end, wherein the first end of the fifth resistor is connected to the gate of the eleventh switch tube; The fifth capacitor has a first end and a second end, the first end of the fifth capacitor is connected to the second end of the fifth resistor, and the second end of the fifth capacitor is connected to the second output end of the fully differential Class-AB output module.

8. The circuit according to claim 1, characterized in that The error amplifier comprises: A thirteenth switch tube, comprising a gate, a source and a drain, wherein the source of the thirteenth switch tube is connected to a power supply voltage, and the gate of the thirteenth switch tube is connected to the drain of the thirteenth switch tube; A fourteenth switch tube, comprising a gate, a source and a drain, wherein the source of the fourteenth switch tube is connected to a power supply voltage, and the gate of the fourteenth switch tube is connected to the gate of the thirteenth switch tube; A fifteenth switch tube has a gate, a source and a drain, the drain of the fifteenth switch tube is connected to the drain of the thirteenth switch tube; the gate of the fifteenth switch tube is connected to the first input terminal of the error amplifier; A sixteenth switch tube has a gate, a source and a drain, the drain of the sixteenth switch tube is connected to the drain of the fourteenth switch tube; the gate of the sixteenth switch tube is connected to the second input terminal of the error amplifier; The third current source has a first end and a second end, wherein the first end of the third current source is respectively connected to the source of the fifteenth switch tube and the source of the sixteenth switch tube; and the second end of the third current source is grounded.

9. A fully differential Class-AB operational amplifier system, characterized in that: The system comprises: the fully differential Class-AB operational amplifier circuit according to any one of claims 1 to 8.

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