Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: providing a substrate; forming a dielectric structure on the surface of the substrate, the dielectric structure comprising a dielectric layer; forming an opening in the dielectric structure; forming a metal material layer in the opening and on the surface of the dielectric structure; using a first mechanochemical grinding process to flatten the metal material layer until the surface of the dielectric structure is exposed, forming an initial conductive structure with the metal material layer, the surface of the initial conductive structure having a butterfly defect, the butterfly defect causing the center of the surface of the initial conductive structure to be recessed relative to the edge; using an etching process to etch the surface of the dielectric structure so that the edge of the surface of the initial conductive structure protrudes from the surface of the dielectric structure; after the etching process, using a second mechanochemical grinding process to flatten the initial conductive structure and the dielectric structure, forming a conductive structure with the initial conductive structure, which is beneficial to improving the surface flatness of the formed conductive structure, reducing the abnormal probability of circuit failure caused by the butterfly defect, and improving the product yield.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the large-scale integrated circuit manufacturing process, chemical mechanical polishing (CMP) is a planarization process that combines chemical and mechanical action, and is the main means of global planarization of the chip surface. The butterfly defect is a common defect in the chemical mechanical polishing process, which is mainly caused by the different polishing rates of the metal line and the dielectric layer during the polishing process.

[0003] With the development of semiconductor manufacturing technology, the integration of wafers continues to increase, the feature size is getting smaller and smaller, and the requirements for defect size are becoming more and more stringent.

[0004] However, in the semiconductor structure formed by the existing chemical mechanical polishing process, the butterfly defect has a large size and cannot meet the production requirements. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric structure on the surface of the substrate, the dielectric structure comprising a dielectric layer; forming an opening in the dielectric structure; forming a metal material layer in the opening and on the surface of the dielectric structure; using a first mechanochemical polishing process to flatten the metal material layer until the surface of the dielectric structure is exposed, forming an initial conductive structure with the metal material layer, the surface of the initial conductive structure having a butterfly defect, the butterfly defect causing the center of the surface of the initial conductive structure to be recessed relative to the edge; using an etching process to etch the surface of the dielectric structure so that the edge of the surface of the initial conductive structure protrudes from the surface of the dielectric structure; after the etching process, using a second mechanochemical polishing process to flatten the initial conductive structure and the dielectric structure, forming a conductive structure with the initial conductive structure.

[0007] Optionally, the etching process includes one of a dry etching process and a wet etching process or a combination of both.

[0008] Optionally, the etching process has an etching selectivity ratio of 15 to 30 for the dielectric structure and the initial conductive structure.

[0009] Optionally, before forming the metal material layer, the method further includes: forming a barrier material layer on the opening and the surface of the dielectric structure; and after the second mechanochemical polishing process, further forming a barrier layer with the barrier material layer.

[0010] Optionally, the ratio of the thickness of the barrier material layer to the thickness of the metal material layer is in a range of 10 to 50.

[0011] Optionally, the etching process has an etching selectivity ratio of 15 to 30 for the dielectric structure and the barrier material layer.

[0012] Optionally, the butterfly defect has a first depth; the etching process reduces the dielectric structure by a first thickness; and a ratio of the first depth to the first thickness ranges from 0.5 to 1.

[0013] Optionally, the dielectric structure further includes a protective layer, the protective layer is located on the surface of the dielectric layer, and the material of the protective layer is different from that of the dielectric layer; the opening is located in the dielectric layer and the protective layer.

[0014] Optionally, the method for forming the conductive structure further includes: using a second mechanical chemical polishing process to planarize the initial conductive structure and the protective layer until the surface of the dielectric layer is exposed.

[0015] Optionally, the material of the protective layer includes a dielectric material including one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride.

[0016] Optionally, the material of the dielectric layer includes a dielectric material, and the dielectric constant of the dielectric material is less than 3.9.

[0017] Optionally, the second mechanochemical polishing process has a first polishing rate for the initial conductive structure and a second polishing rate for the dielectric structure, and a ratio of the first polishing rate to the second polishing rate ranges from 2 to 8.

[0018] Optionally, a device structure is provided in the substrate, and the opening exposes the device structure.

[0019] Optionally, the dielectric structure further includes an etch stop layer, the etch stop layer is located between the dielectric layer and the substrate, and the material of the etch stop layer is different from that of the dielectric layer; the opening is also located in the etch stop layer.

[0020] Optionally, the opening includes a groove and a through hole located at the bottom of the groove, the groove is located in the dielectric layer, the through hole is located in the dielectric layer and the etch stop layer, the groove has a first projection on the substrate surface, the through hole has a second projection on the substrate surface, and the second projection is located within the range of the first projection.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] In the method for forming a semiconductor structure provided by the technical solution of the present invention, an etching process is used to etch the surface of the dielectric structure so that the edge of the initial conductive structure surface protrudes from the surface of the dielectric structure. Since the protruding portion will be preferentially ground and removed in the second mechanical chemical grinding process, the edge of the initial conductive structure surface has a larger grinding rate relative to the center of the initial conductive structure surface, which is beneficial to improving the surface flatness of the formed conductive structure, reducing the abnormal probability of circuit failure due to butterfly defects, and improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1 to 4 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0024] Figures 5 to 10 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0026] As described in the background art, the existing chemical mechanical polishing process needs to be further improved. Now, a semiconductor structure formation process is described and analyzed.

[0027] Figures 1 to 4 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0028] Please refer to Figure 1 , providing a substrate, the substrate comprising a base (not shown in the figure), a dielectric structure located on the base, the dielectric structure comprising an etch stop layer 101, a dielectric layer 102 located on the etch stop layer 101, and an oxide layer 103 located on the dielectric layer 102.

[0029] Please refer to Figure 2 , etching the dielectric structure to form a trench 104 and a through hole 105 located at the bottom of the trench 104 in the dielectric structure.

[0030] Please refer to Figure 3A barrier material layer 106 and a metal material layer 107 located on the surface of the barrier material layer 106 are formed on the surface of the oxide layer 103 , in the groove 104 and in the through hole 105 .

[0031] Please refer to Figure 4 The barrier material layer 106 and the metal material layer 107 are planarized by a mechanical chemical grinding process until the surface of the dielectric layer 102 is exposed, and a conductive structure 107 is formed in the groove 104 and the through hole 105 .

[0032] In the above-mentioned method for forming a semiconductor structure, the material of the metal material layer 107 is copper. During the mechanochemical polishing process, in order to completely polish the copper on the surface of the oxide layer 103, there will be a copper over-polishing process. In this process, due to the excessively fast copper polishing rate and the slow polishing rates of the barrier material layer 106 and the oxide layer 103, local over-polishing is likely to occur, resulting in a dish-shaped defect A (such as Figure 4 As shown in the figure, it affects the subsequent interconnection process, device performance and yield, and may even cause device disconnection, resulting in circuit failure and catastrophic consequences.

[0033] In order to solve the above problems, in a method for forming a semiconductor structure provided by the present invention, an etching process is used to etch the surface of the dielectric structure so that the edge of the initial conductive structure surface protrudes from the surface of the dielectric structure. Since the protruding portion will be preferentially ground and removed in the second mechanochemical grinding process, the edge of the initial conductive structure surface has a larger grinding rate relative to the center of the initial conductive structure surface, which is beneficial to improving the surface flatness of the formed conductive structure, reducing the abnormal probability of circuit failure due to butterfly defects, and improving product yield.

[0034] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 5 to 10 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] Please refer to Figure 5 , providing a substrate (not shown in the figure); forming a dielectric structure 201 on the surface of the substrate, and the dielectric structure 201 includes a dielectric layer 201a.

[0037] In this embodiment, the dielectric structure 201 further includes an etch stop layer 201b, which is located between the dielectric layer 201a and the substrate, and the material of the etch stop layer 201b is different from that of the dielectric layer 201a. In another embodiment, the dielectric structure may not include the etch stop layer.

[0038] The material of the etch stop layer 201b includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the etch stop layer 201b is silicon nitride.

[0039] In this embodiment, the dielectric structure 201 further includes a protective layer 201c, which is located on the surface of the dielectric layer 201. The material of the protective layer 201c is different from that of the dielectric layer 201a. In another embodiment, the dielectric structure may not include the protective layer.

[0040] The protection layer 201c is used to protect the dielectric layer 201a and reduce etching damage in subsequent etching processes. At the same time, it is also used to block the diffusion of impurities into the dielectric layer 201a and improve the performance of the dielectric layer 201a.

[0041] The material of the protective layer 201c includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the protective layer 201c is silicon oxide.

[0042] The material of the dielectric layer 201a includes a dielectric material, and the dielectric constant of the dielectric material is less than 3.9.

[0043] In this embodiment, the dielectric layer 201a is made of silicon carbon oxyhydride (SiCOH). SiCOH material has a relatively low dielectric constant, and its dielectric constant value is about 3.0.

[0044] The substrate has a device structure (not shown in the figure), and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc. In this embodiment, the device structure is a conductive structure.

[0045] In this embodiment, the material of the substrate includes silicon.

[0046] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0047] Please refer to Figure 6 , an opening 202 is formed in the dielectric structure 201 .

[0048] The opening 202 exposes the substrate surface. Specifically, the opening 202 exposes the device structure.

[0049] The process of forming the opening 202 includes a dry etching process.

[0050] In this embodiment, the opening 202 is located in the dielectric layer 201 a and the protective layer 201 c , and is also located in the etch stop layer 201 b .

[0051] In this embodiment, the opening 202 includes a groove (not shown in the figure) and a through hole (not shown in the figure) located at the bottom of the groove, the groove is located in the dielectric layer 201a, the through hole is located in the dielectric layer 201a and the etch stop layer 201b, the groove has a first projection on the substrate surface, the through hole has a second projection on the substrate surface, and the second projection is located within the range of the first projection.

[0052] Specifically, the groove is also located in the protection layer 201c.

[0053] Please refer to Figure 7 A metal material layer 203 is formed in the opening 202 and on the surface of the dielectric structure 201 .

[0054] The material of the metal material layer 203 includes one or more of copper, aluminum, silver or platinum. In this embodiment, the material of the metal material layer 203 is copper.

[0055] In this embodiment, before forming the metal material layer 203 , a barrier material layer 204 is formed in the opening 202 and on the surface of the dielectric structure 201 .

[0056] The material of the barrier material layer 204 includes titanium nitride or titanium nitride. In this embodiment, the material of the barrier material layer 204 is titanium nitride. The barrier material layer 204 plays the role of adhesion and barrier.

[0057] In this embodiment, the ratio of the thickness of the barrier material layer 204 to the thickness of the metal material layer 203 is in a range of 10 to 50. The thickness refers to the thickness of the material film deposited on the surface of the dielectric structure 201 .

[0058] Please refer to Figure 8 , the metal material layer 203 (such as Figure 7 As shown), until the surface of the dielectric structure 201 is exposed, an initial conductive structure 205 is formed with the metal material layer 203, and the surface of the initial conductive structure 205 has a butterfly-shaped defect D, and the butterfly-shaped defect D causes the center of the surface of the initial conductive structure 205 to be recessed relative to the edge.

[0059] In this embodiment, the butterfly defect has a first depth h1.

[0060] In this embodiment, the first mechanochemical polishing process is also used to remove the barrier material layer 204 on the surface of the dielectric structure 201 .

[0061] Please refer to Fig. 9 , an etching process is used to etch the surface of the dielectric structure 201, so that the surface edge of the initial conductive structure 205 protrudes from the surface of the dielectric structure 201 (as shown by the dotted line).

[0062] The etching process reduces the dielectric structure 201 by a first thickness h2. Specifically, the etching process reduces the protective layer 201c by a first thickness h2.

[0063] The first thickness h2 may be adjusted according to the first depth h1 to obtain a relatively flat conductive structure.

[0064] In this embodiment, the ratio of the first depth h1 to the first thickness h2 ranges from 0.5 to 1.

[0065] The etching selectivity of the etching process to the dielectric structure 201 and the initial conductive structure 205 ranges from 15 to 30. Specifically, the etching selectivity of the etching process to the protective layer 201 c and the initial conductive structure 205 ranges from 15 to 30.

[0066] The etching process includes one of a dry etching process and a wet etching process or a combination of the two. In this embodiment, the etching process is a dry etching process.

[0067] In this embodiment, the process parameters of the dry etching process include: the etching gas includes one or more combinations of CF4, CHF3, C4F8, the etching power range is 400W to 800W, the gas pressure range is 50mTorr to 100mTorr, and the gas flow range is 10sccm to 200sccm.

[0068] After etching the surface of the dielectric structure 201 , a portion of the barrier material layer 204 is made to protrude from the surface of the dielectric structure 201 .

[0069] In this embodiment, the etching selectivity ratio of the etching process to the dielectric structure 201 and the barrier material layer 204 ranges from 15 to 30.

[0070] Please refer to Fig.10After the etching process, a second mechanical chemical polishing process is used to planarize the initial conductive structure 205 and the dielectric structure 201, so that the initial conductive structure 205 (such as Fig. 9 As shown) a conductive structure 206 is formed.

[0071] Here, the edge of the surface of the initial conductive structure 205 protrudes from the surface of the dielectric structure 201. Since the protruding portion will be preferentially ground away in the second mechanical chemical grinding process, the edge of the surface of the initial conductive structure 205 has a greater grinding rate relative to the center of the surface of the initial conductive structure 205, which is beneficial to improving the surface flatness of the formed conductive structure 206, reducing the abnormal probability of circuit failure due to butterfly defects, and improving product yield.

[0072] Furthermore, the portion of the barrier material layer 204 protruding from the surface of the dielectric structure 201 is also preferentially polished away in the second mechanochemical polishing process.

[0073] In this embodiment, specifically, the initial conductive structure 205 and the protective layer 201c are planarized by a second mechanochemical polishing process until the surface of the dielectric layer 201a is exposed.

[0074] In this embodiment, the second mechanochemical polishing process has a first polishing rate for the initial conductive structure 205 and a second polishing rate for the dielectric structure 201 , and a ratio of the first polishing rate to the second polishing rate ranges from 2 to 8.

[0075] Specifically, the second mechanochemical polishing process has a first polishing rate for the initial conductive structure 205 and a second polishing rate for the protective layer 201 c , and a ratio of the first polishing rate to the second polishing rate ranges from 2 to 8.

[0076] After the second mechanical chemical polishing process, the barrier material layer 204 (such as Fig. 9 As shown) a barrier layer 207 is formed.

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dielectric structure on the surface of the substrate, wherein the dielectric structure comprises a dielectric layer and a protective layer, and the protective layer is located on the surface of the dielectric layer; forming an opening in the dielectric structure; forming a metal material layer in the opening and on the surface of the dielectric structure; The metal material layer is flattened by a first mechanical chemical grinding process until the surface of the dielectric structure is exposed, and an initial conductive structure is formed by the metal material layer, wherein the surface of the initial conductive structure has a butterfly-shaped defect, wherein the butterfly-shaped defect causes the center of the surface of the initial conductive structure to be concave relative to the edge, and the butterfly-shaped defect has a first depth; Etching a protective layer partially thick on the surface of the dielectric structure by an etching process, so that the edge of the initial conductive structure surface protrudes from the surface of the dielectric structure, the dielectric structure is thinned by a first thickness by the etching process, and the first thickness is determined according to the first depth; After the etching process, a second mechanical chemical polishing process is used to planarize the initial conductive structure and the dielectric structure to form a conductive structure and expose the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The etching process includes one of a dry etching process and a wet etching process or a combination of both.

3. The method for forming a semiconductor structure according to claim 2, wherein: The etching process has an etching selectivity ratio of 15 to 30 for the dielectric structure and the initial conductive structure.

4. The method for forming a semiconductor structure according to claim 2, wherein: Before forming the metal material layer, the method further includes: forming a barrier material layer on the opening and the surface of the dielectric structure; and after the second mechanochemical polishing process, forming a barrier layer with the barrier material layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The ratio of the thickness of the barrier material layer to the thickness of the metal material layer is in a range of 10 to 50.

6. The method for forming a semiconductor structure according to claim 4, wherein: The etching process has an etching selectivity ratio of 15 to 30 for the dielectric structure and the barrier material layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: A ratio of the first depth to the first thickness ranges from 0.5 to 1.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the protection layer is different from that of the dielectric layer; and the opening is located in the dielectric layer and the protection layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the conductive structure further includes: using a second mechanical chemical grinding process to planarize the initial conductive structure and the protective layer until the surface of the dielectric layer is exposed.

10. The method for forming a semiconductor structure according to claim 8, wherein: The material of the protective layer includes a dielectric material including one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide nitride.

11. The method for forming a semiconductor structure according to claim 8, wherein: The material of the dielectric layer includes a dielectric material, and the dielectric constant of the dielectric material is less than 3.

9.

12. The method for forming a semiconductor structure according to claim 1, wherein: The second mechanochemical polishing process has a first polishing rate for the initial conductive structure and a second polishing rate for the dielectric structure, and a ratio of the first polishing rate to the second polishing rate ranges from 2 to 8.

13. The method for forming a semiconductor structure according to claim 1, wherein: The substrate has a device structure therein, and the opening exposes the device structure.

14. The method for forming a semiconductor structure according to claim 1, wherein: The dielectric structure further includes an etch stop layer, the etch stop layer is located between the dielectric layer and the substrate, and the material of the etch stop layer is different from that of the dielectric layer; the opening is also located in the etch stop layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The opening includes a groove and a through hole located at the bottom of the groove, the groove is located in the dielectric layer, the through hole is located in the dielectric layer and the etch stop layer, the groove has a first projection on the substrate surface, the through hole has a second projection on the substrate surface, and the second projection is located within the first projection range.

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