Chip packaging structure, manufacturing method thereof, and electronic device

Abstract

The present application provides a chip packaging structure, a manufacturing method thereof, and an electronic device. The chip packaging structure includes a packaging substrate, a first chip, and a first packaging layer. The packaging substrate includes a first substrate and a second substrate. The first substrate includes a first dielectric layer and a first circuit layer disposed on the surface of the first dielectric layer. The second substrate includes a second dielectric layer covering the surface of the first circuit layer facing away from the first dielectric layer and a second circuit layer disposed on the surface of the second dielectric layer facing away from the first circuit layer. The second circuit layer includes an input pad and an output pad. The second substrate is provided with an opening that penetrates the second dielectric layer and the second circuit layer and exposes a part of the second circuit layer. The first chip is disposed in the opening and electrically connected to the first circuit layer. The first packaging layer is filled in the opening and covers the first chip.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and particularly to a chip packaging structure, a manufacturing method of the chip packaging structure, and an electronic device including the chip packaging structure. Background Art

[0002] With the development of electronic technologies, users have higher and higher requirements for the performance of electronic devices, resulting in an increasing number of transistors in electronic devices, which requires larger and larger chip sizes. However, with the continuous development of electronic devices towards integration and ultra-thinness, the chips in electronic devices also have to develop towards miniaturization. Summary of the Invention

[0003] In view of this, it is necessary to provide a chip packaging structure conducive to miniaturization, a manufacturing method thereof, and an electronic device.

[0004] In a first aspect of the present application, a chip packaging structure is provided, including a packaging substrate, a first chip, and a first packaging layer. The packaging substrate includes a first substrate and a second substrate. The first substrate includes a first dielectric layer and a first circuit layer disposed on the surface of the first dielectric layer. The second substrate includes a second dielectric layer covering the surface of the first circuit layer facing away from the first dielectric layer and a second circuit layer disposed on the surface of the second dielectric layer facing away from the first circuit layer. The second circuit layer includes an input pad and an output pad. The second substrate is provided with an opening penetrating through the second dielectric layer and the second circuit layer and exposing a part of the second circuit layer. The first chip is disposed in the opening and electrically connected to the first circuit layer. The first packaging layer fills the opening and covers the first chip.

[0005] In some embodiments, the chip packaging structure further includes a metal layer covering the surface of the first dielectric layer facing away from the first circuit layer.

[0006] In some embodiments, the chip packaging structure further includes a first solder mask layer disposed on the surface of the second circuit layer facing away from the second dielectric layer and exposing the input pad and the output pad.

[0007] In some embodiments, the surface of the first solder mask layer facing away from the second circuit layer is flush with the surface of the first packaging layer exposed in the opening.

[0008] In some embodiments, the chip packaging structure further includes a third circuit layer, a second chip, and a second packaging layer. The third circuit layer is disposed on the surface of the first dielectric layer facing away from the first circuit layer. The second chip is electrically connected to the third circuit layer. The second packaging layer covers the second chip.

[0009] In some embodiments, the chip packaging structure further includes a second solder mask layer disposed on the surface of the third circuit layer facing away from the first dielectric layer and exposing a part of the third circuit layer. The second packaging layer is disposed on the surface of the second solder mask layer facing away from the first dielectric layer.

[0010] The second aspect of the present application provides an electronic device, including the chip packaging structure of any one of the above and a main board. The main board is disposed on one side of the chip packaging structure and is electrically connected to the input pads and the output pads.

[0011] The third aspect of the present application provides a method for manufacturing a chip packaging structure, including the following steps:

[0012] Provide a substrate, the substrate includes a base layer and two metal layers disposed on opposite sides of the base layer;

[0013] Press two first substrates on two surfaces of the substrate. The first substrate includes a first dielectric layer connected to the metal layer and a first conductor layer disposed on the surface of the first dielectric layer facing away from the first dielectric layer;

[0014] Process the first conductor layer to form a first circuit layer, and the first circuit layer includes a plurality of first connection pads disposed at intervals;

[0015] Form a nickel layer covering the plurality of first connection pads;

[0016] Press a second substrate on the surface of the first circuit layer facing away from the first dielectric layer. The second substrate includes a second dielectric layer covering the nickel layer and the first circuit layer and a second conductor layer disposed on the surface of the second dielectric layer facing away from the first circuit layer;

[0017] Process the second conductor layer to form a second circuit layer, and the second circuit layer includes input pads and output pads;

[0018] Separate the metal layer from the base layer to expose the metal layer to the external environment;

[0019] Remove a part of the second substrate corresponding to the plurality of first connection pads and the nickel layer to form an opening exposing the plurality of first connection pads;

[0020] Mount the first chip on the plurality of first connection pads and form a first encapsulation layer covering the first chip.

[0021] In some embodiments, the method for manufacturing the chip packaging structure further includes the following steps: form a first solder mask layer on the surface of the second circuit layer, and the first solder mask layer exposes the input pads and the output pads.

[0022] In some embodiments, the method for manufacturing the chip packaging structure further includes the following steps: process the metal layer to form a third circuit layer; mount a second chip on the third circuit layer; form a second encapsulation layer covering the second chip.

[0023] In the chip packaging structure, manufacturing method thereof, and electronic device provided by the embodiments of the present application, the first chip, the input pads and the output pads for connecting to the main board are located on the same side of the chip packaging structure in the thickness direction, and the first chip is embedded in the second substrate, reducing the overall thickness of the chip packaging structure and facilitating miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 FIG. is a schematic cross-sectional view of a substrate provided by an embodiment of the present application.

[0025] Figure 2 FIG. is a schematic cross-sectional view of the first substrate being laminated on both sides of the substrate shown in FIG. Figure 1 FIG. is a schematic cross-sectional view of a first circuit layer being formed on the surface of the first substrate shown in FIG.

[0026] Figure 3 FIG. is a schematic cross-sectional view of a dry film being laminated on the surface of the first circuit layer shown in FIG. Figure 2 FIG. is a schematic cross-sectional view of a seed layer being formed on the surface of the first dielectric layer shown in FIG.

[0027] Figure 4 FIG. is a schematic cross-sectional view of a nickel layer being formed on the surface of the seed layer shown in FIG. Figure 3 FIG. is a schematic cross-sectional view of a second substrate being laminated on the surface of the first circuit layer shown in FIG.

[0028] Figure 5 FIG. is a schematic cross-sectional view of a second circuit layer being formed on the surface of the second substrate shown in FIG. Figure 4 FIG. is a schematic cross-sectional view of a first solder mask layer being formed on the surface of the second circuit layer shown in FIG.

[0029] Figure 6 FIG. is a schematic cross-sectional view of the metal layer and the base layer of the structure shown in FIG. being separated. Figure 5 FIG. is a schematic cross-sectional view of an opening being formed on the surface of the second dielectric layer shown in FIG.

[0030] Figure 7 FIG. is a schematic cross-sectional view of a structure shown in FIG. Figure 6 FIG. is a schematic cross-sectional view of a second circuit layer being formed on the surface of the second substrate shown in FIG.

[0031] Figure 8 FIG. is a schematic cross-sectional view of a first solder mask layer being formed on the surface of the second circuit layer shown in FIG. Figure 7 FIG. is a schematic cross-sectional view of a second circuit layer being formed on the surface of the second substrate shown in FIG.

[0032] Figure 9 FIG. is a schematic cross-sectional view of a first solder mask layer being formed on the surface of the second circuit layer shown in FIG. Figure 8 FIG. is a schematic cross-sectional view of a first solder mask layer being formed on the surface of the second circuit layer shown in FIG.

[0033] Figure 10 FIG. is a schematic cross-sectional view of the metal layer and the base layer of the structure shown in FIG. being separated. Figure 9 FIG. is a schematic cross-sectional view of an opening being formed on the surface of the second dielectric layer shown in FIG.

[0034] Figure 11 FIG. is a schematic cross-sectional view of an opening being formed on the surface of the second dielectric layer shown in FIG. Figure 10 FIG. is a schematic cross-sectional view of an opening being formed on the surface of the second dielectric layer shown in FIG.

[0035] Figure 12 FIG. is a schematic cross-sectional view of a structure shown in FIG. Figure 11Cross-sectional schematic diagram after removing the nickel layer of the shown structure.

[0036] Figure 13 For Figure 12 Cross-sectional schematic diagram after removing the seed layer of the shown structure.

[0037] Figure 14 Cross-sectional schematic diagram of the encapsulation structure provided by an embodiment of the present application.

[0038] Figure 15 Cross-sectional schematic diagram of the electronic device provided by an embodiment of the present application.

[0039] Figure 16 Cross-sectional schematic diagram after forming the third circuit layer on the metal layer in another embodiment of the present application.

[0040] Figure 17 For Figure 16 Cross-sectional schematic diagram after forming the second solder mask layer on the third circuit layer.

[0041] Figure 18 Cross-sectional schematic diagram of the chip encapsulation structure provided by another embodiment of the present application.

[0042] Main component symbol description

[0043] Chip encapsulation structure 200

[0044] Substrate 10

[0045] Base layer 11

[0046] Metal layer 12

[0047] Removable adhesive film 13

[0048] First substrate 20

[0049] First dielectric layer 21

[0050] First conductor layer 22

[0051] First circuit layer 23

[0052] Seed layer 31

[0053] Nickel layer 32

[0054] Dry film 33

[0055] Second substrate 40

[0056] Second dielectric layer 41

[0057] Second conductor layer 42

[0058] Second circuit layer 43

[0059] Input pad 431

[0060] Output pad 432

[0061] First conductive structure 420

[0062] First blind via 410

[0063] First solder mask layer 50

[0064] Opening 40a

[0065] Package substrate 100

[0066] First chip 60

[0067] First encapsulation layer 70

[0068] Electronic device 300

[0069] Main board 310

[0070] Solder ball 320

[0071] Third circuit layer 121

[0072] Second connection pad 121a

[0073] Second chip 61

[0074] Second encapsulation layer 71

[0075] The following specific embodiments will further illustrate the embodiments of the present application in conjunction with the above drawings. Specific embodiments

[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the embodiments of the present application belong. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application.

[0077] In the present application, descriptions such as "first" and "second" are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0078] Embodiments of the present application are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate configurations) of the present application. Thus, differences in the illustrated shapes due to manufacturing processes and / or tolerances are foreseeable. Therefore, the embodiments of the present application should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, deviations in shape resulting from manufacturing. The regions shown in the figures are themselves merely schematic, their shapes are not intended to illustrate the actual shape of the device, and are not intended to limit the scope of the present application.

[0079] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the case of no conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0080] Please refer to Figures 1 to 14 , an embodiment of the present application provides a method for manufacturing a chip package structure 200, including the following steps.

[0081] Step S1, please refer to Figure 1 , provide a substrate 10. The substrate 10 includes a base layer 11 and two metal layers 12 disposed on opposite sides of the base layer 11.

[0082] The base layer 11 is used to support the metal layer 12. The material of the metal layer 12 may include copper, gold, silver, etc. In this embodiment, the metal layer 12 is a copper foil. In some embodiments, the waste removed after circuit board assembly can be used as the substrate 10.

[0083] In some embodiments, the base layer 11 is connected to the metal layer 12 through a tearable adhesive film 13 sandwiched between the base layer 11 and the metal layer 12, so as to facilitate separating the metal layer 12 from the surface of the base layer 11.

[0084] Step S2, please refer to Figure 2 , press two first substrates 20 on two surfaces of the substrate 10. The first substrate 20 includes a first dielectric layer 21 and a first conductor layer 22 disposed on the surface of the first dielectric layer 21. After pressing, the first dielectric layer 21 is connected to the metal layer 12 and sandwiched between the metal layer 12 and the first conductor layer 22.

[0085] The first dielectric layer 21 can be made of a resin material with high temperature resistance, and its material can be selected from at least one of polyimide (PI), polyethylene terephthalate (PET), polytetrafluoroethylene (PTFE), polyamide (PA), polypropylene (PP), polyethylene (PE), liquid crystal polymer (LCP), polyvinyl chloride polymer (PVC), etc. In this embodiment, the material of the first dielectric layer 21 is PTFE.

[0086] The first conductor layer 22 is made of a conductive material, and its material can include copper, gold, silver, etc. In this embodiment, the first conductor layer 22 is a copper foil.

[0087] Step S3, please refer to Figure 3 , process the first conductor layer 22 to form a first circuit layer 23. The first circuit layer 23 includes a plurality of first connection pads 231, and the plurality of first connection pads 231 are arranged at intervals.

[0088] In this embodiment, the first conductor layer 22 is processed by a photolithography process to form the first circuit layer 23. It can be understood that other conventional circuit manufacturing methods can also be used to form the first circuit layer 23, and this application is not limited.

[0089] Step S4, please refer to Figure 6 , form a seed layer 31 on the surface of the first dielectric layer 21, and form a nickel layer 32 on the surface of the seed layer 31. The nickel layer 32 completely covers the surfaces of the plurality of first connection pads 231 exposed on the surface of the first dielectric layer 21. The seed layer 31 covers a part of the surface of the first dielectric layer 21 provided with the first circuit layer 23 and is disposed close to the plurality of first connection pads 231. The material of the seed layer 31 is a metal, which is used to improve the adhesion between the nickel layer 32 and the first dielectric layer 21.

[0090] Specifically, step S4 includes the following steps: Step S41, please refer to Figure 4 , press a dry film 33 on the surface of the first circuit layer 23 facing away from the first dielectric layer 21, and expose and develop the dry film 33 to expose the plurality of first connection pads 231 and a part of the surface of the first dielectric layer 21. This part of the surface includes the surface of the first dielectric layer 21 between the plurality of first connection pads 231 and the surface of the first dielectric layer 21 surrounding the plurality of first connection pads 231; Step S42, please refer to Figure 5, a seed layer 31 is formed on the exposed surface of the first dielectric layer 21; Step S43, please refer to Figure 6 , a nickel layer 32 is formed on the seed layer 31 and the plurality of first connection pads 231, and the dry film 33 is removed to expose the first circuit layer 23, removing the part of the first connection pad 231 and the part of the first dielectric layer 21 corresponding to the nickel layer 32 and the first circuit layer 23.

[0091] The seed layer 31 can be formed on the surface of the first dielectric layer 21 by, but not limited to, a sputtering coating process. The nickel layer 32 can be formed on the surface of the seed layer 31 and the plurality of first connection pads 231 by, but not limited to, an electroless plating process.

[0092] Step S5, please refer to Figure 7 , a second substrate 40 is laminated on the surface of the first circuit layer 23 facing away from the first dielectric layer 21. The second substrate 40 includes a second dielectric layer 41 and a second conductor layer 42 disposed on the surface of the second dielectric layer 41. After lamination, the second dielectric layer 41 covers the nickel layer 32, the surface of the first circuit layer 23 exposed to the first dielectric layer 21 and the nickel layer 32, and the surface of the first dielectric layer 21 exposed to the first circuit layer 23 and the nickel layer 32, and the second conductor layer 42 is located on the surface of the second dielectric layer 41 facing away from the first dielectric layer 21.

[0093] The second dielectric layer 41 can be made of a resin material with high temperature resistance. The material of the second dielectric layer 41 and the material of the first dielectric layer 21 can be the same or different, and this application does not limit. In this embodiment, the material of the second dielectric layer 41 is PI. The second conductor layer 42 is made of a conductive material, and its material can include copper, gold, silver, etc. In this embodiment, the second conductor layer 42 is a copper foil.

[0094] Step S6, please refer to Figure 8 , the second conductor layer 42 is processed to form a second circuit layer 43. The second circuit layer 43 includes input pads 431 and output pads 432 disposed at intervals. The input pads 431 and the output pads 432 are used to connect to the main board to supply power to the second circuit layer 43 and the first circuit layer 23. The second circuit layer 43 also exposes the surface of the part of the second dielectric layer 41 corresponding to the nickel layer 32.

[0095] In this embodiment, a photolithography process is used to process the second conductor layer 42 to form the second circuit layer 43. It can be understood that other conventional circuit manufacturing methods can also be used to form the second circuit layer 43, and this application does not limit.

[0096] The second circuit layer 43 is electrically connected to the first circuit layer 23 through a first conductive structure 420 that penetrates the second dielectric layer 41. The first conductive structure 420 can be obtained by the following method: forming a first blind via 410 that penetrates the second dielectric layer 41 and exposes a part of the first circuit layer 23, and forming the first conductive structure 420 in the first blind via 410 by processes such as electroplating and printing.

[0097] Step S7, please refer to Figure 9 , form a first solder mask layer 50 on the surface of the second circuit layer 43. The first solder mask layer 50 exposes a part of the surface of the input pad 431 and a part of the surface of the output pad 432.

[0098] The first solder mask layer 50 is used to protect the second circuit layer 43 and prevent oxidation or soldering short circuit of the second circuit layer 43. The first solder mask layer 50 can be formed on the surface of the second circuit layer 43 by a printing process using solder mask ink, but is not limited thereto.

[0099] Step S8, please refer to Figure 10 , board separation: separate the metal layer 12 from the base layer 11 to expose the metal layer 12 to the external environment.

[0100] When the metal layer 12 and the base layer 11 are separated, the metal layer 12 and the first substrate and the second substrate located on the side of the metal layer 12 away from the base layer 11 are separated as a whole to form a packaging substrate. Through board separation, the Figure 9 shown stacked structure is divided into a structure that can form two packaging substrates, improving the processing efficiency.

[0101] Step S9, please refer to Figure 11 , remove a part of the second dielectric layer 41 corresponding to the position of the nickel layer 32 to form an opening 40a that exposes the nickel layer 32.

[0102] The opening 40a exposes the entire nickel layer 32 to facilitate the removal of the nickel layer 32 through the opening 40a. The opening 40a can be formed by methods such as laser cutting and mechanical cutting, but is not limited thereto.

[0103] Step S10, please refer to Figure 12 , remove the nickel layer 32 to expose a plurality of first connection pads 231 and the seed layer 31 in the opening 40a. The nickel layer 32 can be removed by an etching process, but is not limited thereto.

[0104] Step S11, please refer to Figure 13 , remove the seed layer 31 to expose a part of the surface of the first dielectric layer 21 to obtain the packaging substrate 100. The seed layer 31 can be removed by an etching process, but is not limited thereto.

[0105] The encapsulation substrate 100 includes a metal layer 12, a first substrate 20, a second substrate 40, and a first solder mask layer 50. The first substrate 20 includes a first dielectric layer 21 and a first circuit layer 23 disposed on one surface of the first dielectric layer 21. The first dielectric layer 21 covers one surface of the metal layer 12, and the first circuit layer 23 is located on the surface of the first dielectric layer 21 facing away from the metal layer 12. The second substrate 40 includes a second dielectric layer 41 and a second circuit layer 43 disposed on one surface of the second dielectric layer 41. The second dielectric layer 41 covers the surface of the first circuit layer 23 facing away from the first dielectric layer 21 and is connected to the first dielectric layer 21. The second substrate 40 is provided with openings 40a that penetrate through the second dielectric layer 41 and the second circuit layer 43 and expose a plurality of first connection pads 231 of the first circuit layer 23. The input pad 431 and the output pad 432 of the second circuit layer 43 are located on both sides of the opening 40a and are electrically connected to the first circuit layer 23 through a first conductive structure 420, so that the second circuit layer 43 and the first circuit layer 23 are electrically connected.

[0106] The first solder mask layer 50 covers the surface of the second circuit layer 23 and exposes the input pad 431 and the output pad 432.

[0107] Step S12, please refer to Figure 14 , mount the first chip 60 on the first connection pads 231, and fill the opening 40a with an encapsulation material to form a first encapsulation layer 70, obtaining a chip encapsulation structure 200. The first chip 60 is received in the opening 40a. The first encapsulation layer 70 covers the first chip 60 and fills the gap between the first chip 60 and the opening 40a, so that the first chip 60 is embedded in the first encapsulation layer 70. The first chip 60 can be electrically connected to the first connection pads 231 by, but not limited to, a flip-chip packaging method.

[0108] In some embodiments, the material of the first encapsulation layer 70 is a non-conductive material, and the non-conductive material includes one or more of injection molding materials such as EMC (Epoxy Molding Compound), ABS (Acrylonitrile Butadiene Styrene), PC (Polycarbonate), and PET (Polyethylene Terephthalate).

[0109] In some embodiments, the surface of the first encapsulation layer 70 exposed in the opening 40a is flush with the surface of the first solder mask layer 50 facing away from the second dielectric layer 41.

[0110] It can be understood that the order of the above steps and subsequent steps can be adjusted as needed. For example, step S7 can be executed after step S8, step S9, step S10, step S11, or step S12.

[0111] In the chip packaging structure 200 provided by the embodiment of the present application, the first chip 60 and the input pads 431 and output pads 432 for connecting to the main board are located on the same side of the chip packaging structure 200 in the thickness direction, and the first chip 60 is embedded in the second substrate 40, reducing the overall thickness of the chip packaging structure 200 and facilitating miniaturization. In addition, the metal layer 12 has a continuous structure as a whole, which is located on the side of the chip packaging structure 200 facing away from the first chip 60 and corresponds to the position of the first chip 60, and can achieve electrostatic shielding.

[0112] Please refer to Figure 15 , an embodiment of the present application provides an electronic device 300, including a chip packaging structure 200 and a main board 310. The main board 310 is disposed on the side of the chip packaging structure 200 where the input pads 431 and output pads 432 are provided, and is electrically connected to the input pads 431 and output pads 432 to supply power to the chip packaging structure 200. The main board 310 can be electrically connected to the input pads 431 and output pads 432 through solder balls 320.

[0113] In some embodiments, after step S8, the manufacturing method of the chip packaging structure 200 further includes the following steps.

[0114] Step S81, please refer to Figure 16 , the metal layer 12 is processed to form a third circuit layer 121. The third circuit layer 121 includes a plurality of second connection pads 121a arranged at intervals.

[0115] In this embodiment, the metal layer 12 is processed by a photolithography process to form the third circuit layer 121. It can be understood that other conventional circuit manufacturing methods can also be used to form the third circuit layer 121, and the present application does not make any restrictions.

[0116] The third circuit layer 121 is electrically connected to the first circuit layer 23 through a second conductive structure 122 penetrating the first dielectric layer 21. The second conductive structure 122 can be obtained by the following method: forming a second blind hole penetrating the first dielectric layer 21 and exposing a part of the first circuit layer 23, and forming the second conductive structure 122 in the second blind hole through processes such as electroplating and printing.

[0117] Step S82, please refer to Figure 17 , a second solder resist layer 51 is formed on the surface of the third circuit layer 121, and a part of the surface of the second connection pads 121a is exposed by the second solder resist layer 51.

[0118] Step S83, please refer to Figure 18, the second chip 61 is mounted on the second connection pad 121a, and a second encapsulation layer 71 covering the second chip 61 is formed. The second encapsulation layer 71 also covers the surface of the second solder mask layer 51 facing away from the third circuit layer 121 and fills the gap between the second chip 61 and the second connection pad 121a. The second chip 61 can be electrically connected to the second connection pad 121a by, but not limited to, flip-chip packaging. Encapsulating the second chip 61 on the side of the chip packaging structure 200 facing away from the first chip 60 improves the integration of the chip packaging structure 200 and is conducive to miniaturization.

[0119] The above description is some specific embodiments of the present application, but in actual application, it cannot be limited to these embodiments only. For those of ordinary skill in the art, other deformations and changes made according to the technical concept of the present application should fall within the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that, Comprising: A packaged substrate, the packaged substrate includes a first substrate and a second substrate, the first substrate includes a first dielectric layer and a first circuit layer disposed on the surface of the first dielectric layer, and the entire first circuit layer protrudes from the surface of the first dielectric layer. The second substrate includes a second dielectric layer and a second circuit layer. The second dielectric layer covers the surface of the first circuit layer facing away from the first dielectric layer. The second circuit layer is disposed on the surface of the second dielectric layer facing away from the first circuit layer, and the entire second circuit layer protrudes from the surface of the second dielectric layer. The second circuit layer includes an input pad and an output pad. The second substrate is provided with an opening that penetrates the second dielectric layer and the second circuit layer and exposes a part of the first circuit layer. A first chip, the first chip is disposed in the opening and electrically connected to the first circuit layer. And A first encapsulation layer, the first encapsulation layer fills the opening and encapsulates the first chip.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a metal layer, and the metal layer covers the surface of the first dielectric layer facing away from the first circuit layer.

3. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a first solder mask layer, the first solder mask layer is disposed on the surface of the second circuit layer facing away from the second dielectric layer, and exposes the input pad and the output pad.

4. The chip packaging structure according to claim 3, characterized in that, The surface of the first solder mask layer facing away from the second circuit layer is flush with the surface of the first encapsulation layer exposed in the opening.

5. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a third circuit layer, a second chip, and a second encapsulation layer. The third circuit layer is disposed on the surface of the first dielectric layer facing away from the first circuit layer. The second chip is electrically connected to the third circuit layer. The second encapsulation layer encapsulates the second chip.

6. The chip packaging structure according to claim 5, characterized in that, The chip packaging structure further includes a second solder mask layer, the second solder mask layer is disposed on the surface of the third circuit layer facing away from the first dielectric layer and exposes a part of the third circuit layer. The second encapsulation layer is disposed on the surface of the second solder mask layer facing away from the first dielectric layer.

7. An electronic device, characterized in that, Comprising the chip packaging structure according to any one of claims 1-6 and a main board, the main board is disposed on one side of the chip packaging structure and electrically connected to the input pad and the output pad.

8. A method for manufacturing a chip packaging structure, characterized in that, Comprising the following steps: Providing a substrate, the substrate includes a base layer and two metal layers disposed on opposite sides of the base layer. Pressing two first substrates on two surfaces of the substrate. The first substrate includes a first dielectric layer connected to the metal layer and a first conductor layer disposed on the surface of the first dielectric layer facing away from the first dielectric layer. Processing the first conductor layer to form a first circuit layer, the first circuit layer includes a plurality of first connection pads disposed at intervals. Forming a nickel layer covering the plurality of first connection pads. Pressing a second substrate on the surface of the first circuit layer facing away from the first dielectric layer. The second substrate includes a second dielectric layer covering the nickel layer and the first circuit layer and a second conductor layer disposed on the surface of the second dielectric layer facing away from the first circuit layer. Processing the second conductor layer to form a second circuit layer, the second circuit layer includes an input pad and an output pad. Separate the metal layer from the base layer to expose the metal layer to the external environment; Remove a part of the second substrate corresponding to the plurality of first connection pads and the nickel layer to form an opening exposing the plurality of first connection pads; Mount the first chip on the plurality of first connection pads and form a first encapsulation layer covering the first chip.

9. The method for manufacturing a chip packaging structure according to claim 8, characterized in that, It further includes the following steps: Form a first solder mask layer on the surface of the second circuit layer, and the first solder mask layer exposes the input solder pads and the output solder pads.

10. The method for manufacturing a chip packaging structure according to claim 8, characterized in that, It further includes the following steps: Process the metal layer to form a third circuit layer; Mount a second chip on the third circuit layer; Form a second encapsulation layer covering the second chip.

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