A multi-channel DMA implementation method based on FPGA

Abstract

The present invention provides a multi-channel DMA implementation method based on FPGA, PS divides and manages DDR memory, and transmits control information to DMA_CTRL in PL, DMA_CTRL transmits data between PS and PL according to the direction and control information of data transmission, and allocates two BUFFs to each channel of DMA, and ensures that PS and PL will not operate the same BUFF at the same time during data transmission. Multi-channel DMA, multi-address, and highly flexible data transmission can be realized, in order to solve the problem of reducing the occupancy rate of logic resources during DMA data transmission, only single-channel DMA is needed for time-division multiplexing during multi-channel data transmission, which reduces the time cost of logic development and the cost of hardware selection.

Description

Technical Field

[0001] The present invention relates to the technical field of large data transmission interaction, and also to technical fields such as segmented memory management, DMA transmission time-sharing multiplexing, AXI bus application, high-speed DMA interface processing, and more specifically to a multi-channel DMA implementation method based on FPGA. Background Art

[0002] Computer technology is becoming more and more mature. In the field of big data, storage capacity and data have been greatly improved, and the requirements for the capacity and read and write speed of storage devices are more stringent. FPGA (field programmable gate array) is a programmable array with multiple embedded soft cores. It is more and more widely used in the field of high-speed signals. The data transmission between FPGA and computer usually adopts DMA (direct memory access) transmission method to speed up the data transmission speed and reduce the CPU load. The DMA controller can move data from one address space (computer) to another address space (FPGA). The moving process does not require CPU participation, thus saving CPU resources. However, the traditional DMA application method realizes the transfer of data from one address to another. When data with multiple addresses needs to be transmitted, multiple DMAs are required, which will lead to a large logic resource occupancy rate. Many programmable systems with small logic resources cannot support the simultaneous existence of multiple DMAs, so the hardware cost is greatly increased in chip selection.

[0003] The existing DMA application technology realizes one-to-one transmission, which has low resource utilization and high requirements on logic resources and hardware costs when transmitting multiple data channels.

[0004] The above-mentioned record of background technical knowledge is intended to help ordinary technicians in this field understand the existing technologies that are relatively close to the present invention, and at the same time facilitate the understanding of the inventive concept and technical solution of the present invention. It should be clear that in the absence of clear evidence that the above-mentioned content has been disclosed before the filing date of this patent application, the above-mentioned background technology should not be used to evaluate the novelty of the technical solution of this application. Summary of the invention

[0005] Technical issues

[0006] In order to solve the above problems and the problems of low transmission speed and high resource occupancy when transmitting large data between PS and PL in a fully programmable system on chip, the purpose of the present invention is to provide a multi-channel DMA data transmission method based on FPGA, which can be embedded in the FPGA of any platform as a universal IP, and realize fast and flexible transmission of multi-channel data with very small resource occupancy.

[0007] Technical Solution

[0008] In order to achieve the above-mentioned objectives, the inventors of this application conducted in-depth research and discovered a multi-channel DMA data transmission method based on FPGA, which can realize multi-channel DMA, multi-address, and highly flexible data transmission. In order to solve the problem of reducing the occupancy rate of logic resources during DMA data transmission, only a single-channel DMA is needed for time-sharing multiplexing during multi-channel data transmission, which reduces the time cost of logic development and the cost of hardware selection.

[0009] That is, the present invention is:

[0010] A multi-channel DMA implementation method based on FPGA, comprising:

[0011] PS divides and manages DDR memory and passes control information to DMA_CTRL in PL. According to the direction and control information of data transmission, DMA_CTRL transfers data between PS and PL and allocates two BUFFs to each DMA channel. During data transmission, PS and PL are ensured not to operate the same BUFF at the same time.

[0012] The FPGA-based multi-channel DMA implementation method proposed in the present invention ensures that the PS and PL will not operate the same BUFF at the same time during the data transmission process, and can realize multi-channel, multi-address, fast and flexible transmission of multi-channel data with minimum resource consumption and smaller hardware resource requirements, which is conducive to significantly reducing hardware costs and development time costs. It is not only suitable for fully programmable on-chip systems, but also can be applied to other FPGA chips to realize the transmission of large data.

[0013] Furthermore, the PS partitioning and managing the DDR memory means partitioning at least one BUFF in the DDR memory.

[0014] Furthermore, the control information includes memory address and division rule information.

[0015] Furthermore, the PS determines the currently operable BUFF by way of status query.

[0016] Furthermore, PL schedules DMA through the configuration information of PS, and each DMA channel has a data cache FIFO.

[0017] Furthermore, the DMA_CTRL transmitting the data between the PS and the PL includes the DMA_CTRL transmitting the data from the BUFF corresponding to the DDR to the FIFO corresponding to the PL.

[0018] Furthermore, the DMA_CTRL transfers data from the BUFF corresponding to the DDR to the corresponding FIFO in the PL by performing the following steps: when the DMA_CTRL receives a data transmission request, the DMA_CTRL controls the DMA_IP to read data from the BUFF corresponding to the DDR and store it in the corresponding FIFO. When the data in the FIFO is reduced to a set threshold, the DMA_CTRL will automatically supplement the data in the FIFO until the data length reaches the set transmission length.

[0019] Furthermore, the DMA_CTRL transmitting the data between the PS and the PL includes the DMA_CTRL transmitting the data from the FIFO corresponding to the PL to the BUFF corresponding to the DDR.

[0020] Furthermore, DMA_CTRL transfers data from the FIFO corresponding to PL to the BUFF corresponding to DDR by performing the following steps: When DMA_CTRL receives a data transfer request, DMA_CTRL automatically transfers the data in the FIFO to the BUFF corresponding to DDR according to the burst length of DMA until the length of the transferred data reaches the set transfer length.

[0021] Furthermore, when multiple channels apply for DMA transmission at the same time, DMA_CTRL will schedule DMA to perform time-sharing transmission on the data of different channels, so that a single DMA can perform time-sharing transmission on multiple channels. Time-sharing transmission on different channel data can make full use of the performance of DMA high-speed transmission, so that a single DMA can perform time-sharing transmission on multiple channels, significantly improving the efficiency of data transmission.

[0022] A multi-channel DMA data transmission method based on FPGA, the method executes at least one step of the aforementioned multi-channel DMA implementation method based on FPGA.

[0023] A computer device, comprising a memory, a processor, a communication interface and a communication bus; wherein the memory, the processor and the communication interface communicate with each other via the communication bus; the memory is used to store computer programs; the processor is used to execute the computer programs stored in the memory, and when the processor executes the computer program, at least one step of the aforementioned FPGA-based multi-channel DMA implementation method or at least one step of the aforementioned FPGA-based multi-channel DMA data transmission method is implemented.

[0024] Based on the common knowledge in this field, the above-mentioned preferred conditions can be combined with each other to obtain a specific implementation method.

[0025] Beneficial Effects

[0026] According to the present invention, by dividing and managing the DDR memory, the DDR memory is divided into multiple BUFFs, and DMA_CTRL transmits data between PS and PL according to the memory address and the division rule information, and two BUFFs are allocated to each channel of DMA, so as to ensure that PS and PL will not operate the same BUFF at the same time during the data transmission process. Multi-channel DMA, multi-address, and highly flexible data transmission can be realized. In order to solve the problem of reducing the occupancy rate of logic resources during DMA data transmission, only a single-channel DMA is needed for time-division multiplexing during multi-channel data transmission, which reduces the time cost of logic development and the cost of hardware selection.

[0027] When multiple channels apply for DMA transmission at the same time, DMA_CTRL will schedule DMA to perform time-sharing transmission on the data of different channels, so that a single DMA can transmit the data of multiple channels in time-sharing mode, making full use of the performance of DMA high-speed transmission.

[0028] The FPGA-based multi-channel DMA implementation method or data transmission method provided by the present invention can be applied to a fully programmable system on chip for big data interaction between PS and PL, and can also be applied to other FPGA chips to achieve efficient transmission of big data.

[0029] The present invention adopts the above technical solution to achieve the above purpose, which makes up for the shortcomings of the prior art and has reasonable design and convenient operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to make the above and / or other purposes, features, advantages and examples of the present invention more obvious and easy to understand, the drawings required for use in the specific implementation of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A system architecture diagram showing a multi-channel DMA implementation method based on FPGA;

[0032] Figure 2 A flow chart showing a data transmission method;

[0033] Figure 3 A flowchart showing the data transmission direction from PS to PL;

[0034] Figure 4 Flowchart showing the data transmission direction from PL to PS. DETAILED DESCRIPTION

[0035] Those skilled in the art can refer to the content of this article and appropriately replace and / or modify the process parameters to achieve the same. However, it should be particularly noted that all similar replacements and / or modifications are obvious to those skilled in the art and are considered to be included in the present invention. The products and preparation methods described in the present invention have been described through preferred examples. It is obvious that relevant personnel can modify or appropriately change and combine the products and preparation methods described herein without departing from the content, spirit and scope of the present invention to implement and apply the technology of the present invention.

[0036] Unless otherwise defined, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. The present invention uses the methods and materials described herein; however, other suitable methods and materials known in the art may also be used. The materials, methods, and examples described herein are illustrative only and are not intended to be limiting. All publications, patent applications, patents, provisional applications, database entries, and other references mentioned herein are incorporated herein by reference in their entirety. In the event of a conflict, the present specification, including definitions, shall prevail.

[0037] Unless specifically stated, the materials, methods, and examples described herein are illustrative only and not limiting. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods and materials are still described herein.

[0038] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. At the same time, the embodiments in this application and the features in the embodiments can be combined with each other without conflict.

[0039] In order to facilitate understanding of the embodiments of the present invention, the abbreviations and key terms that may be involved in the embodiments of the present invention are first explained or defined. For undefined abbreviations or key terms, they are commonly understood by those skilled in the art.

[0040] FPGA: Field Programmable Gate Array, field programmable gate array;

[0041] DMA: Direct Memory Access, direct memory access;

[0042] PS: Processing System, the part of ARM's SOC that is not related to FPGA;

[0043] PL: Programmable Logic, i.e. FPGA part;

[0044] MCDMA: Multi-channel DMA, multi-channel DMA data transmission mode;

[0045] BUFF: memory segment in DDR;

[0046] DDR_CTRL: DDR controller;

[0047] AXI: internal transmission bus;

[0048] DMA_IP: DMA IP core;

[0049] DMA_CTRL: DMA control and scheduling unit;

[0050] FIFO: Data cache unit in PL;

[0051] DMA_write: DMA write data module;

[0052] DMA_read: DMA read data module;

[0053] Application unit: A module in the PL that uses the data in the FIFO.

[0054] The present invention is described in detail below

[0055] Embodiment 1:

[0056] A multi-channel DMA implementation method based on FPGA is provided, including: PS divides and manages DDR memory, and passes memory address and division rule information to DMA_CTRL in PL; according to the direction and control information of data transmission, DMA_CTRL transmits data between PS and PL, and allocates two BUFFs to each channel of DMA. During data transmission, it is ensured that PS and PL will not operate the same BUFF at the same time.

[0057] like Figure 1 As shown in the figure, the system architecture of the FPGA-based multi-channel DMA implementation method includes:

[0058] PS part:

[0059] The PS part manages the DDR memory, divides multiple BUFFs in the DDR memory, allocates two BUFFs to each DMA channel, and passes the memory address and division rule information to the DMA_CTRL in the PL to ensure that data can be transmitted continuously during data transmission and that the PS and PL will not operate the same BUFF at the same time. The PS determines the currently operable BUFF through status query.

[0060] PL part

[0061] The PL part schedules DMA through the configuration information of PS. Each DMA channel has a data buffer FIFO. When the data in the BUFF is reduced to the set threshold, the DMA will automatically replenish the data in the BUFF. When multiple channels are started at the same time, the DMA scheduling module will coordinate DMA to transmit data from different channels, so that a single DMA can transmit data from multiple channels in a time-sharing manner.

[0062] Data Transfer

[0063] According to the direction and control information of the data to be transmitted, DMA_CTRL transfers the data between PS and PL:

[0064] 1. When the transmission direction is from PS DDR to PL FIFO, when DMA_CTRL receives a data transfer request, DMA_CTRL controls DMA_IP to read data from the BUFF corresponding to DDR and store it in the corresponding FIFO. When the data in the FIFO is reduced to the set threshold, DMA_CTRL will automatically supplement the data in the FIFO until the data length reaches the set transmission length.

[0065] 2. When the transmission direction is from PL's FIFO to PS's DDR, after DMA_CTRL receives a data transfer request, DMA_CTRL automatically transfers the data in FIFO to the BUFF corresponding to DDR according to the DMA burst length until the transmitted data length reaches the set transmission length.

[0066] 3. When multiple channels apply for DMA transmission at the same time, DMA_CTRL will schedule DMA to perform time-sharing transmission on the data of different channels, so that a single DMA can transmit the data of multiple channels in time-sharing mode, making full use of the performance of DMA high-speed transmission.

[0067] By dividing the DDR memory into multiple BUFFs, data is transferred between PS and PL, and two BUFFs are allocated to each DMA channel. During the data transmission process, it is ensured that PS and PL will not operate the same BUFF at the same time, which can realize multi-channel DMA, multi-address, and highly flexible data transmission. In order to solve the problem of reducing the occupancy rate of logic resources during DMA data transmission, only a single DMA is needed for time-sharing multiplexing during multi-channel data transmission, which reduces the time cost of logic development and the cost of hardware selection. When multiple channels apply for DMA transmission at the same time, DMA_CTRL will schedule DMA to perform time-sharing transmission of data from different channels, so that a single DMA can transmit data from multiple channels in time. Make full use of the performance of DMA high-speed transmission.

[0068] Embodiment 2:

[0069] like Figure 2 The process shown provides a data transmission method, including:

[0070] Step S1: receiving a control instruction from a host computer, wherein the control instruction includes: a DMA start address, a DMA size, a DMA mode and a DMA start command.

[0071] The host computer is a computer that interacts with the FPGA for data. As for the specific content of the control instruction sent by the host computer, as long as the corresponding DMA channel can be selected from multiple DMA channels according to the control instruction to transmit the data through the AXI bus, avoiding complex processing methods such as packaging and unpacking of each type of data, this embodiment is not subject to any restrictions.

[0072] It should be understood that before or after this step, the host computer may also configure the cache space, that is, the host computer first places the data to be transmitted in the cache space or opens up a free storage space to prepare for receiving data, and then sends a control instruction to the DMA controller.

[0073] Step S2: selecting the corresponding DMA channel from the multiple DMA channels according to the control instruction, and transmitting data through the AXI bus; wherein the multiple DMA channels are independent of each other.

[0074] During the working process, the PS divides one or more buffers in the DDR memory, and passes the control information including the memory address and division rule information to the DMA control and scheduling unit in the PL. The DMA control and scheduling unit transfers the data between the PS and the PL according to the control information: when the transmission direction is from the PS to the PL, that is, from the DDR of the PS to the FIFO of the PL, after the DMA control and scheduling unit receives the data transfer request, it controls the DMA IP core to read the data from the BUFF corresponding to the DDR and stores it in the corresponding FIFO of the PL. When the data in the FIFO is reduced to the set threshold, the DMA control and scheduling unit will automatically supplement the data in the FIFO until the data length reaches the set transmission length; when the transmission direction is from the PL to the PS, that is, from the FIFO of the PL to the DDR of the PS, after the DMA control and scheduling unit receives the data transfer request, according to the DMA burst length, the DMA control and scheduling unit automatically transfers the data in the FIFO to the BUFF corresponding to the DDR until the length of the transmitted data reaches the set transmission length.

[0075] The operation of the multi-channel DMA data transmission method specifically includes:

[0076] like Figure 3 The process shown is when the data transmission direction is from PS to PL:

[0077] 1) PS configures the control information to DMA_CTRL in PL;

[0078] 2) PS stores the data in the memory specified by DDR;

[0079] 3) DMA_CTRL starts DMA transfer after receiving the start transfer signal;

[0080] 4) DMA_CTRL controls DMA_IP to read the data in BUFF through AXI bus and DDR_CTRL;

[0081] 5) DMA_CTRL puts the read data into the specified FIFO for use by other modules such as the application unit;

[0082] 6) When multiple channels apply for DMA transfer at the same time, DMA_CTRL will transfer the data of multiple channels in time-sharing.

[0083] like Figure 4 The process shown is when the data transmission direction is from PL to PS:

[0084] 1) PS configures the control information to DMA_CTRL in PL;

[0085] 2) DMA_CTRL starts DMA transfer after receiving the start transfer signal;

[0086] 3) DMA_CTRL writes the data in the specified FIFO into the BUFF corresponding to DDR through AXI bus and DDR_CTRL via DMA_IP;

[0087] 4) PS uses the data in the DDR specified BUFF according to the transmission status;

[0088] 5) When multiple channels apply for DMA transfer at the same time, the DMA controller will transfer the data of multiple channels in time-sharing;

[0089] Among them, after step 3), after the data is written, the FPGA sends a data write completion signal to the DMA_CTRL controller, and the DMA_CTRL initiates a DMA completion abort instruction to the CPU software. The CPU software responds to the abort instruction and then proceeds to step 4). When new data is received from the application unit and needs to be transmitted to the BUFF of the PS part, the scheme of the present invention omits the data receiving interruption step of the application unit, and also omits the CPU's response to the data receiving interruption step. In the data transmission process, it is ensured that the PS and PL will not operate the same BUFF at the same time, and the CPU initializes the memory buffer for receiving data. Therefore, it is conducive to simplifying the transmission steps, reducing the consumption of FPGA storage resources and the delay of the data transmission program, reducing the CPU activation rate and CPU power consumption, and improving the data transmission efficiency.

[0090] It can be understood that the DMA control and scheduling unit selects the corresponding DMA channel from multiple DMA channels according to the control instruction to transmit data through the AXI bus, which can be a method of first de-framing and command parsing the control instruction, obtaining a slave transaction request, then processing the slave transaction request, generating DMA parameters, and then generating a DMA control signal according to the DMA parameters, and finally selecting the corresponding DMA channel from multiple DMA channels according to the DMA control signal to perform DMA reading and / or DMA writing through the AXI bus, wherein DMA reading is performed by a DMA read data module (DMA_read), and DMA writing is performed by a DMA write data module (DMA_write); the above method is not limited, as long as the corresponding DMA channel can be selected from multiple DMA channels according to the control instruction to perform DMA reading and / or DMA writing operations through the AXI bus, and similarly, the method of parsing the control instruction by the DMA control and scheduling unit is not limited. Multiple DMA channels are independent of each other and can be started at the same time. The designer or user can independently set the DMA operation parameters according to the practical scenario or user needs. The DMA can coordinate the data transmission of different channels, thereby achieving the purpose of a single DMA time-sharing multiplexing transmission of data of multiple channels.

[0091] It should be noted that after the above steps, the steps of generating interrupt information after the transmission is completed and sending the interrupt information to the host computer in the MSI interrupt mode or the inherited interrupt INTx mode can also be included. By sending the interrupt information to the host computer, the host computer can start the interrupt service program to determine whether the DMA transmission is successful. If it is unsuccessful, it can be retransmitted according to user needs. If it is successful, the next transmission can be continued. This embodiment does not impose any restrictions on the specific process of the interrupt service program started by the host computer.

[0092] The key points of the present invention are single-channel DMA multi-channel multiplexing, multi-address management technology, data synchronization technology, data real-time design, etc., which realize a multi-channel DMA, multi-address, and highly flexible data transmission method. During DMA data transmission, the occupancy rate of logic resources is reduced. During multi-channel data transmission, only single-channel DMA is needed for time-division multiplexing, which reduces the time cost of logic development and the cost of hardware selection. Therefore, the method has the advantages of less consumption of logic resources, higher flexibility, and less requirements for hardware resources, which can greatly reduce the hardware cost and development time cost, is suitable for fully programmable chip systems, and is used for large data interaction between PS and PL. It can also be applied to other FPGA chips to realize the transmission of large data.

[0093] Embodiment 3:

[0094] A computer device, comprising a memory, a processor, a communication interface and a communication bus; wherein the memory, the processor and the communication interface communicate with each other via the communication bus; the memory is used to store computer programs; the processor is used to execute the computer programs stored in the memory, and when the processor executes the computer program, at least one step of the aforementioned FPGA-based multi-channel DMA implementation method or at least one step of the aforementioned FPGA-based multi-channel DMA data transmission method is implemented.

[0095] The memory is also a computer-readable storage medium, including permanent and non-permanent, removable and non-removable media, and information storage can be achieved by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PR AM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0096] The conventional techniques in the above embodiments are prior arts known to those skilled in the art, and thus will not be described in detail here.

[0097] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

[0098] Although the present invention has been described in detail and some specific embodiments have been cited, it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention.

[0099] Although the above-mentioned specific embodiments have been shown, described and pointed out the novel features applied to various embodiments, it should be understood that various omissions, substitutions and changes can be made to the form and details of the described device or method without departing from the spirit of the present disclosure. In addition, the above-mentioned various features and methods can be used independently of each other, or can be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of the present disclosure. Many of the above-mentioned embodiments include similar components, and therefore, these similar components are interchangeable in different embodiments. Although the present invention has been disclosed in the context of certain embodiments and examples, it should be understood by those skilled in the art that the present invention can extend beyond the specifically disclosed embodiments to other alternative embodiments and / or applications and obvious modifications and equivalents thereof. Therefore, the present invention is not intended to be limited by the specific disclosure of the preferred embodiments herein.

[0100] Matters not covered in the present invention are all known technologies.

Claims

1. A multi-channel DMA implementation method based on FPGA, characterized in that: PS divides and manages DDR memory and passes control information to DMA_CTRL in PL. According to the direction and control information of data transmission, DMA_CTRL transmits data between PS and PL through AXI bus. Two BUFFs are allocated to each DMA channel. During data transmission, PS and PL are ensured not to operate the same BUFF at the same time. The DMA_CTRL transmits data between the PS and the PL through the AXI bus, including the DMA_CTRL transmitting data from the BUFF corresponding to the DDR to the corresponding FIFO in the PL, and executing the following steps: when the DMA_CTRL receives a data transmission request, the DMA_CTRL controls the DMA_IP to read data from the BUFF corresponding to the DDR and store it in the corresponding FIFO. When the data in the FIFO is reduced to a set threshold, the DMA_CTRL will automatically supplement the data in the FIFO until the data length reaches the set transmission length, specifically including: 1) the PS configures the control information to the DMA_CTRL in the PL; 2) the PS stores the data in the memory specified by the DDR; 3) the DMA_CTRL starts the DMA transmission after receiving the start transmission signal; 4) the DMA_CTRL controls the DMA_IP to read the data in the BUFF through the AXI bus and the DDR_CTRL; 5) the DMA_CTRL puts the read data into the specified FIFO for use by other modules such as the application unit; 6) when multiple channels apply for DMA transmission at the same time, the DMA_CTRL will transmit the data of multiple channels in time-sharing; The DMA_CTRL transmits data between the PS and the PL through the AXI bus, including the DMA_CTRL transmitting data from the FIFO corresponding to the PL to the BUFF corresponding to the DDR, and executing the following steps: when the DMA_CTRL receives a data transmission request, the DMA_CTRL automatically transfers the data in the FIFO to the BUFF corresponding to the DDR according to the DMA burst length, until the length of the transmitted data reaches the set transmission length, specifically including: 1) the PS configures the control information to the DMA_CTRL in the PL; 2) the DMA_CTRL starts the DMA transmission after receiving the start transmission signal; 3) the DMA_CTRL writes the data in the specified FIFO to the BUFF corresponding to the DDR through the AXI bus and the DDR_CTRL through the DMA_IP; 4) the PS uses the data in the BUFF specified by the DDR according to the transmission status; 5) when multiple channels apply for DMA transmission at the same time, the DMA controller will transmit the data of multiple channels in time-sharing; wherein, after step 3), after the data is written, the FPGA sends a data write completion signal to the DMA_CTRL controller, and the DMA_CTRL initiates a DMA completion abort instruction to the CPU software, and the CPU software responds to the abort instruction before performing step 4).

2. The FPGA-based multi-channel DMA implementation method according to claim 1, characterized in that: The PS partitioning and managing the DDR memory means partitioning at least one BUFF in the DDR memory.

3. The FPGA-based multi-channel DMA implementation method according to claim 1 or 2, characterized in that: The control information includes memory address and division rule information.

4. The FPGA-based multi-channel DMA implementation method according to claim 1 or 2, characterized in that: PL schedules DMA through the configuration information of PS, and each DMA channel has a data cache FIFO.

5. The FPGA-based multi-channel DMA implementation method according to claim 1 or 2, characterized in that: When multiple channels apply for DMA transfer at the same time, DMA_CTRL will schedule DMA to transfer data of different channels in time-sharing mode, so that a single DMA can transfer data of multiple channels in time-sharing mode.

6. A multi-channel DMA data transmission method based on FPGA, the method executing at least one step of the multi-channel DMA implementation method based on FPGA according to any one of claims 1 to 5.

7. A computer device, comprising a memory, a processor, a communication interface and a communication bus; wherein: The memory, processor, and communication interface communicate with each other via the communication bus; the memory is used to store computer programs; the processor is used to execute the computer programs stored in the memory, and is characterized in that: when the processor executes the computer program, it implements at least one step of the FPGA-based multi-channel DMA implementation method described in any one of claims 1 to 5, or at least one step of the FPGA-based multi-channel DMA data transmission method described in claim 6.

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