Semiconductor structure and method of fabricating the same

Abstract

Disclosed are a semiconductor structure and a method of fabricating the same. The semiconductor structure includes a pad array. The pad array includes a plurality of pads, a pad boundary, a plurality of second branches, and at least one first surrounding pad. The pads are arranged in a plurality of rows. The pad boundary is disposed outside all of the pads and includes a plurality of first branches. The second branches are alternately arranged with the first branches. The at least one first surrounding pad is located between a first branch and a pad and between two adjacent second branches. A center of gravity of the at least one first surrounding pad is not in line with centers of gravity of pads arranged in the same row. Thus, by providing a surrounding pad with a center of gravity offset from the pad array, structural defects that can arise in semiconductor devices are improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure including a pad and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, since it can obtain a longer carrier channel length within the same semiconductor substrate, thereby reducing the leakage of the capacitor structure, it has gradually replaced DRAM cells with only a planar gate structure under the current mainstream development trend. Generally speaking, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage device to receive voltage signals from the bit line and word line. However, due to the limitations of process technology, existing DRAM cells with a recessed gate structure still have many defects, and further improvements are needed to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] One object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which improves structural defects of the semiconductor structure that may be derived from the continuous increase in storage cell density by providing peripheral pads with offset centers of gravity on at least one side of a pad array.

[0004] In order to achieve the above-mentioned object, one embodiment of the present invention provides a semiconductor structure, comprising a pad array. The pad array comprises a plurality of pads, a pad boundary, a plurality of second branches, and at least one first surrounding pad. The pads are spaced apart from each other along the first direction and the second direction, and are arranged in multiple rows in the first direction. The pad boundary is arranged outside all the pads, including a plurality of first branches extending in the first direction. The second branches extend in the first direction and are arranged alternately with the first branches in the third direction. At least one first surrounding pad is located between the first branch and the pad in the first direction, and between two adjacent second branches in the third direction, wherein the center of gravity of the at least one first surrounding pad is not on the same line as the center of gravity of the pads arranged in the same row in the first direction.

[0005] In order to achieve the above-mentioned object, another embodiment of the present invention provides a semiconductor structure, comprising a pad array. The pad array comprises a plurality of pads, a pad boundary, and a plurality of second branches. The pads are spaced apart from each other along a first direction and a second direction, and each of the pads has two parallel opposite sides in the first direction. The pad boundary is arranged outside all the pads, including a plurality of first branches extending in the first direction. The second branches extend in the first direction and are arranged alternately with the first branches in the third direction. At least one surrounding pad is located between the pad boundary and the pad, wherein the at least one surrounding pad has two parallel opposite sides, and the two opposite sides of the at least one surrounding pad are not parallel to the two opposite sides of any of the pads.

[0006] In order to achieve the above-mentioned object, another embodiment of the present invention provides another method for manufacturing a semiconductor structure, comprising the following steps. A chip is provided, and a plug array is formed on the chip, comprising a plurality of plugs. A plurality of first parallel patterns extending in a first direction are defined on the chip. A plurality of second parallel patterns extending in a first direction are defined on the chip, wherein the first direction is different from the first direction. The end of at least one of the second parallel patterns is corrected to define at least one corrected pattern, wherein the end of the at least one corrected pattern deviates from the first direction. A first patterning process is performed using the first parallel pattern, and a second patterning process is performed using the corrected pattern and the second parallel pattern, to form a pad array on the plug, comprising a plurality of pads and at least one surrounding pad, which respectively overlap the plug below.

[0007] Generally speaking, the semiconductor structure and its manufacturing method are to perform a correction step to adjust the tilt angle and / or line width of at least one pattern end before performing two self-aligned reverse patterning processes to ensure that the end of the corresponding mask pattern can overlap with the plug arranged below. This makes the center of gravity of the surrounding pads subsequently formed on at least one side of the pad array deviate from the center of gravity of the adjacent pads, or makes the side edges of the surrounding pads non-parallel to the side edges of the adjacent pads, thereby ensuring the overlap rate between the surrounding pads and the corresponding plugs, thereby improving the structural defects of the semiconductor structure that may be derived from the continuous increase in storage cell density. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of these embodiments and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for ease of illustration and drawing. The same symbols in different embodiments represent corresponding or similar features.

[0009] Figures 1 to 2FIG. 1 is a schematic diagram of a semiconductor structure according to a first embodiment of the present invention, wherein:

[0010] Figure 1 is a schematic top view of a semiconductor structure; and

[0011] Figure 2 for Figure 1 Schematic cross-section along the tangent line D-D'.

[0012] Figures 3 and 4 FIG. 1 is a schematic diagram of a semiconductor structure according to a second embodiment of the present invention, wherein:

[0013] Figure 3 is a schematic top view of a semiconductor structure; and

[0014] Figure 4 for Figure 3 Schematic cross-section along the tangent line D-D'.

[0015] Figures 5 to 10 FIG2 is a schematic diagram of a method for manufacturing a semiconductor structure according to a preferred embodiment of the present invention, wherein:

[0016] Figure 5 is a schematic flow chart of steps in a method for manufacturing a semiconductor structure;

[0017] Figure 6 is a schematic diagram after forming a parallel pattern;

[0018] Figure 7 This is a schematic diagram after correcting the parallel pattern;

[0019] Figure 8 is a schematic top view of forming a mask pattern according to a parallel pattern;

[0020] Figure 9 A schematic top view of forming a mask pattern according to a correction pattern; and

[0021] Figure 10 Another schematic diagram after correcting the parallel pattern.

[0022] The description of the accompanying drawings is as follows:

[0023] 10, 20 Semiconductor Structure

[0024] 100A storage area

[0025] 100B surrounding areas

[0026] 102 insulation layer

[0027] 104 Isolation Structure

[0028] 110 pad array

[0029] 111 pad

[0030] 111a Side

[0031] 113 pad boundary

[0032] 115 First surrounding pad, surrounding pad

[0033] 115a Side

[0034] 117 First Branch

[0035] 119 Second Branch

[0036] 121 First Edge

[0037] 123 Second Edge

[0038] 125 Second surrounding pad, surrounding pad

[0039] 125a Side

[0040] 130 character line

[0041] 131 dielectric layer

[0042] 133 Gate dielectric layer

[0043] 135 Gate

[0044] 137 cap layer

[0045] 140 plug array

[0046] 141, 143 plug

[0047] 200 chips

[0048] 202 mask layer

[0049] 204 First Parallel Pattern

[0050] 206 Second Parallel Pattern

[0051] 208, 210, 308, 310 Correction Patterns

[0052] 212 First Opening

[0053] 214 Silicon Hard Mask Bottom Anti-Reflective Coating

[0054] 216 second mask pattern

[0055] A, B, C center of gravity

[0056] D1 First direction

[0057] D2 Second direction

[0058] D3 third direction

[0059] D4 Fourth Direction

[0060] L1 first length

[0061] L2 Second length

[0062] L3, L4 extension length

[0063] L5 length

[0064] R1, R2, R3…Rn rows

[0065] S1 First Distance

[0066] S2 Second distance

[0067] S3 Third distance

[0068] S4 Fourth distance

[0069] S5 Fifth Distance

[0070] S6 Sixth Distance

[0071] S7 Seventh Distance

[0072] S8 Eighth Distance

[0073] S9 Ninth Distance

[0074] S10 Tenth distance

[0075] W1, W2 end line width

[0076] Angle θ1, θ2 DETAILED DESCRIPTION

[0077] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present invention.

[0078] Please refer to Figures 1 to 2 , which is a schematic diagram of a semiconductor structure 10 according to a first embodiment of the present invention. Figure 1As shown, semiconductor structure 10 includes a pad array 110, the details of which include a plurality of pads 111, a pad boundary 113, a first peripheral pad 115, a plurality of first branches 117, and a plurality of second branches 119. Pads 111 are spaced apart along a first direction D1 and a second direction D2 that are intersecting and non-perpendicular to each other, and are arranged in a plurality of rows R1, R2, ..., Rn in the first direction D1 to serve as storage node pads (SNpads) of a semiconductor device (not shown, such as a dynamic random access memory device). Pad boundary 113 is disposed outside all pads 111 and includes first branches 117 extending in the first direction D1. Second branches 119 also extend in the first direction D1 and are arranged alternately with first branches 117 in a third direction D3. It should be noted that at least one first peripheral pad 115 is located between a first branch 117 and a pad 111 in the first direction D1 and between two adjacent second branches 119 in the third direction D3. The centers of gravity A of the pads 111 arranged in the same row R1, R2, ..., Rn all fall on the same extension line parallel to the first direction D1, while the centers of gravity B of at least one first peripheral pad 115 arranged in the same row of pads 111 are not on the extension line. Figure 2 As shown, the centers of gravity A / B of the pads 111 and / or at least one first peripheral pad 115 can correspond to the centers of gravity of the plugs 141 disposed thereunder, respectively, thereby ensuring contact between the pads 111 and / or at least one first peripheral pad 115 and the corresponding plugs 141. Thus, by providing first peripheral pads 115 on one side of the pad array 110 with their centers of gravity offset from the center of gravity A of the pads 111 in an adjacent row, structural defects in the semiconductor structure 10 that may arise from the continued increase in memory cell density can be alleviated.

[0079] In detail, Figure 1As shown, the first branches 117 are arranged sequentially in the third direction D3, and a plurality of first peripheral pads 115 are disposed between each first branch 117 and the corresponding pad 111, such that each first peripheral pad 115 is located on one side of the pad array 110 and has a center of gravity B offset from the extension line. The center of gravity B of each first peripheral pad 115 is spaced a first distance S1 and a second distance S1 from two adjacent second branches 119 in the third direction D3, respectively. The first distance S1 is, for example, less than the second distance S2. Furthermore, the center of gravity B of each first peripheral pad 115 is spaced a third distance S3 and a fourth distance S4 from an adjacent pad 111 to a first branch 117 in the first direction D1, respectively. The third distance S3 is, for example, less than the fourth distance S4. On the other hand, the center of gravity A of each solder pad 111 has a fifth distance S5 and a sixth distance S6, respectively, from two adjacent solder pads 111 in the third direction D3. The difference between the fifth distance S5 and the sixth distance S6 is, for example, less than the difference between the first distance S1 and the second distance S2. Furthermore, the center of gravity A of each solder pad 111 has a seventh distance S7 and an eighth distance S8, respectively, from two adjacent solder pads 111 in the first direction D1. The difference between the seventh distance S7 and the eighth distance S8 is, for example, less than the difference between the third distance S3 and the fourth distance S4. In a preferred embodiment, the fifth distance S5 and the sixth distance S6 are identical, and / or the seventh distance S7 and the eighth distance S8 are preferably identical, i.e., the difference between the two is zero, but this is not limiting.

[0080] For example Figure 1 As shown, the pad boundary 113 includes two first edges 121 disposed in a third direction D3 and two second edges 123 disposed in a fourth direction D4 perpendicular to the third direction D3. In one embodiment, one end of each first edge 121 is directly connected to one end of each second edge 123, forming an overall rectangular frame structure that surrounds the pad 111 and the first peripheral pad 115, thereby protecting the pad 111 and the first peripheral pad 115. It should be readily understood by those skilled in the art that, in another embodiment, the pad boundary may optionally include additional edges and exhibit other suitable overall shapes to achieve even more optimized protection. Each first branch 117 is, for example, disposed on the first edge 121 and has a first length L1 in the first direction D1. Each second branch 119 is disposed near, but not in contact with, the first edge 121 and has a second length L2 in the first direction D1. The first length L1 is, for example, less than the second length L2, but is not limited thereto.

[0081] The pad array 110 also includes a plurality of second peripheral pads 125, which are arranged between the second edge 123 of the pad boundary 113 and the pad 111 in the third direction D3. It should be noted that the center of gravity C of each second peripheral pad 125 also deviates from the extension line where the center of gravity A of the adjacent row of pads 111 is located. Among them, the center of gravity C of each second peripheral pad 125 has a ninth distance S9 and a tenth distance S10 between the adjacent second edge 123 and the pad 111 in the third direction D3, respectively. The ninth distance S9 is, for example, smaller than the tenth distance S10, and the ninth distance S9 is not equal to the aforementioned first distance S1, but is not limited thereto. In this way, the center of gravity C of the second peripheral pad 125 can also correspond to the center of gravity of the plug 141 arranged below, as shown in FIG. Figure 2 As shown, the second peripheral pads 125 are arranged to ensure contact between the corresponding plugs 141. In one embodiment, the maximum extension length L3 of each second peripheral pad 125 is, for example, different from the maximum extension length L4 of each first peripheral pad 115. The maximum extension length L4 of the first peripheral pad 115 is preferably equal to the length L5 of each pad 111 in the first direction D1 or the second direction D2. It will be readily understood by those skilled in the art that the aforementioned first length L1, second length L2, maximum extension lengths L3, L4, and length L5 refer to the average length or maximum length of each component of the pad array 110 in the first direction D1 or the second direction D2, but are not limited thereto. The pad array 110 may include a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), preferably including tungsten, but not limited thereto.

[0082] like Figure 1 and Figure 2 As shown, the semiconductor structure 10 also includes a substrate 100 and a plurality of word lines 130 arranged in the substrate 100. The aforementioned pad array 110 is, for example, arranged on the substrate 100, and the substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but is not limited thereto. Moreover, the pads 111 of the pad array 110 are, in principle, arranged in a storage area (cell region) 100A with a relatively high component integration in the substrate 100, while the first branch 117, the second branch 119, etc. located around the pad array 110 are, in principle, located in a peripheral area (periphery region) 100B with a relatively low component integration in the substrate 100. In one embodiment, the peripheral area 100B is, for example, arranged on at least one side of the storage area 100A, preferably, since Figure 1From the top view shown, the peripheral region 100B is, for example, disposed around the outside of the memory region 100A, but not limited thereto. Each word line 130 is disposed in a spaced relationship within the substrate 100, and includes a dielectric layer 131, a gate dielectric layer 133, and a gate 135 stacked in sequence, as well as a cap layer 137 covering the gate 135. Figure 2 As shown, the surface of the cap layer 137 can be flush with the top surface of the substrate 100, so that each word line 130 serves as a buried word line (BWL) of the semiconductor device and is isolated from other components disposed on the substrate 100 by the insulating layer 102 disposed on the substrate 100. In one embodiment, the insulating layer 102 preferably has a composite layer structure, such as, but not limited to, an oxide-nitride-oxide (ONO) structure.

[0083] For example Figure 2 As shown, the semiconductor structure 10 further includes a plug array 140 also disposed on the substrate 100, including a plurality of plugs 141 and 143 disposed in the storage region 100A and the peripheral region 100B, respectively. Each plug 141 and 143 is alternately disposed with a plurality of isolation structures 104 in a first direction D1, so as to electrically isolate adjacent plugs 141 and 143 from each other via the isolation structures 104. In one embodiment, the plugs 141 and 143 include, for example, an epitaxial material such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), or a low-resistance metal material such as aluminum, titanium, copper, or tungsten, but are not limited thereto. In a direction perpendicular to the substrate 100, each plug 141 is disposed below the pad 111 or the first peripheral pad 115, respectively, and physically contacts the corresponding pad 111 or the first peripheral pad 115 above it. Thus, the top of plug 141 is electrically connected to pad 111 or first peripheral pad 115, while the bottom portion of plug 141 extends into substrate 100 and is electrically connected to a transistor element (not shown) disposed within substrate 100, thereby serving as a storage node contact (SNC) of the semiconductor device, further electrically connecting to a storage node (SN) subsequently disposed above pad array 110. Meanwhile, each plug 143 is disposed below first branch 117 or second branch 119 and physically contacts the corresponding first branch 117 or second branch 119 above. However, the bottom of plug 143 is located on insulating layer 102 and does not contact substrate 100, serving as a dummy plug for the semiconductor device.

[0084] According to the first embodiment of the present invention, the semiconductor structure 10 provides first peripheral pads 115 and / or second peripheral pads 125 around the periphery of the pad array 110, for example, on at least one side of the pad array 110, with their centers of gravity offset from the center of gravity A of the adjacent row of pads 111. This allows the centers of gravity B / C of the first peripheral pads 115 and / or second peripheral pads 125 adjacent to the pad boundary 113 to correspond to the centers of gravity of the underlying plugs 141, thereby ensuring contact between the first peripheral pads 115 and / or second peripheral pads 125 and the corresponding plugs 141. Accordingly, by providing the first peripheral pads 115 and / or second peripheral pads 125 with offset centers of gravity on at least one side of the pad array 110, structural defects that may arise in the semiconductor structure 10 due to the continuous increase in memory cell density can be improved. A person skilled in the art will readily appreciate that the semiconductor structure 10 of this embodiment can further include various components, such as transistor components, bit line components, and / or capacitor components, within the storage region 100A according to actual device requirements to form a dynamic random access memory device and achieve good device performance.

[0085] Please refer to Figures 3 and 4 , which is a schematic diagram of a semiconductor structure 20 according to a second embodiment of the present invention. The semiconductor structure 20 of this embodiment is substantially the same as the semiconductor structure 10 of the aforementioned embodiment, for example, both include a pad array 110, word lines 130, and a plug array 140. Pad array 110 also includes, in detail, a plurality of pads 111, pad boundaries 113, a plurality of first branches 117, and a plurality of second branches 119. The same details are not further described here.

[0086] like Figures 3 and 4 As shown, the main difference between the manufacturing method of the semiconductor structure 20 of this embodiment and the aforementioned first embodiment is that the pad array 110 further includes at least one peripheral pad 115 / 125, for example, located between the first edge 121 or the second edge 123 of the pad boundary 113 and the pad 111. The at least one peripheral pad 115 / 125 has two opposite side edges 115a / 125a parallel to each other, and each pad 111 has two opposite side edges 111a parallel to the first direction D1 or the second direction D2, and the two opposite side edges 115a / 125a of the at least one peripheral pad 115 / 125 are not parallel to the two opposite side edges 111a of any pad 111 in the second direction D2. Under this configuration, Figure 4As shown, at least one peripheral pad 115 / 125 can correspond to the plug 141 disposed thereunder, ensuring contact between the at least one peripheral pad 115 / 125 and the corresponding plug 141. Thus, by disposing at least one peripheral pad 115 / 125 around the pad array 110, for example, on at least one side of the pad array 110, with a side that is not parallel to the side 111a of the adjacent pad 111, structural defects that may arise in the semiconductor structure 10 due to the continuous increase in memory cell density can be improved.

[0087] In detail, Figure 3 As shown, the semiconductor structure 10 includes a plurality of peripheral pads 115 and / or a plurality of peripheral pads 125. The peripheral pads 115 are disposed between each first branch 117 and the corresponding pad 111. The two opposing sides 115a of each peripheral pad 115 are not parallel to the two opposing sides 111a of the corresponding pad 111 in the second direction D2, and the angle θ1 between the two opposing sides 115a of the peripheral pad 115 and the two opposing sides 111a of the pad 111 is not greater than 90 degrees, but is not limited thereto. Furthermore, the peripheral pads 125 are disposed between the second edge 123 and the corresponding pad 111 in the third direction D3. The two opposing sides 125a of each peripheral pad 125 are also non-parallel to the two opposing sides 111a of the corresponding pad 111 in the second direction D2. The included angle θ2 between the two opposing sides 125a of the peripheral pad 125 and the two opposing sides 111a of the pad 111 is no greater than 90 degrees. The included angle θ2 is preferably different from the included angle θ1, but is not limited thereto. In one embodiment, the peripheral pads 115 and the peripheral pads 125 each have different maximum extension lengths, for example. The maximum extension length L3 of the peripheral pad 125 is preferably greater than the maximum extension length L4 of the peripheral pad 115, or the length L5 of each pad 111 in the first direction D1 or the second direction D2. Furthermore, the maximum extension length L4 of the peripheral pad 115 is also preferably greater than the length L5 of the pad 111, but is not limited thereto.

[0088] According to the second embodiment of the semiconductor structure 20 of the present invention, peripheral pads 115 / 125 having side edges that are not parallel to the side edges 111a of the pads 111 and / or having a maximum extension length greater than the length L5 of the pads 111 are disposed around the pad array 110, for example, on at least one side of the pad array 110. This allows the peripheral pads 115 / 125 adjacent to the pad boundary 113 to be aligned with the underlying plugs 141, thereby ensuring contact between the peripheral pads 115 / 125 and the corresponding plugs 141. Accordingly, by disposing peripheral pads 115 / 125 on at least one side of the pad array 110, structural defects in the semiconductor structure 20 that may arise from the continuous increase in memory cell density are alleviated, thereby enabling the subsequently fabricated dynamic random access memory device to achieve good device performance.

[0089] In order to enable a person skilled in the art to easily understand the semiconductor structure 10 / 20 of the present invention, the manufacturing method of the semiconductor structure 10 / 20 of the present invention will be further described below.

[0090] Please refer to Figures 5 to 10 , which is a schematic diagram of a method for manufacturing a semiconductor structure 10 / 20 in a preferred embodiment of the present invention, wherein, Figure 5 1 is a schematic flow chart of the steps of a method for manufacturing a semiconductor structure 10 / 20. Figures 6 to 10 This is a schematic diagram of the manufacturing process of the semiconductor structure 10 / 20. First, please refer to Figure 5 and Figure 6 As shown, a chip 200 is provided, and a plug array 140 including a plurality of plugs 141 is formed on the chip 200 (step S1 ).

[0091] Next, a mask layer 202 is formed on the chip 200, covering the plug array 110, and parallel patterns are defined on the mask layer 202 (step S2), including a plurality of first parallel patterns 204 spaced apart from each other and arranged along the first direction D1, and a plurality of second parallel patterns 206 spaced apart from each other and arranged along the second direction D2. Each of the first parallel patterns 204 and each of the second parallel patterns 204 are, for example, strip-shaped, and the first parallel patterns 204 and the second parallel patterns 204 are interlaced with each other, as shown in FIG. Figure 6 shown.

[0092] like Figure 5 and Figure 7As shown, a correction step is performed to correct at least one parallel pattern (step S3) to define at least one corrected pattern 208 / 210. Specifically, the correction step, for example, adjusts the tilt angle of the end of at least one second parallel pattern 206 (step S31), such as by causing the end of at least one corrected pattern 208 / 210 to deviate from the second direction D2. The deviation angle θ1 / θ2 is, for example, less than 90 degrees, but not limited thereto. A person skilled in the art will readily appreciate that, in one embodiment, the correction step can be performed on the end of any one second parallel pattern 206, or can be performed simultaneously on the ends of all second parallel patterns 206, depending on actual manufacturing requirements. For example, before defining at least one correction pattern 208 / 210, a comparison step may be performed in advance. By comparing the overlap ratios between each second parallel pattern 206 and the plug 141 disposed thereunder, the second parallel pattern 206 to be corrected is selected. The correction step is then performed on the selected second parallel pattern 206, so that the overlap ratio between at least one correction pattern 208 / 210 and the plug 141 disposed thereunder is greater than the overlap ratio between the second parallel pattern 206 and the plug 141 disposed thereunder before correction. Alternatively, in another embodiment, the correction step may be performed on the ends of a portion of the second parallel patterns 206, so that the ends deviate from the second direction D2 and have a deviation angle θ1. At the same time, the correction step may be performed on the ends of another portion of the second parallel patterns 206, so that the ends deviate from the second direction D2 and have a deviation angle θ2, as shown in FIG. Figure 7 The deviation angle θ2 is preferably different from the deviation angle θ1, so that the overlap ratios of the modified patterns 208 and 210 with the plugs 141 disposed thereunder are both greater than the overlap ratios of the second parallel pattern 206 before modification with the plugs 141 disposed thereunder.

[0093] Then, if Figure 5 and Figures 8 and 9 As shown, a pad array is formed by parallel patterning (step S4) to form a Figure 1 or Figure 3 Specifically, the semiconductor structures 10 and 20 are shown. First, a first patterning process is performed on the first parallel pattern 204, such as a first self-aligned reverse patterning (SARP) process, and a plurality of first openings 212 in a rectangular shape are etched on the mask layer 202, as shown in FIG. Figure 8As shown. Next, a mask structure (not shown) is formed on the mask layer 202 to cover all the first openings 212. The mask structure, for example, has a composite structure including an organic bottom layer (not shown) stacked in sequence, a silicon hard mask bottom anti-reflective coating 214, and a second patterning process, such as a second self-aligned reverse patterning process, is performed through the second parallel pattern 204 and at least one correction pattern 208 / 210 to form a plurality of second mask patterns 216 in a rectangular frame shape, as shown. Figure 9 As shown. Then, a second etching process is performed using the second mask pattern 216 to sequentially transfer the rectangular frame pattern of the second mask pattern 216 to the underlying silicon hard mask bottom anti-reflective coating 214 and the organic bottom layer, and then to the mask layer 202 further below, so as to again etch a plurality of second rectangular frame-shaped openings (not shown) on the mask layer 202. Subsequently, at least one more etching process is performed to transfer the pattern on the mask layer 202 to the conductive material layer (not shown) on the chip 200, so as to form a conductive layer as shown in FIG. Figure 1 or Figure 3 The pad array 110 shown includes a plurality of pads 111 and at least one peripheral pad 115 / 125 , each of which overlaps with the underlying plug 141 .

[0094] This operation completes the fabrication of the semiconductor structure 10 / 20 according to the preferred embodiment of the present invention. According to the fabrication method of this embodiment, the pads 111 in the pad array 110 are fabricated by performing two self-aligned reverse patterning processes, and the peripheral pads 115 / 125 are fabricated by additionally performing the aforementioned correction step. Thus, by performing the aforementioned correction step, the degree of overlap between the end of the second mask pattern 216 and the underlying plug 141 is adjusted, such that the center of gravity of the formed peripheral pad 115 / 125 deviates from the center of gravity A of the adjacent pad 111, or the side edges of the peripheral pad 115 / 125 are not parallel to the side edges 111a of the adjacent pad 111, thereby ensuring the overlap ratio between the peripheral pad 115 / 125 and the corresponding plug 141. Accordingly, by forming the peripheral pad 115 / 125 on at least one side of the pad array 110, structural defects that may arise in the semiconductor structure 10 / 20 due to the continuous increase in memory cell density can be improved. A person skilled in the art should readily understand that the semiconductor structure 10 / 20 of this embodiment may further form various components, such as transistor components, bit line components, and / or capacitor components, within the storage region 100A according to actual device requirements, to subsequently form a dynamic random access memory device and achieve good device performance.

[0095] In addition, in order to meet the actual product requirements, the manufacturing method of the semiconductor device of the present invention may also have other aspects and is not limited to the above. Figure 10As shown, in another embodiment, the correction step may also selectively adjust the line width of the end of at least one second parallel pattern 206 to form at least one correction pattern 308 / 310 with a relatively large end line width W1 / W2, so that the overlap ratio of at least one correction pattern 308 / 310 and the plug 141 provided thereunder is greater than the overlap ratio of the second parallel pattern 206 before correction and the plug 141 provided thereunder. Similarly, the correction step of this embodiment may be performed on the end of any second parallel pattern 206 according to actual production requirements, or the correction step may be performed on the ends of all second parallel patterns 206 simultaneously, or the end line width of a portion of the second parallel patterns 206 may be selectively adjusted to have a relatively large end line width W1, while the end line width of another portion of the second parallel patterns 206 may be adjusted to have a relatively large end line width W2, as shown in FIG. Figure 10 As shown, but not limited to this. The end line width W2 is preferably different from the end line width W1, so that the overlap ratios of the correction patterns 308 and 310 with the underlying plugs 141 are both greater than the overlap ratios of the second parallel patterns 206 and the underlying plugs 141 before correction. In other embodiments, the tilt angle and end line width of at least one second parallel pattern 206 can be adjusted simultaneously during the correction step to further increase the overlap ratio between the correction pattern (not shown) and the underlying plugs 141 before correction. Thus, the peripheral pads produced by performing the aforementioned correction step can also form peripheral pads 115 / 125 whose center of gravity deviates from the center of gravity A of the adjacent pad 111 or whose side edges are not parallel to the side edges 111a of the adjacent pad 111, thereby ensuring the overlap ratios between the peripheral pads 115 / 125 and the corresponding plugs 141, thereby improving the structural defects that may arise in the semiconductor structure due to the continuous increase in memory cell density.

[0096] In general, the semiconductor structure and its fabrication method utilize a correction step to adjust the tilt angle and / or line width of at least one pattern end before performing two self-aligned reverse patterning processes to ensure that the end of the corresponding mask pattern is highly overlapped with the plug disposed thereunder. This causes the center of gravity of the peripheral pads subsequently formed around the pad array to deviate from the center of gravity of the adjacent pads, or to prevent the side edges of the peripheral pads from being parallel to the side edges of the adjacent pads. This ensures the overlap ratio between the peripheral pads and the corresponding plugs, thereby improving the structural defects of the semiconductor structure that may arise from the continuous increase in memory cell density. Through this operation, the fabrication method of the present invention can effectively avoid structural defects that may arise from the continuous increase in memory cell density in the peripheral pads around the pad array, thereby enabling the semiconductor structure of the present invention to have a more optimized structure and device reliability, and achieve excellent operating performance and efficiency.

[0097] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that include: A pad array, the pad array comprising: A plurality of pads are spaced apart from each other along a first direction and a second direction, and arranged in a plurality of rows in the first direction; a pad boundary, arranged outside all the pads, comprising a plurality of first branches extending in the first direction; a plurality of second branches extending in the first direction and arranged alternately with the first branches in a third direction; and At least one first peripheral pad is located between the first branch and the pad in the first direction, and between two adjacent second branches in the third direction, wherein the center of gravity of the at least one first peripheral pad is not on the same line as the center of gravity of the pads arranged in the same row in the first direction.

2. The semiconductor structure according to claim 1, wherein: in, A first distance and a second distance are respectively provided between the center of gravity of the at least one first peripheral pad and the two second branches in the third direction, and the first distance is smaller than the second distance.

3. The semiconductor structure according to claim 1, wherein: There are a third distance and a fourth distance between the center of gravity of the at least one first peripheral pad and one of the pads and one of the first branches in the first direction, respectively, and the third distance is smaller than the fourth distance.

4. The semiconductor structure according to claim 2, wherein: The center of gravity of each of the pads has a fifth distance and a sixth distance from two adjacent pads in the third direction, respectively, wherein a difference between the fifth distance and the sixth distance is smaller than a difference between the first distance and the second distance.

5. The semiconductor structure according to claim 3, wherein: The center of gravity of each pad has a seventh distance and an eighth distance from two adjacent pads in the first direction, respectively, wherein the difference between the seventh distance and the eighth distance is smaller than the difference between the third distance and the fourth distance.

6. The semiconductor structure according to claim 2, wherein: It also includes at least one second surrounding pad, which is located between the pad boundary and the pad in the third direction, the center of gravity of the at least one second surrounding pad has a ninth distance from the pad boundary in the third direction, and the center of gravity of the at least one second surrounding pad has a tenth distance from one of the pads in the third direction, and the ninth distance is less than the tenth distance.

7. The semiconductor structure according to claim 6, wherein: The at least one first peripheral pad and the at least one second peripheral pad have different extension lengths.

8. The semiconductor structure according to claim 6, wherein: The ninth distance is not equal to the first distance.

9. A semiconductor structure comprising: A pad array, the pad array comprising: A plurality of pads are spaced apart from each other along a first direction and a second direction, each pad having two parallel opposite sides in the second direction; a pad boundary, arranged outside all the pads, comprising a plurality of first branches extending in the first direction; a plurality of second branches extending in the first direction and arranged alternately with the first branches in a third direction; and At least one peripheral pad is located between the pad boundary and the pad, wherein the at least one peripheral pad has two parallel opposite sides, and the two opposite sides of the at least one peripheral pad are not parallel to the two opposite sides of any of the pads.

10. The semiconductor structure according to claim 9, wherein: An angle between one of the two opposite sides of the at least one peripheral pad and one of the two opposite sides of the pad is no greater than 90 degrees.

11. The semiconductor structure according to claim 9, wherein: The at least one peripheral pad includes a plurality of peripheral pads, and at least two of the peripheral pads have different maximum extension lengths.

12. The semiconductor structure according to claim 11, wherein: An included angle between one of the two opposite sides of at least two of the peripheral pads and one of the two opposite sides of the pad is not equal.

13. The semiconductor structure according to claim 9, wherein: The maximum extension length of the at least one peripheral pad is greater than the length of each of the pads in the first direction.

14. The semiconductor structure according to claim 9, wherein: The at least one peripheral pad is located between the first branch and the pad in the first direction, and is located between two adjacent second branches in the third direction.

15. A method for manufacturing a semiconductor structure, characterized in that include: Provide chips; forming a plug array on the chip, comprising a plurality of plugs; defining a plurality of first parallel patterns extending in a first direction on the chip; defining a plurality of second parallel patterns extending in a second direction on the chip, the first direction being different from the second direction; Correcting an end of at least one of the second parallel patterns to define at least one corrected pattern, wherein the end of the at least one corrected pattern deviates from the second direction; as well as A first patterning process is performed using the first parallel pattern, and a second patterning process is performed using the at least one correction pattern and the second parallel pattern to form a pad array on the plug, including multiple pads and at least one surrounding pad, which overlap the plug below.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein: Also includes: Before defining the at least one correction pattern, at least one second parallel pattern to be corrected is selected by comparing the overlap ratios of the second parallel patterns with the plug, wherein the overlap ratio of the end of the at least one correction pattern with the plug is greater than the overlap ratio of the end of the at least one second parallel pattern with the plug.

17. The method for manufacturing a semiconductor structure according to claim 16, wherein: Also includes: The end line width of at least one of the second parallel patterns is adjusted to define at least one correction pattern.

18. The method for manufacturing a semiconductor structure according to claim 16, wherein: The deviation angle of the at least one correction pattern relative to the second direction is less than 90 degrees.

19. The method for manufacturing a semiconductor structure according to claim 16, wherein: Also includes: The ends of the plurality of first parallel patterns are modified simultaneously to define a plurality of modified patterns, wherein at least two of the modified patterns have different deviation angles relative to the second direction.

20. The method for manufacturing a semiconductor structure according to claim 16, wherein: Also includes: The ends of the plurality of first parallel patterns are modified simultaneously to define a plurality of the modified patterns, wherein at least two of the modified patterns have different end line widths.

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