Three-dimensional gallium nitride-based PN diode and preparation method

Abstract

The present invention provides a three-dimensional gallium nitride-based PN diode and a method for preparing the same. The three-dimensional gallium nitride-based PN diode comprises: a three-dimensional substrate having a plurality of device regions spaced apart on its outer surface, a plurality of devices correspondingly arranged on each device region, and an interconnecting dielectric layer covering the device surface and the non-device region of the three-dimensional substrate; each device comprises a first dielectric layer arranged on the surface of the three-dimensional substrate, and an n-type dielectric layer arranged on the side of the first dielectric layer facing away from the three-dimensional substrate. ‑ ‑GaN layer, set on n ‑ The p-GaN layer has a cathode on the side facing away from the 3D substrate, and a p-GaN layer, and an anode on the p-GaN layer, also facing away from the 3D substrate. The interconnect dielectric layer is fixed with a number of interconnect metals, connecting the corresponding anodes between devices via the interconnect metals, and also connecting the corresponding cathodes between devices via the interconnect metals. The diodes of this invention have excellent heat dissipation from the 3D substrate, a high degree of diode integration, superior electrical performance, a wider range of application scenarios, and improved device performance and lifespan.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices, and in particular relates to a three-dimensional gallium nitride-based PN diode and a preparation method thereof. Background Art

[0002] The PN diode is one of the most basic semiconductor devices, consisting of a P-type semiconductor and an N-type semiconductor, forming a PN structure. This diode plays a vital role in electronics, used in various circuits such as rectification, switching, voltage regulation, and amplification. Its unique unidirectional conductivity makes it a commonly used rectifier in circuits, converting AC signals into DC. The PN diode has a long history of research and application. Its simple principle and high stability have made it widely used in various electronic devices and circuits, laying the foundation for the development of modern electronic technology.

[0003] However, traditional PN diode devices often cannot meet the requirements of modern applications for devices with higher performance and specific needs. At the same time, the heat dissipation problem of traditional PN diode devices has always plagued their development and affected their normal operation. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a three-dimensional gallium nitride-based PN diode, aiming to solve the problems of poor heat dissipation and low integration of traditional PN diode devices.

[0005] To solve the above technical problems, the present invention is implemented as follows. In a first aspect, the present invention provides a three-dimensional gallium nitride-based PN diode, comprising: a three-dimensional substrate having a plurality of device regions spaced apart on its outer surface, a plurality of devices corresponding to each of the device regions, and an interconnect dielectric layer covering the device surface and non-device regions of the three-dimensional substrate;

[0006] Each of the devices comprises a first dielectric layer disposed on the surface of the three-dimensional substrate, an n-type dielectric layer disposed on a side of the first dielectric layer facing away from the three-dimensional substrate, - -GaN layer, provided on the n - - a cathode on the GaN layer facing away from the three-dimensional substrate, a p-GaN layer, and an anode provided on the p-GaN layer facing away from the three-dimensional substrate;

[0007] The interconnect dielectric layer is fixed with a plurality of interconnect metals, and the corresponding anodes between the devices are connected through the interconnect metals, and the corresponding cathodes between the devices are also connected through the interconnect metals.

[0008] Furthermore, the interconnection dielectric layer has at least multiple layers, and the corresponding interconnection metal on each layer of the interconnection dielectric layer connects the anodes between the devices, or connects the cathodes between the devices.

[0009] Furthermore, the interconnection dielectric layer includes a second dielectric layer, which covers the device surface and the non-device area of ​​the three-dimensional substrate; the interconnection metal includes a first interconnection metal located on the second dielectric layer, and the corresponding cathodes between the devices are connected through the first interconnection metal.

[0010] Furthermore, the interconnect dielectric layer includes a third dielectric layer covering the second dielectric layer, and the interconnect dielectric layer also includes a second interconnect metal located on the third dielectric layer, and the corresponding anodes between the devices are connected via the second interconnect metal.

[0011] Furthermore, the thickness of the second dielectric layer and the third dielectric layer are both 1-5 μm.

[0012] Furthermore, the three-dimensional substrate is in the shape of a sphere, a polyhedron or a cylinder.

[0013] Furthermore, the n - The dopant of the GaN layer is Si, with a doping concentration of 1×10 16 cm -3 ~8×10 16 cm -3 ; said n - -The thickness of the GaN layer is 20~100μm.

[0014] Furthermore, the dopant of the p-GaN layer is Mg, and the doping concentration is 2×10 18 cm -3 ~ 4×10 18 cm -3 The thickness of the p-GaN layer is 0.2~1μm.

[0015] A second aspect of the present invention provides a method for preparing the diode as described above, comprising the steps of:

[0016] Preparing a three-dimensional substrate, wherein a plurality of device areas are arranged at intervals on an outer surface of the three-dimensional substrate;

[0017] A first dielectric layer is deposited on the surface of the three-dimensional substrate, and n is grown on the surface of the first dielectric layer. - -GaN layer;

[0018] Etching the first dielectric layer and the n-type dielectric layer in the non-device area of ​​the three-dimensional substrate - -GaN layer, exposing the surface of the non-device region of the three-dimensional substrate; - -Preparing a p-GaN layer on the side of the GaN layer facing away from the three-dimensional substrate;

[0019] The n -A cathode is formed on the p-GaN layer, and an anode is formed on the p-GaN layer;

[0020] In the n - -GaN layer, the p-GaN layer and the partially grown interconnect dielectric layer exposed on the three-dimensional substrate;

[0021] Openings are etched on the interconnect dielectric layer at positions corresponding to the cathodes and the anodes, and interconnect metal is grown on the interconnect dielectric layer and at the openings to interconnect the cathodes and anodes on different device regions.

[0022] Furthermore, in the n - -GaN layer, the p-GaN layer and the partially grown interconnect dielectric layer exposed on the three-dimensional substrate;

[0023] Etching openings on the interconnect dielectric layer at positions corresponding to the cathodes and the anodes, and growing interconnect metal on the interconnect dielectric layer and at the openings to interconnect the cathodes and anodes on different device regions, including:

[0024] In the n - -Growing a second dielectric layer on the GaN layer, the p-GaN layer, and the exposed portion of the three-dimensional substrate, etching openings in the second dielectric layer corresponding to the positions of the cathodes, and growing a first interconnection metal on the surface of the second dielectric layer and at the openings to interconnect the cathodes in different device regions;

[0025] A third dielectric layer is grown on the surface of the second dielectric layer, holes are etched on the third dielectric layer corresponding to the positions of the anodes, and a second interconnection metal is grown on the surface of the third dielectric layer and at the holes to interconnect the anodes on different device regions.

[0026] Compared with the prior art, the three-dimensional gallium nitride-based PN diode and its preparation method in the present invention have the following advantages:

[0027] First, the diode of the present invention differs from the flat substrate used in related art. It has a three-dimensional substrate. Multiple devices can be integrated on the three-dimensional outer surface of the substrate, and the electrodes of each device are interconnected. This highly integrated diode can output high current, has better electrical performance, and has a wider range of application scenarios.

[0028] Secondly, the three-dimensional substrate is conducive to better heat dissipation of the diode, improving the reliability of the device in high-temperature environments and improving the performance and life of the device;

[0029] Finally, the diodes in modern devices often require a large space to achieve the required electrical performance. However, diodes that integrate several devices on a three-dimensional substrate can maximize the use of the three-dimensional surface of the three-dimensional substrate, maximize power in the smallest volume, and get rid of the limitations of the substrate surface area and volume on the electrical performance of PN diodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 1 is a schematic partial structural cross-sectional view of a method for preparing a three-dimensional gallium nitride-based PN diode after each step is completed in one embodiment of the present invention;

[0031] Figure 2 is a partial cross-sectional view of a three-dimensional gallium nitride-based PN diode according to an embodiment of the present invention;

[0032] Figure 3 FIG. 1 is a partial cross-sectional view of a schematic partial structure of a three-dimensional gallium nitride-based PN diode after step 2 is completed in an embodiment of the present invention.

[0033] In the accompanying drawings, each reference numeral represents:

[0034] 1. 3D substrate; 1a. Device area; 1b. Non-device area; 2. First dielectric layer; 3. n - -GaN layer; 4, p-GaN layer; 5, cathode; 6, anode; 7, second dielectric layer; 8, first interconnect metal; 9, third dielectric layer; 10, second interconnect metal. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] Example:

[0037] See also Figure 2 In this embodiment, a three-dimensional gallium nitride-based PN diode includes: a three-dimensional substrate 1 having a plurality of device regions 1a spaced apart on its outer surface, a plurality of devices corresponding to each device region 1a, and an interconnect dielectric layer covering the device surface and the non-device region 1b of the three-dimensional substrate 1;

[0038] Each device includes a first dielectric layer 2 disposed on the surface of a three-dimensional substrate 1, and an n-type dielectric layer 2 disposed on a side of the first dielectric layer 2 facing away from the three-dimensional substrate 1. - -GaN layer 3, set on n - - a cathode 5 and a p-GaN layer 4 on the side of the GaN layer 3 facing away from the three-dimensional substrate 1, and an anode 6 provided on the side of the p-GaN layer 4 facing away from the three-dimensional substrate 1;

[0039] The interconnect dielectric layer is fixed with a number of interconnect metals, and the corresponding anodes 6 between the devices are connected through the interconnect metals, and the corresponding cathodes 5 between the devices are also connected through the interconnect metals.

[0040] The diode in this embodiment has the following advantages:

[0041] First, the diode in this embodiment differs from the flat substrate in related art. It has a three-dimensional substrate 1. Multiple devices can be integrated on the three-dimensional outer surface of the three-dimensional substrate 1, and the electrodes of each device are interconnected. This highly integrated diode can output large currents, has better electrical performance, and has a wider range of applications.

[0042] Secondly, the three-dimensional substrate 1 is conducive to better heat dissipation of the diode, improving the reliability of the device in a high-temperature environment, and improving the performance and life of the device;

[0043] Finally, the diodes in modern devices often require a larger space to achieve the required electrical performance. However, diodes that integrate several devices on a three-dimensional substrate 1 can maximize the use of the three-dimensional surface of the three-dimensional substrate 1, maximize power in the smallest volume, and get rid of the limitations of the substrate surface area and volume on the electrical performance of the PN diode.

[0044] When the diode in this embodiment is integrated into other circuits, holes can be opened at positions corresponding to the interconnecting metal to allow the cathode 5 and anode 6 of the diode to be led out, or holes can be opened at positions corresponding to the cathode 5 and anode 6 of the diode to allow the cathode 5 and anode 6 of the diode to be led out and connected to other circuits through gold wire bonding.

[0045] Preferably, the three-dimensional substrate 1 is made of a heat-dissipating material with high thermal conductivity and a low coefficient of thermal expansion, such as a diamond substrate, boron nitride, or silicon nitride substrate. It should be noted that the three-dimensional substrate 1 has a certain thickness in all three directions, preferably with equal thickness in all directions. Several devices are preferably evenly spaced and integrated on the entire surface of the three-dimensional substrate 1, resulting in a highly integrated, heat-dissipating three-dimensional gallium nitride PN diode.

[0046] The main function of the first dielectric layer 2 is to serve as a solid substrate 1 and n - -GaN layer 3 between the buffer layer, reducing the three-dimensional substrate 1 and n - To prevent the stress caused by lattice mismatch and different thermal expansion coefficients between the GaN layer 3, the first dielectric layer 2 is preferably made of materials such as AlN.

[0047] The interconnect dielectric layer is used to provide a platform for the interconnect metal to attach, and preferably uses materials such as AlN. The interconnect metal is achieved by plating a metal film on the surface of the interconnect dielectric layer and using photolithography to achieve interconnection between the cathodes 5 and anodes 6 of each device. The interconnect dielectric layer has holes corresponding to the cathodes 5 and anodes 6 of each device, and the holes are filled with interconnect metal, with a portion of the interconnect metal located in the holes of the interconnect dielectric layer. The interconnect dielectric layer can be a single layer or multiple layers. The devices can be interconnected by providing interconnect metal on the surfaces of interconnect dielectric layers at different levels, or by only one layer of interconnect dielectric layer. The basic requirement is that the interconnect metal between the interconnected anodes 6 and the interconnect metal between the interconnected cathodes 5 cannot cross or contact each other.

[0048] also, Figure 2 This is only a partial cross-sectional view of a diode in some embodiments of the present invention. In other embodiments, a plurality of devices may be arranged at intervals in a PN diode, and is not limited to the following. Figure 2 Only two devices are shown.

[0049] Furthermore, if Figure 2 As shown, the interconnection dielectric layer has at least multiple layers, and the corresponding interconnection metal on each layer connects the anode 6 between the devices, or the cathode 5 between the devices.

[0050] Specifically, the multiple dielectric layers can ensure that the cathode 5 , the anode 6 and the corresponding interconnecting metals between the devices do not cross in space.

[0051] It should be understood that the interconnecting metal on a single interconnecting dielectric layer can connect the cathodes 5 between all devices or the cathodes 5 between some devices. That is, the cathodes 5 between all devices can be connected via the interconnecting metal on multiple layers of interconnecting dielectric layers. The connection method of the anodes 6 between devices is similar to that of the anodes 6 and will not be described in detail here.

[0052] In addition, there is no specific covering order for the interconnection dielectric layer carrying the cathode 5 between the interconnected devices and the interconnection dielectric layer carrying the anode 6 between the interconnected devices.

[0053] Preferably, the cathodes 5 between all devices are connected through the interconnection metal on the single-layer interconnection dielectric layer, and the anodes 6 between all devices are also connected through the interconnection metal on the single-layer interconnection dielectric layer, which is conducive to the thinning of the diode and reduces the preparation cost.

[0054] Furthermore, if Figure 2 As shown, the interconnection dielectric layer includes a second dielectric layer 7, which covers the device surface and the non-device area 1b of the three-dimensional substrate 1; the interconnection metal includes a first interconnection metal 8 located on the second dielectric layer 7, and the corresponding cathodes 5 between each device are connected through the first interconnection metal 8.

[0055] Preferably, the height from the surface of the second dielectric layer 7 facing away from the cubic substrate to the outer surface of the cubic substrate is equal, and the surface of the second dielectric layer 7 is flattened.

[0056] Holes are formed in the second dielectric layer 7 in areas corresponding to the cathodes 5 on each device, exposing the cathodes 5. A portion of the first interconnecting metal 8 is located within the holes in the second dielectric layer 7, while the remaining portion is located on the surface of the second dielectric layer 7. The corresponding cathodes 5 of each device are connected via the first interconnecting metal 8, thereby achieving interconnection between the devices and obtaining a highly integrated three-dimensional gallium nitride-based PN diode.

[0057] The second dielectric layer 7 is preferably made of AlN material, which has excellent thermal conductivity and strong thermal stability. As one of the outermost layers of the three-dimensional gallium nitride-based PN diode, it is beneficial to the heat dissipation of the device.

[0058] Furthermore, if Figure 2 As shown, the interconnect dielectric layer includes a third dielectric layer 9 covering the second dielectric layer 7 , and the interconnect dielectric layer also includes a second interconnect metal 10 located on the third dielectric layer 9 . The corresponding anodes 6 between the devices are connected through the second interconnect metal 10 .

[0059] The surface of the third dielectric layer 9 is also to be planarized, and the thickness of the third dielectric layer 9 is preferably uniform.

[0060] Holes are opened in the third dielectric layer 9 in areas corresponding to the cathodes 5 on each device, exposing the anodes 6. A portion of the second metal interconnect 10 is located within the holes in the third dielectric layer 9, while the remaining portion is located on the surface of the third dielectric layer 9. The corresponding anodes 6 of each device are connected via the second metal interconnect 10, thereby interconnecting the anodes 6 of each device and achieving a highly integrated three-dimensional gallium nitride-based PN diode. The third dielectric layer 9 has a similar structure and function to the second dielectric layer 7. It also protects the first metal interconnect 8 on the second dielectric layer 7 and isolates the first metal interconnect 8 from the second metal interconnect 10.

[0061] Furthermore, if Figure 2 As shown, the thickness of the second dielectric layer 7 and the third dielectric layer 9 are both 1-5 μm.

[0062] The thickness of the second dielectric layer 7 and the third dielectric layer 9 is only 1-5 μm, the diode is small in size, and each device is light and thin.

[0063] Furthermore, the three-dimensional substrate 1 is in the shape of a sphere, a polyhedron or a cylinder.

[0064] Such a three-dimensional substrate 1 is conducive to better heat dissipation of the device, thereby ensuring that the overall life of the device is improved. Preferably, the three-dimensional substrate 1 can be a spherical substrate that is easy to prepare.

[0065] Furthermore, n - The dopant of the GaN layer 3 is Si, with a doping concentration of 1×10 16 cm -3 ~8×10 16 cm -3 ;n - The thickness of the GaN layer 3 is 20 to 100 μm.

[0066] Furthermore, the dopant of the p-GaN layer 4 is Mg, and the doping concentration is 2×10 18 cm -3 ~ 4×10 18 cm -3 , the thickness of the p-GaN layer 4 is 0.2~1μm.

[0067] Here is an example, Figures 1 and 2 As shown, a three-dimensional substrate 1 made of spherical diamond with a diameter of 60 μm and an outer surface roughness of less than 0.5 nm is selected, and a plurality of devices are arranged at intervals on the outer surface of the three-dimensional substrate 1 .

[0068] In each device, the first dielectric layer 2 covers the device region 1a on the surface of the three-dimensional substrate 1. The first dielectric layer 2 is an AlN dielectric layer with a thickness of 20 nm to 50 nm, preferably 30 nm. - -GaN layer 3 covers the surface of the first dielectric layer 2, n - The Si doping concentration of the GaN layer 3 is preferably 5×10 16 cm -3 , the thickness is preferably 40μm; the p-GaN layer 4 is n - Part of the surface of the p-GaN layer 3 is formed by Mg ion implantation, and the Mg doping concentration of the p-GaN layer 4 is preferably 3×10 18 cm -3 , the thickness is preferably 0.5 μm. - The cathode 5 on the p-GaN layer 3 is preferably Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm), the anode 6 on the p-GaN layer 4 is preferably Ni (10 nm) / Au (60 nm), the interconnect metal is selected from metal Au, the first dielectric layer 2 and the second dielectric layer 7 are AlN layers, and their thickness is 1~5 μm, preferably 2 μm in this embodiment.

[0069] Compared to planar substrates, spherical PN diodes optimize their shape, increasing their heat dissipation area, improving their reliability in high-temperature environments, and enhancing their performance and lifespan. They effectively utilize the three-dimensional outer surface area, increasing diode integration and improving high-power electrical performance. Furthermore, compared to polyhedral or cylindrical three-dimensional substrates 1, spherical diamond is easier to prepare and provides uniform heat dissipation, making this configuration a preferred solution.

[0070] It should be understood that the above is only one embodiment of the three-dimensional gallium nitride-based PN diode and is not intended to limit the present invention. Those skilled in the art can reasonably change the material and shape of the three-dimensional substrate 1, select a suitable n - The three-dimensional gallium nitride-based PN diode of the present invention is prepared by selecting the appropriate Si doping concentration and thickness of the p-GaN layer 3, selecting the appropriate Si doping concentration and thickness of the p-GaN layer 4, reasonably selecting the cathode 5 and anode 6 that can form an ohmic contact, selecting the appropriate interconnecting metal material and the material of the first dielectric layer 2, etc.

[0071] like Figure 1 As shown, in some embodiments of the present invention, the steps of the method for preparing a diode as described above are as follows:

[0072] Step 1: preparing a three-dimensional substrate 1, wherein a plurality of device regions 1a are arranged at intervals on the outer surface of the three-dimensional substrate 1;

[0073] Step 2: Deposit a first dielectric layer 2 on the surface of the three-dimensional substrate 1, and grow n - -GaN layer 3;

[0074] Step 3: Etching the first dielectric layer 2 and n in the non-device area 1b of the three-dimensional substrate 1 - -GaN layer 3, exposing the surface of the non-device region 1b of the three-dimensional substrate 1; - -Prepare a p-GaN layer 4 on the side of the GaN layer 3 facing away from the three-dimensional substrate 1;

[0075] Step 4: n - A cathode 5 is formed on the p-GaN layer 3, and an anode 6 is formed on the p-GaN layer 4;

[0076] Step 5: In n - An interconnect dielectric layer is grown on the exposed portions of the p-GaN layer 3, the p-GaN layer 4 and the three-dimensional substrate 1; holes are etched on the interconnect dielectric layer at positions corresponding to the cathode 5 and the anode 6, and interconnect metal is grown on the interconnect dielectric layer and at the openings to interconnect the cathodes 5 and the anodes 6 on different device regions 1a.

[0077] It should be understood that in n -An interconnect dielectric layer is grown on the exposed portion of the p-GaN layer 3, the p-GaN layer 4 and the three-dimensional substrate 1, and interconnect metal is photolithographically grown on the surface of the interconnect dielectric layer, but the interconnect metal between the cathodes 5 on each device area 1a and the interconnect metal between the anodes 6 on each device area 1a cannot cross.

[0078] You can also - Multiple interconnect dielectric layers are grown on the exposed portions of the -GaN layer 3, the p-GaN layer 4 and the three-dimensional substrate 1. Interconnect metals are photolithographically and grown on each interconnect dielectric layer. Each layer interconnects different electrodes of the diode.

[0079] like Figure 1 As shown, further, step 5 includes:

[0080] In n - A second dielectric layer 7 is grown on the GaN layer 3, the p-GaN layer 4, and the exposed portion of the three-dimensional substrate 1. A hole is etched in the second dielectric layer 7 corresponding to the position of the cathode 5. A first interconnection metal 8 is grown on the surface of the second dielectric layer 7 and in the hole to interconnect the cathodes 5 in different device regions 1a.

[0081] A third dielectric layer 9 is grown on the surface of the second dielectric layer 7, holes are etched on the third dielectric layer 9 at positions corresponding to the anodes 6, and a second interconnection metal 10 is grown on the surface of the third dielectric layer 9 and at the holes to interconnect the anodes 6 on different device regions 1a.

[0082] The technical solution of the present invention is further described below in conjunction with specific embodiments:

[0083] See also Figures 1 and 2 This embodiment provides a method for preparing a diode, comprising the steps of:

[0084] Step 1: preparing spherical diamonds by microwave plasma chemical vapor deposition, and performing three-dimensional dynamic friction polishing on the spherical diamonds to reduce the surface roughness of the spherical diamonds to less than 0.5 nm, thereby obtaining a three-dimensional substrate 1, wherein a plurality of device regions 1a are spaced apart on the outer surface of the three-dimensional substrate 1;

[0085] Step 2: Depositing a 20-50 nm thick AlN dielectric layer on the outer surface of the three-dimensional substrate 1 by magnetron sputtering or atomic layer deposition to obtain a first dielectric layer 2;

[0086] A 20-100 μm n-type layer is grown on the first dielectric layer 2 by hydride vapor phase epitaxy, molecular beam epitaxy or metal organic chemical vapor deposition. - -GaN layer 3, where n - -GaN layer 3 is doped with Si, with a doping concentration of 1×10 16 cm-3 ~8×10 16 cm -3 .

[0087] Specifically, if Figure 3 As shown, Figure 3 FIG. 1 is a partial cross-sectional view of a schematic partial structure of the three-dimensional gallium nitride-based PN diode after step 2 is completed in this embodiment.

[0088] Step 3: Etch the first dielectric layer 2 and n in the non-device area 1a of the three-dimensional substrate 1 by ICP etching. - -GaN layer;

[0089] The barrier layer is made by photolithography and magnesium ion implantation is performed on n - A p-GaN region with a thickness of 0.2 μm to 1 μm is formed on the -GaN layer 3 and then rapidly thermally annealed to obtain a p-GaN layer 4, wherein the magnesium ion doping concentration of the p-GaN layer 4 is 2×10 18 cm 3 ~ 4×10 18 cm 3 ;

[0090] Step 4: In n - -Partially on the surface of the GaN layer 3, a metal film of Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm) is deposited by photolithography using thermal evaporation, magnetron sputtering, or electron beam evaporation. After a desmearing process, a stacked cathode 5 is formed. This is then annealed at 650°C in an N2 environment to provide a better ohmic contact.

[0091] Photolithography is performed on a portion of the surface of the p-GaN layer 4, and metal Ni / Au (10 nm / 60 nm) is evaporated using an evaporation process, and the gold is then removed to form an anode 6;

[0092] Step 5: Use magnetron sputtering or pulsed laser deposition to deposit - -Grow AlN with a thickness of 1 to 5 μm on the surface of the p-GaN layer 3 and the p-GaN layer 4, and fill the exposed portion of the three-dimensional substrate 1 with AlN, and then planarize the surface covered with AlN to obtain a second dielectric layer 7;

[0093] Photolithography and ICP etching (SF6) are used to open a hole in the second dielectric layer 7 at a position corresponding to the cathode 5 to expose the pattern of the cathode 5;

[0094] Deposit the first interconnection metal 8Au on the second dielectric layer 7 and the cathode 5 pattern by photolithography, evaporation or magnetron sputtering, and interconnect the cathodes 5 on different device regions 1a after stripping.

[0095] A 1-5 μm thick AlN layer is grown on the second dielectric layer 7 by magnetron sputtering or pulsed laser deposition, and the surface of the AlN layer is flattened to obtain a third dielectric layer 9.

[0096] Photolithography and ICP etching (SF6) are used to open a hole in the third dielectric layer 9 at a position corresponding to the anode 6 to expose the pattern of the anode 6;

[0097] A second interconnection metal 10Au is grown on the third dielectric layer 9 and the openings by photolithography, evaporation or magnetron sputtering, and the cathodes 5 on different devices are interconnected after debonding.

[0098] Specifically, it can be understood that in each step, the first dielectric layer 2, the second dielectric layer 7, the third dielectric layer 9, the cathode 5, the anode 6 and the n - -GaN layer 3 and the like are not limited to the deposition methods in the above embodiments. Those skilled in the art can reasonably use chemical vapor deposition to grow the first dielectric layer 2, the second dielectric layer 7, the third dielectric layer 9, the cathode 5, the anode 6 and the n-GaN layer 3. - -GaN layer 3. p-GaN layer 4 can be doped by ion implantation or thermal diffusion. - -Prepared on the GaN layer 3.

[0099] It should be understood that the steps in the above embodiments are not limited to a specific order, and some steps can be interchanged. In addition, in the above multiple embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in one embodiment, please refer to the relevant description of other embodiments.

[0100] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A three-dimensional gallium nitride-based PN diode, characterized in that: include: A three-dimensional substrate having a plurality of device areas spaced apart on its outer surface, a plurality of devices correspondingly arranged on each of the device areas, and an interconnect dielectric layer covering the device surface and the non-device area of ​​the three-dimensional substrate; Each of the devices comprises a first dielectric layer disposed on the surface of the three-dimensional substrate, an n-type dielectric layer disposed on a side of the first dielectric layer facing away from the three-dimensional substrate, - -GaN layer, provided on the n - - a cathode on the GaN layer facing away from the three-dimensional substrate, a p-GaN layer, and an anode provided on the p-GaN layer facing away from the three-dimensional substrate; The interconnect dielectric layer is fixed with a plurality of interconnect metals, and the corresponding anodes between the devices are connected through the interconnect metals, and the corresponding cathodes between the devices are also connected through the interconnect metals; The interconnect dielectric layer has at least multiple layers, and the corresponding interconnect metal on each layer of the interconnect dielectric layer connects the anodes between the devices, or connects the cathodes between the devices; the cathodes between all devices are connected through the interconnect metal on a single layer of interconnect dielectric layer, and the anodes between all devices are also connected through the interconnect metal on a single layer of interconnect dielectric layer.

2. The diode according to claim 1, characterized in that The interconnect dielectric layer includes a second dielectric layer, which covers the device surface and the non-device area of ​​the three-dimensional substrate; the interconnect metal includes a first interconnect metal located on the second dielectric layer, and the corresponding cathodes between the devices are connected through the first interconnect metal.

3. The diode according to claim 2, characterized in that The interconnect dielectric layer includes a third dielectric layer covering the second dielectric layer. The interconnect dielectric layer also includes a second interconnect metal located on the third dielectric layer. The corresponding anodes between the devices are connected via the second interconnect metal.

4. The diode according to claim 3, characterized in that The thickness of the second dielectric layer and the third dielectric layer are both 1-5 μm.

5. The diode according to any one of claims 1 to 4, characterized in that The three-dimensional substrate is in the shape of a sphere, a polyhedron or a cylinder.

6. The diode according to any one of claims 1 to 4, characterized in that The n - The dopant of the GaN layer is Si, with a doping concentration of 1×10 16 cm -3 ~8×10 16 cm -3 ; said n - -The thickness of the GaN layer is 20~100μm.

7. The diode according to any one of claims 1 to 4, characterized in that The dopant of the p-GaN layer is Mg, and the doping concentration is 2×10 18 cm -3 ~ 4×10 18 cm -3 The thickness of the p-GaN layer is 0.2~1μm.

8. The method for preparing a diode according to any one of claims 1 to 7, wherein: Including steps: Preparing a three-dimensional substrate, wherein a plurality of device areas are arranged at intervals on an outer surface of the three-dimensional substrate; A first dielectric layer is deposited on the surface of the three-dimensional substrate, and n is grown on the surface of the first dielectric layer. - -GaN layer; Etching the first dielectric layer and the n-type dielectric layer in the non-device area of ​​the three-dimensional substrate - -GaN layer, exposing the surface of the non-device region of the three-dimensional substrate; - -Preparing a p-GaN layer on the side of the GaN layer facing away from the three-dimensional substrate; The n - A cathode is formed on the p-GaN layer, and an anode is formed on the p-GaN layer; In the n - -GaN layer, the p-GaN layer and the partially grown interconnect dielectric layer exposed on the three-dimensional substrate; Openings are etched on the interconnect dielectric layer at positions corresponding to the cathodes and the anodes, and interconnect metal is grown on the interconnect dielectric layer and at the openings to interconnect the cathodes and anodes on different device regions.

9. The method according to claim 8, characterized in that described in the n - -GaN layer, the p-GaN layer and the partially grown interconnect dielectric layer exposed on the three-dimensional substrate; Etching openings on the interconnect dielectric layer at positions corresponding to the cathodes and the anodes, and growing interconnect metal on the interconnect dielectric layer and at the openings to interconnect the cathodes and anodes on different device regions, including: In the n - -Growing a second dielectric layer on the GaN layer, the p-GaN layer, and the exposed portion of the three-dimensional substrate, etching openings in the second dielectric layer corresponding to the positions of the cathodes, and growing a first interconnection metal on the surface of the second dielectric layer and at the openings to interconnect the cathodes in different device regions; A third dielectric layer is grown on the surface of the second dielectric layer, holes are etched on the third dielectric layer corresponding to the positions of the anodes, and a second interconnection metal is grown on the surface of the third dielectric layer and at the holes to interconnect the anodes on different device regions.

Images