Silicon carbide MOSFET device and preparation method thereof
By introducing control gate and split gate structures into silicon carbide MOSFET devices, combined with the charge coupling effect, the problem of parasitic gate leakage capacitance in the device is solved, and the switching rate and stability are improved.
Patent Information
- Application Number
- CN202410379294.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2044-03-29
AI Technical Summary
Due to the presence of parasitic gate leakage capacitors, the loss of silicon carbide MOSFET devices increases during the on-off process, affecting their fast switching performance.
The control gate structure and the split gate structure are adopted. The split gate structure is arranged between the control gate structure and the drain region, and is connected to the source region through the split gate conductive layer, generating a charge coupling effect, reducing the gate leakage capacitance, and optimizing the internal electric field.
The Miller platform's existence time of silicon carbide MOSFET devices is effectively reduced, the switching rate is improved, the loss is reduced, and the working performance and stability are improved.
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Figure CN118263326B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a silicon carbide MOSFET device and a method for preparing the same. Background Art
[0002] A semiconductor is a material with conductivity between that of a good conductor and that of an insulator. Semiconductor devices are electronic devices that use the special electrical properties of semiconductor materials to perform specific functions. For example, silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices can be used to generate, receive, transform and amplify signals, as well as perform energy conversion.
[0003] In the related art, due to the structural characteristics of the silicon carbide MOSFET device itself, the silicon carbide MOSFET device must have parasitic capacitance, such as the parasitic gate-drain capacitance Cgd, which will lead to the generation of the Miller platform. The Miller platform will increase the loss of the silicon carbide MOSFET device during the turn-on and turn-off process, resulting in the silicon carbide MOSFET device being unable to switch quickly during operation, affecting the performance of the silicon carbide MOSFET device. Summary of the invention
[0004] Based on this, it is necessary to provide a silicon carbide MOSFET device and a preparation method thereof, aiming to reduce the gate-drain capacitance generated in the silicon carbide MOSFET device and improve the performance of the silicon carbide MOSFET device.
[0005] An embodiment of the first aspect of the present application provides a silicon carbide MOSFET device, the silicon carbide MOSFET device comprising a substrate, a first doped region, a gate trench, a control gate structure, a split gate structure, a body region, a source region and a drain region; the first doped region is arranged in the substrate; the gate trench is arranged in the first doped region, and opens from the front side of the substrate and extends along the thickness direction of the substrate, the gate trench comprises a first sub-trench and a second sub-trench, the second sub-trench is located on the side of the first sub-trench away from the front side of the substrate; the control gate structure is arranged in the first sub-trench, the control gate structure comprises a control gate conductive layer and a control gate dielectric layer, the control gate dielectric layer is located between the control gate conductive layer and the groove wall of the first sub-groove; a split gate structure is arranged in the second sub-groove, the split gate structure includes a split gate conductive layer and a split gate dielectric layer, the split gate dielectric layer covers the split gate conductive layer; the dielectric constant of the control gate dielectric layer is different from the dielectric constant of the split gate dielectric layer; the body region is arranged in the first doped region and is located on a side of the control gate dielectric layer away from the control gate conductive layer; the source region is arranged in the body region; the drain region is arranged in the substrate and is located on a side of the first doped region away from the front side of the substrate.
[0006] In the embodiment of the present application, the control gate structure and the split gate structure jointly form the gate of the silicon carbide MOSFET device. The split gate structure is arranged between the control gate structure and the drain region. The split gate structure can reduce the gate-drain (Cgd) capacitance between the control gate structure and the drain region, thereby reducing the existence time of the Miller platform in the silicon carbide MOSFET device, improving the switching rate of the silicon carbide MOSFET device, reducing the loss of the silicon carbide MOSFET device during the switching process, and improving the working performance and stability of the silicon carbide MOSFET device.
[0007] In the embodiment of the present application, the split gate conductive layer can be connected to the source region through the peripheral contact hole, so that the split gate conductive layer is also in a negative voltage environment, so that the split gate conductive layer and the epitaxial layer around the split gate dielectric layer produce a charge coupling effect under an external high voltage electric field, so that when the silicon carbide MOSFET device is reversely withstand voltage, the negative voltage in the source region will repel the negative charge in the epitaxial layer, so that the epitaxial layer around the split gate dielectric layer exhibits the properties of an intrinsic semiconductor, which can improve the withstand voltage performance of the silicon carbide MOSFET device, so that under the same withstand voltage conditions, the doping concentration of the epitaxial layer can be increased, the auxiliary depletion drift region can be enhanced, and the on-resistance of the silicon carbide MOSFET device can be reduced; and the connection between the split gate conductive layer and the source region can also improve the internal electric field of the silicon carbide MOSFET device, and further optimize the working performance of the silicon carbide MOSFET device.
[0008] In some embodiments, the dielectric constant of the control gate dielectric layer is greater than the dielectric constant of the split gate dielectric layer.
[0009] In some embodiments, the control gate dielectric layer covers the side walls of the first sub-trench; the split gate dielectric layer includes a first sub-portion, a second sub-portion and a third sub-portion, the first sub-portion covers the side walls of the second sub-trench, the second sub-portion covers the bottom wall of the second sub-trench, and the third sub-portion is located between the split gate conductive layer and the control gate conductive layer.
[0010] In some embodiments, the material of the control gate dielectric layer includes aluminum oxide, and the material of the split gate dielectric layer includes silicon oxide.
[0011] In some embodiments, a depth of the first sub-groove is less than a depth of the second sub-groove.
[0012] In some embodiments, along a direction from a center of the control gate conductive layer to a center of the source region, the control gate conductive layer has a first size, and the split gate conductive layer has a second size, and the first size is greater than the second size.
[0013] An embodiment of the second aspect of the present application provides a method for preparing a silicon carbide MOSFET device, the method comprising:
[0014] providing a substrate;
[0015] forming a first doped region in the substrate;
[0016] forming a body region in the first doped region, and forming a source region in the body region;
[0017] A gate trench is formed in the first doped region, the gate trench opens from the front side of the substrate and extends along the thickness direction of the substrate, the gate trench includes a first sub-trench and a second sub-trench, the second sub-trench is located on the side of the first sub-trench away from the front side of the substrate; a control gate structure is formed in the first sub-trench, and a split gate structure is formed in the second sub-trench, the control gate structure includes a control gate conductive layer and a control gate dielectric layer, the control gate dielectric layer is located between the control gate conductive layer and the trench wall of the first sub-trench; the split gate structure includes a split gate conductive layer and a split gate dielectric layer, the split gate dielectric layer covers the split gate conductive layer; the dielectric constant of the control gate dielectric layer is different from the dielectric constant of the split gate dielectric layer; the body region is located on the side of the control gate dielectric layer away from the control gate conductive layer;
[0018] A drain region is formed in the substrate, wherein the drain region is located on a side of the first doped region away from the front surface of the substrate.
[0019] In the embodiment of the present application, the control gate structure and the split gate structure jointly form the gate of the silicon carbide MOSFET device. The split gate structure is arranged between the control gate structure and the drain region. The split gate structure can reduce the gate-drain (Cgd) capacitance between the control gate structure and the drain region, thereby reducing the existence time of the Miller platform in the silicon carbide MOSFET device, improving the switching rate of the silicon carbide MOSFET device, reducing the loss of the silicon carbide MOSFET device during the switching process, and improving the working performance and stability of the silicon carbide MOSFET device.
[0020] In the embodiment of the present application, the split gate conductive layer can be connected to the source region through the peripheral contact hole, so that the split gate conductive layer is also in a negative voltage environment, so that the split gate conductive layer and the epitaxial layer around the split gate dielectric layer produce a charge coupling effect under an external high voltage electric field, so that when the silicon carbide MOSFET device is reversely withstand voltage, the negative voltage in the source region will repel the negative charge in the epitaxial layer, so that the epitaxial layer around the split gate dielectric layer exhibits the properties of an intrinsic semiconductor, which can improve the withstand voltage performance of the silicon carbide MOSFET device, so that under the same withstand voltage conditions, the doping concentration of the epitaxial layer can be increased, the auxiliary depletion drift region can be enhanced, and the on-resistance of the silicon carbide MOSFET device can be reduced; and the connection between the split gate conductive layer and the source region can also improve the internal electric field of the silicon carbide MOSFET device, and further optimize the working performance of the silicon carbide MOSFET device.
[0021] In some embodiments, the step of forming a body region in the first doped region and forming a source region in the body region includes:
[0022] forming a body doped region in the first doped region;
[0023] forming a source doping region in the body doping region;
[0024] A first sub-trench is formed in the first doping region, wherein the first sub-trench opens from the front surface of the substrate and penetrates the body doping region and the source doping region to form the body region and the source region.
[0025] In some embodiments, the step of forming a control gate structure in the first sub-trench and forming a split gate structure in the second sub-trench includes:
[0026] forming the control gate dielectric layer on the sidewall of the first sub-trench, and forming the second sub-trench on a side of the first sub-trench away from the front surface of the substrate;
[0027] forming the split gate dielectric layer and the split gate conductive layer in the second sub-trench;
[0028] The control gate conductive layer is formed in the first sub-trench.
[0029] In some embodiments, the step of forming the split gate dielectric layer and the split gate conductive layer in the second sub-trench includes:
[0030] forming a first sub-portion on a sidewall of the second sub-trench and forming a second sub-portion on a bottom wall of the second sub-trench;
[0031] forming the split-gate conductive layer in a groove formed by the first sub-portion and the second sub-portion;
[0032] A third sub-portion is formed on a side of the split gate conductive layer close to the front surface of the substrate, and the first sub-portion, the second sub-portion and the third sub-portion form the split gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 Schematic diagram of the structure of a silicon carbide MOSFET device in an embodiment of the present application;
[0034] Figure 2 This is a flow chart of a method for manufacturing a silicon carbide MOSFET device in an embodiment of the present application;
[0035] Figure 3-Figure 26 for Figure 2 Schematic diagram of the structure of a silicon carbide MOSFET device during the preparation method shown.
[0036] Reference numerals: silicon carbide MOSFET device-100, substrate-10, first doped region-1, gate trench-2, first sub-trench-21, second sub-trench-22, control gate structure-20, control gate conductive layer-3, control gate dielectric layer-4, split gate structure-30, split gate conductive layer-5, split gate dielectric layer-6, first sub-portion-61, second sub-portion-62, third sub-portion-63, body region-7, source region-8, body lead region-9, interlayer dielectric layer-11, connecting junction Structure-12, body doping region-701, source doping region-801, first etching window-101, first mask layer-102, first photoresist layer-103, second etching window-201, second mask layer-202, second photoresist layer-203, third etching window-301, third mask layer-302, third photoresist layer-303, control gate conductive material-300, control gate dielectric material-400, split gate conductive material-500, split gate dielectric material-600. DETAILED DESCRIPTION
[0037] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0039] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0040] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0041] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0042] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.
[0043] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.
[0044] A semiconductor is a material with conductivity between that of a good conductor and that of an insulator. Semiconductor devices are electronic devices that use the special electrical properties of semiconductor materials to perform specific functions. For example, silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices can be used to generate, receive, transform and amplify signals, as well as perform energy conversion.
[0045] In the related art, due to the structural characteristics of the silicon carbide MOSFET device itself, the silicon carbide MOSFET device must have parasitic capacitance, such as the parasitic gate-drain capacitance Cgd, which will lead to the generation of the Miller platform. The Miller platform will increase the loss of the silicon carbide MOSFET device during the turn-on and turn-off process, resulting in the silicon carbide MOSFET device being unable to switch quickly during operation, affecting the performance of the silicon carbide MOSFET device.
[0046] Based on the above problems, the present application provides a silicon carbide MOSFET device and a preparation method thereof, which can reduce the gate-drain capacitance generated in the silicon carbide MOSFET device and improve the performance of the silicon carbide MOSFET device.
[0047] The embodiment of the first aspect of the present application provides a silicon carbide MOSFET device 100, such as Figure 1 As shown, the silicon carbide MOSFET device 100 includes a substrate 10, a first doped region 1, a gate trench 2, a control gate structure 20, a split gate structure 30, a body region 7 and a source region 8; the first doped region 1 is arranged in the substrate 10; the gate trench 2 is arranged in the first doped region 1, and is opened from the front side of the substrate 10 and extends along the thickness direction of the substrate 10, the gate trench 2 includes a first sub-trench 21 and a second sub-trench 22, and the second sub-trench 22 is located on the side of the first sub-trench 21 away from the front side of the substrate 10; the control gate structure 20 is arranged in the first sub-trench 21, and the control gate structure 20 includes a control gate conductive layer 3 and a control gate conductive layer 4. A control gate dielectric layer 4 is provided, and the control gate dielectric layer 4 is located between the control gate conductive layer 3 and the groove wall of the first sub-groove 21; a split gate structure 30 is arranged in the second sub-groove 22, and the split gate structure 30 includes a split gate conductive layer 5 and a split gate dielectric layer 6, and the split gate dielectric layer 6 covers the split gate conductive layer 5; the dielectric constant of the control gate dielectric layer 4 is different from the dielectric constant of the split gate dielectric layer 6; the body region 7 is arranged in the first doped region 1 and is located on the side of the control gate dielectric layer 4 away from the control gate conductive layer 3; the source region 8 is arranged in the body region 7; the drain region is arranged in the substrate 10, and is located on the side of the first doped region 1 away from the front of the substrate 10.
[0048] In the embodiment of the present application, the substrate 10 can provide a support basis for other structural layers above it. Exemplarily, the substrate 10 may include a base and an epitaxial layer located above the base, and the first doped region 1 may be arranged in the epitaxial layer. The first doped region 1 has a certain thickness and a high doping concentration, which can reduce the on-resistance of the silicon carbide MOSFET device 100. The substrate 10 may be a SiC substrate, and the epitaxial layer is a SiC epitaxial layer. Optionally, the material of the substrate 10 may also be a semiconductor material such as single crystal Si, single crystal Ge, single crystal GeSi, GaN, etc., and the epitaxial layer material may be an epitaxial semiconductor layer of other materials, such as a Si epitaxial layer, a Ge epitaxial layer, a GeSi epitaxial layer, a GaN epitaxial layer, etc. Preferably, the material of the substrate 10 and the epitaxial layer is the same, which is conducive to forming a high-quality epitaxial layer, reducing defects in the epitaxial layer, and improving the performance of the subsequently formed trench transistor.
[0049] In the embodiment of the present application, the control gate structure 20 and the split gate structure 30 jointly form the gate of the silicon carbide MOSFET device 100. The split gate structure 30 is arranged between the control gate structure 20 and the drain region. The split gate structure 30 can reduce the gate-drain (Cgd) capacitance between the control gate structure 20 and the drain region, thereby reducing the existence time of the Miller platform in the silicon carbide MOSFET device 100, improving the switching rate of the silicon carbide MOSFET device 100, reducing the loss of the silicon carbide MOSFET device 100 during the switching process, and improving the working performance and stability of the silicon carbide MOSFET device 100.
[0050] In the embodiment of the present application, the split gate conductive layer 5 can be connected to the source region 8 through the peripheral contact hole, so that the split gate conductive layer 5 is also in a negative voltage environment, so that the split gate conductive layer 5 and the epitaxial layer around the split gate dielectric layer 6 produce a charge coupling effect under an external high voltage electric field, so that when the silicon carbide MOSFET device 100 is reversely withstand voltage, the negative voltage of the source region 8 will repel the negative charge in the epitaxial layer, so that the epitaxial layer around the split gate dielectric layer 6 exhibits the properties of an intrinsic semiconductor, which can improve the withstand voltage performance of the silicon carbide MOSFET device 100, so that under the same withstand voltage conditions, the doping concentration of the epitaxial layer can be increased, the auxiliary depletion drift region can be enhanced, and the on-resistance of the silicon carbide MOSFET device 100 can be reduced; and the split gate conductive layer 5 is connected to the source region 8, which can also improve the internal electric field of the silicon carbide MOSFET device 100 and further optimize the working performance of the silicon carbide MOSFET device 100.
[0051] In some embodiments, the dielectric constant of the control gate dielectric layer 4 is different from the dielectric constant of the split gate dielectric layer 6, and the material of the control gate dielectric layer 4 is different from the material of the split gate dielectric layer 6. This can also reduce the impact on the control gate dielectric layer 4 during the subsequent etching of the split gate dielectric layer 6, thereby ensuring the performance of the silicon carbide MOSFET device 100.
[0052] In some embodiments, the dielectric constant of the control gate dielectric layer 4 is greater than the dielectric constant of the split gate dielectric layer 6 .
[0053] In some embodiments, along the direction from the center of the control gate conductive layer 3 to the center of the source region 8, the thickness of the control gate dielectric layer 4 is less than the thickness of the split gate dielectric layer 6. The smaller the thickness of the control gate dielectric layer 4, the lower the channel resistance of the silicon carbide MOSFET device 100, the lower the on-resistance, and the better the electrical performance of the device; the larger the thickness of the split gate dielectric layer 6, the better the withstand voltage performance of the silicon carbide MOSFET device 100, and the electrical isolation between the gate and the substrate 10 can be ensured under high operating voltage conditions, thereby improving the reliability of the silicon carbide MOSFET device 100. Optionally, the thickness of the split gate dielectric layer 6 can be set according to the electric field strength of the working scene of the silicon carbide MOSFET device 100 finally formed to meet the reliability requirements.
[0054] In some embodiments, Figure 1 As shown, the control gate dielectric layer 4 covers the sidewalls of the first sub-trench 21; the split gate dielectric layer 6 includes a first sub-portion 61, a second sub-portion 62 and a third sub-portion 63, the first sub-portion 61 covers the sidewalls of the second sub-trench 22, the second sub-portion 62 covers the bottom wall of the second sub-trench 22, and the third sub-portion 63 is located between the split gate conductive layer 5 and the control gate conductive layer 3, and the control gate conductive layer 3 and the split gate conductive layer 5 are separated by the split gate dielectric layer 6. The control gate dielectric layer 4 and the split gate dielectric layer 6 can effectively isolate the charges between the control gate conductive layer 3 and the split gate conductive layer 5 and the substrate 10, thereby improving the working performance and stability of the silicon carbide MOSFET device 100.
[0055] In some embodiments, the material of the control gate dielectric layer 4 includes aluminum oxide, and the material of the split gate dielectric layer 6 includes silicon oxide. The material of the control gate dielectric layer 4 may be a high-K dielectric material, and the material of the control gate dielectric layer 4 may also include at least one of hafnium oxide, zirconium oxide, and lanthanum oxide, and the control gate dielectric layer 4 may be a single-layer or multi-layer structure. The split gate dielectric layer 6 is formed by a deposition process, and the material of the split gate dielectric layer 6 is an insulating dielectric material with electrical isolation performance, and the material of the split gate dielectric layer 6 may also include any one of silicon oxynitride, hafnium oxide, and lanthanum oxide, and the split gate dielectric layer 6 may be a single-layer structure or a multi-layer structure. Since the film forming efficiency of the deposition process is high, the rate of forming the split gate dielectric layer 6 can be increased.
[0056] In some embodiments, Figure 1As shown, along the thickness direction of the substrate 10, the depth of the first sub-groove 21 is less than the depth of the second sub-groove 22, which can reduce the length of the gate groove 2 along the length or width direction of the substrate 10, thereby reducing the resistance of the gate groove 2 and improving the working performance of the silicon carbide MOSFET device 100. And the depth of the second sub-groove 22 is greater than the depth of the first sub-groove 21, which is also conducive to giving full play to the charge coupling effect between the split gate structure 30 and the epitaxial layer, further improving the withstand voltage performance of the silicon carbide MOSFET device 100, and improving the working performance of the silicon carbide MOSFET device 100. The depth of the first sub-groove 21 can be set according to the requirements of the device to be formed. Specifically, the extension depth of the control gate conductive layer 3 can be greater than the extension depth of the body region 7, and the extension depth of the split gate conductive layer 5 can be less than the extension depth of the first doping region 1. The top view of the first sub-groove 21 can be a long strip, or a rectangle, a circle or other shapes.
[0057] In some embodiments, Figure 1 As shown, along the direction from the center of the control gate conductive layer 3 to the center of the source region 8, the control gate conductive layer 3 has a first size, and the split gate conductive layer 5 has a second size, and the first size is larger than the second size. Figure 1 As an example, the direction from the center of the control gate conductive layer 3 to the center of the source region 8 refers to Figure 1 In the horizontal direction, the first size refers to the width of the control gate conductive layer 3 in the horizontal direction, and the second size refers to the width of the split gate conductive layer 5 in the horizontal direction.
[0058] In some embodiments, Figure 1 As shown, the silicon carbide MOSFET device 100 further includes a body lead-out region 9, an interlayer dielectric layer 11 and a connection structure 12. The body lead-out region 9 is arranged in the body region 7 and is located on the side of the source region 8 away from the control gate conductive layer 3. The interlayer dielectric layer 11 is arranged on the upper surface of the first doped region 1. Furthermore, a conductive contact hole with a bottom connected to the body region 7 is also arranged above the interlayer dielectric layer 11, and the conductive contact hole can be filled with a conductive medium such as tungsten. The connection structure 12 is arranged on the upper surface of the interlayer dielectric layer 11, and the material of the connection structure 12 includes metal, and the connection structure 12 is in contact with the top of the conductive medium in the conductive contact hole.
[0059] The second aspect of the present application provides a method for preparing a silicon carbide MOSFET device 100, such as Figure 2 As shown, the preparation method comprises:
[0060] S101, providing a substrate;
[0061] S102, forming a first doped region in the substrate;
[0062] S103, forming a body region in the first doping region, and forming a source region in the body region;
[0063] S104, forming a gate trench in the first doping region, the gate trench opening from the front side of the substrate and extending along the thickness direction of the substrate, the gate trench including a first sub-trench and a second sub-trench, the second sub-trench being located on the side of the first sub-trench away from the front side of the substrate; forming a control gate structure in the first sub-trench, and forming a split gate structure in the second sub-trench; the control gate structure including a control gate conductive layer and a control gate dielectric layer, the control gate dielectric layer being located between the control gate conductive layer and the trench wall of the first sub-trench; the split gate structure including a split gate conductive layer and a split gate dielectric layer, the split gate dielectric layer covering the split gate conductive layer; the dielectric constant of the control gate dielectric layer is different from the dielectric constant of the split gate dielectric layer; the body region is located on the side of the control gate dielectric layer away from the control gate conductive layer;
[0064] S105, forming a drain region in the substrate, wherein the drain region is located on a side of the first doped region away from the front surface of the substrate.
[0065] In the embodiment of the present application, the control gate structure 20 and the split gate structure 30 jointly form the gate of the silicon carbide MOSFET device 100. The split gate structure 30 is arranged between the control gate structure 20 and the drain region. The split gate structure 30 can reduce the gate-drain (Cgd) capacitance between the control gate structure 20 and the drain region, thereby reducing the existence time of the Miller platform in the silicon carbide MOSFET device 100, improving the switching rate of the silicon carbide MOSFET device 100, reducing the loss of the silicon carbide MOSFET device 100 during the switching process, and improving the working performance and stability of the silicon carbide MOSFET device 100.
[0066] In the embodiment of the present application, the split gate conductive layer 5 can be connected to the source region 8 through the peripheral contact hole, so that the split gate conductive layer 5 is also in a negative voltage environment, so that the split gate conductive layer 5 and the epitaxial layer around the split gate dielectric layer 6 produce a charge coupling effect under an external high voltage electric field, so that when the silicon carbide MOSFET device 100 is reversely withstand voltage, the negative voltage of the source region 8 will repel the negative charge in the epitaxial layer, so that the epitaxial layer around the split gate dielectric layer 6 exhibits the properties of an intrinsic semiconductor, which can improve the withstand voltage performance of the silicon carbide MOSFET device 100, so that under the same withstand voltage conditions, the doping concentration of the epitaxial layer can be increased, the auxiliary depletion drift region can be enhanced, and the on-resistance of the silicon carbide MOSFET device 100 can be reduced; and the split gate conductive layer 5 is connected to the source region 8, which can also improve the internal electric field of the silicon carbide MOSFET device 100 and further optimize the working performance of the silicon carbide MOSFET device 100.
[0067] In the embodiment of the present application, the control gate dielectric layer 4 and the split gate dielectric layer 6 are formed separately, so that the thickness of the two can be adjusted separately to form a control gate dielectric layer 4 and a split gate dielectric layer 6 that meet the requirements, so that the thickness and material selection of the two are more flexible, while meeting the requirements that the silicon carbide MOSFET device 100 has low channel on-resistance and high voltage resistance.
[0068] In the embodiment of the present application, the preparation method further comprises:
[0069] S106 , forming an interlayer dielectric layer 11 and a connection structure 12 on the substrate 10 in sequence by deposition and etching processes.
[0070] In some embodiments, S103, forming a body region 7 in the first doping region 1 and forming a source region 8 in the body region 7, further specifically includes the following steps:
[0071] S1031, forming a body doping region 701 in the first doping region 1. Specifically, Figure 4 As shown, an ion implantation process may be used to form a body doping region 701 in the first doping region 1 .
[0072] S1032, forming a source doping region 801 in the body doping region 701. Specifically, Figure 7 As shown, an ion implantation process may be used to form a source doping region 801 in the body doping region 701 .
[0073] S1034 , forming a first sub-trench 21 in the first doping region 1 , the first sub-trench 21 opens from the front surface of the substrate 10 and penetrates the body doping region 701 and the source doping region 801 , and forms the body region 7 and the source region 8 .
[0074] In one embodiment, if Figures 5 to 8 As shown, S1032 may include the following steps:
[0075] S10321 , forming a first mask layer 102 and a first photoresist layer 103 in sequence on the body doping region 701 .
[0076] S10322 , forming a first etching window 101 on the first mask layer 102 .
[0077] S10323, etching the body doping region 701 based on the first etching window 101 to form a groove, removing the first photoresist layer 103 and then forming a source doping region 801 in the groove by ion implantation or the like.
[0078] S10324, remove the first mask layer 102.
[0079] In the embodiment of the present application, the silicon carbide MOSFET device 100 further includes a body lead-out region 9, which is disposed in the body region 7 and located on a side of the source region 8 away from the control gate conductive layer 3. In one embodiment, S103 further includes:
[0080] S1033 , forming a body lead-out region 9 in the body doping region 701 .
[0081] In a specific embodiment, Figures 9 to 12 As shown, S1033 specifically includes the following steps:
[0082] S10331 , forming a second mask layer 202 and a second photoresist layer 203 in sequence on the body doping region 701 .
[0083] S10332 , forming a second etching window 201 on the second mask layer 202 .
[0084] S10333, etching the body doping region 701 based on the second etching window 201 to form a groove, removing the second photoresist layer 203 and then forming a body lead-out region 9 in the groove by ion implantation or the like.
[0085] S10334, then remove the second mask layer 202.
[0086] In a specific embodiment, Figures 13 to 15 As shown, S1034 specifically includes the following steps:
[0087] S10341 , forming a third mask layer 302 on the first doping region 1 .
[0088] S10342 , forming a third photoresist layer 303 on the third mask layer 302 , and forming a third etching window 301 on the third mask layer 302 .
[0089] S10343, based on the third etching window 301, the first doped region 1 is etched to form a first sub-groove 21, the first sub-groove 21 is opened from the front side of the substrate 10 and passes through the body doped region 701 and the source doped region 801, and forms the body region 7 and the source region 8, and then the third photoresist layer 303 is removed.
[0090] The materials of the first mask layer 102, the second mask layer 202 and the third mask layer 302 may include commonly used mask materials such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, etc. The first mask layer 102, the second mask layer 202 and the third mask layer 302 may be a single layer or a multi-layer composite structure. Preferably, the first mask layer 102, the second mask layer 202 and the third mask layer 302 may be made of a hard mask material to maintain a good morphology in the subsequent etching process, so as to accurately transfer the pattern of the etching window to the epitaxial layer, and to play a good protective role on the area outside the gate trench 2 in the subsequent etching process.
[0091] In some embodiments, in S104, a control gate structure 20 is formed in the first sub-trench 21, and a split gate structure 30 is formed in the second sub-trench 22, which further specifically includes the following steps:
[0092] S1041 , forming a control gate dielectric layer 4 on the sidewall of the first sub-trench 21 , and forming a second sub-trench 22 on a side of the first sub-trench 21 away from the front surface of the substrate 10 .
[0093] S1042 , forming a split gate dielectric layer 6 and a split gate conductive layer 5 in the second sub-trench 22 .
[0094] S1043 , forming a control gate conductive layer 3 in the first sub-trench 21 .
[0095] In a specific embodiment, Figures 16 to 18 As shown, S1041 specifically includes the following steps:
[0096] S10411 , depositing a control gate dielectric material 400 , such as aluminum oxide, on the surface of the first doping region 1 .
[0097] S10412, remove the control gate dielectric material 400 above the third mask layer 302 and on the bottom wall of the first sub-trench 21, and form a control gate dielectric layer 4 on the sidewall of the first sub-trench 21; and continue to etch the first doped region 1 based on the third etching opening to form a second sub-trench 22.
[0098] S10413 , removing the third mask layer 302 and the control gate dielectric material 400 abutting against the third mask layer 302 .
[0099] In some embodiments, S1042 specifically includes the following steps:
[0100] S10421, forming a first sub-portion 61 on the sidewall of the second sub-trench 22, and forming a second sub-portion 62 on the bottom wall of the second sub-trench 22;
[0101] S10422, forming a split gate conductive layer 5 in the groove formed by the first sub-portion 61 and the second sub-portion 62;
[0102] S10423 , forming a third sub-portion 63 on a side of the split gate conductive layer 5 close to the front surface of the substrate, and the first sub-portion 61 , the second sub-portion 62 and the third sub-portion 63 form a split gate dielectric layer 6 .
[0103] In a specific embodiment, Fig.19 and Fig. 20 As shown, S10421 specifically includes the following steps:
[0104] S104211, depositing a split-gate dielectric material 600, such as silicon oxide, on the surface of the first doping region 1.
[0105] S104212 , removing the split gate dielectric material 600 on the upper surface of the first doped region 1 and in the first sub-trench 21 , and forming a first sub-portion 61 and a second sub-portion 62 in the second sub-trench 22 .
[0106] In a specific embodiment, Fig.21 and Fig.23 As shown, S10422 specifically includes the following steps:
[0107] S104221 , depositing a split gate conductive material 500 on the first doping region 1 , and filling the gate trench 2 with the split gate conductive material 500 .
[0108] S104222, removing the split gate conductive material 500 on the upper surface of the first doping region 1.
[0109] S104223 , etching back the split gate conductive material 500 in the gate trench 2 , removing the split gate conductive material 500 in the first sub-trench 21 , and forming a split gate conductive layer 5 in the second sub-trench 22 .
[0110] In a specific embodiment, Fig.24 As shown, S10423 specifically includes the following steps:
[0111] S104231 , depositing the split gate dielectric material 600 again on the first doping region 1 , and performing high temperature thermal oxidation on the split gate dielectric material 600 in the second sub-trench 22 to form an intermediate oxide, and forming a third sub-portion 63 of the split gate dielectric layer 6 above the split gate conductive layer 5 .
[0112] In a specific embodiment, Figure 25 to Figure 26 As shown, S1043 specifically includes the following steps:
[0113] S10431 , depositing a control gate conductive material 300 on the first doping region 1 to fill the first sub-trench 21 .
[0114] S10432, using a CMP process to remove the control gate conductive material 300 and the split gate dielectric material 600 on the surface of the first doping region 1.
[0115] In the present application embodiment, Figure 1 As shown, the split gate dielectric layer 6 includes a first sub-portion 61 , a second sub-portion 62 and a third sub-portion 63 , and the control gate conductive layer 3 and the split gate conductive layer 5 are separated by the third sub-portion 63 .
[0116] It should be understood that, in the embodiments of the present application, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.
[0117] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0118] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0119] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A method for preparing a silicon carbide MOSFET device, characterized in that: The preparation method comprises: providing a substrate; forming a first doped region in the substrate; forming a body region in the first doped region, and forming a source region in the body region; A gate trench is formed in the first doped region, the gate trench opens from the front side of the substrate and extends along the thickness direction of the substrate, the gate trench includes a first sub-trench and a second sub-trench, the second sub-trench is located on the side of the first sub-trench away from the front side of the substrate; a control gate structure is formed in the first sub-trench, and a split gate structure is formed in the second sub-trench, the control gate structure includes a control gate conductive layer and a control gate dielectric layer, the control gate dielectric layer is located between the control gate conductive layer and the trench wall of the first sub-trench; the split gate structure includes a split gate conductive layer and a split gate dielectric layer, the split gate dielectric layer covers the split gate conductive layer; the dielectric constant of the control gate dielectric layer is different from the dielectric constant of the split gate dielectric layer; the body region is located on the side of the control gate dielectric layer away from the control gate conductive layer; forming a drain region in the substrate, wherein the drain region is located on a side of the first doped region away from the front surface of the substrate; The step of forming a control gate structure in the first sub-trench and forming a split gate structure in the second sub-trench comprises: forming the control gate dielectric layer on the sidewall of the first sub-trench, and forming the second sub-trench on a side of the first sub-trench away from the front surface of the substrate; forming the split gate dielectric layer and the split gate conductive layer in the second sub-trench; The control gate conductive layer is formed in the first sub-trench.
2. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: The step of forming a body region in the first doped region and forming a source region in the body region comprises: forming a body doped region in the first doped region; forming a source doping region in the body doping region; A first sub-trench is formed in the first doping region, wherein the first sub-trench opens from the front surface of the substrate and penetrates the body doping region and the source doping region to form the body region and the source region.
3. The method for preparing a silicon carbide MOSFET device according to claim 1, characterized in that: The step of forming the split gate dielectric layer and the split gate conductive layer in the second sub-trench includes: forming a first sub-portion on a sidewall of the second sub-trench and forming a second sub-portion on a bottom wall of the second sub-trench; forming the split-gate conductive layer in a groove formed by the first sub-portion and the second sub-portion; A third sub-portion is formed on a side of the split gate conductive layer close to the front surface of the substrate, and the first sub-portion, the second sub-portion and the third sub-portion form the split gate dielectric layer.