Capacitance-voltage curve correction method, device, equipment and storage medium

Abstract

The present application discloses a method, apparatus, device and storage medium for correcting a capacitance-voltage curve. First, the superimposed voltage and output current of the target transistor can be obtained respectively through the high end and low end of the first impedance test bridge, and the superimposed voltage and output current of the reference transistor can be obtained respectively through the high end and low end of the second impedance test bridge. The target capacitance-voltage curve of the target transistor is drawn according to the superimposed voltage and output current of the target transistor, and the reference capacitance-voltage curve of the reference transistor is drawn according to the superimposed voltage and output current of the reference transistor. Then, several channel capacitance pairs are generated based on the target capacitance-voltage curve and the reference capacitance-voltage curve, and a correction capacitance-voltage curve is drawn based on the several channel capacitance pairs. By using a reference transistor and a target transistor, the present application can achieve high-precision correction of the capacitance-voltage curve of the target transistor to ensure accuracy and reliability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a capacitance-voltage curve correction method, device, equipment and storage medium. Background Art

[0002] Short channel effects exist in integrated circuits. To address this, transistor performance can be improved by adjusting the characteristics of the gate oxide layer, thereby reducing the short channel effect. This can be achieved by stacking a dielectric layer with a high dielectric constant (high-k) with silicon dioxide (SiO2).

[0003] Fully depleted silicon-on-insulator metal oxide semiconductor field-effect transistors, or FDSOI MOSFETs, utilize a gate process that stacks a high-k dielectric layer with SiO2. Extracting the equivalent SiO2 thickness (Equivalent Oxide Thickness, EOT)—the thickness at which the high-k dielectric layer and SiO2 achieve the same capacitance—is crucial for semiconductor processing, device design, and production. EOT is extracted based on the device's capacitance-voltage (CV) curve characteristics, but the CV curve extraction methods provided in related art are inaccurate.

[0004] Therefore, how to correct the CV curve to improve the accuracy of the CV curve is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] Based on the above problems, the present application provides a capacitance-voltage curve correction method, device, equipment and storage medium, which can correct the CV curve and thus improve the accuracy of the CV curve.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] A method for correcting a capacitance-voltage curve, the method comprising:

[0008] The superimposed voltage of the target transistor is obtained through the high end of the first impedance test bridge, and the output current of the target transistor is obtained through the low end of the first impedance test bridge; the front gate of the target transistor is connected to the high end of the first impedance test bridge; the source and drain of the target transistor are short-circuited, and the shorted source and drain of the target transistor are connected to the low end of the first impedance test bridge; the back gate of the target transistor is connected to the ground line;

[0009] The superimposed voltage of the reference transistor is obtained through the high end of the second impedance test bridge, and the output current of the reference transistor is obtained through the low end of the second impedance test bridge; the front gate of the reference transistor is connected to the high end of the second impedance test bridge; the source and drain of the reference transistor are short-circuited, and the shorted source and drain of the reference transistor are connected to the low end of the second impedance test bridge; the back gate of the reference transistor is connected to the ground line; the superimposed voltage is obtained by superimposing an AC voltage and a DC voltage; the channel length of the reference transistor is greater than the channel length of the target transistor;

[0010] plotting a target capacitance-voltage curve of the target transistor according to the superimposed voltage and output current of the target transistor, and plotting a reference capacitance-voltage curve of the reference transistor according to the superimposed voltage and output current of the reference transistor;

[0011] generating a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve;

[0012] A corrected capacitance-voltage curve is drawn based on the plurality of channel capacitance pairs.

[0013] In a possible implementation, generating a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve includes:

[0014] extracting a plurality of target channel capacitances from the target capacitance-voltage curve and extracting a plurality of reference channel capacitances from the reference capacitance-voltage curve;

[0015] The target channel capacitance and the reference channel capacitance at the same voltage form a channel capacitance pair.

[0016] In a possible implementation, drawing a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs includes:

[0017] Calculating a plurality of corrected channel capacitances according to the plurality of channel capacitance pairs, the corrected channel capacitance calculation formula, and the channel normalization formula;

[0018] The corrected capacitance-voltage curve is drawn based on the plurality of corrected channel capacitances.

[0019] In a possible implementation, the correction channel capacitance calculation formula is:

[0020]

[0021] Among them, C GC is the middle channel capacitance; C GC1 is the target channel capacitance of the target transistor; C GC2is the reference channel capacitance of the reference transistor; L1 is the channel length of the target transistor; L2 is the channel length of the reference transistor; C GC1 and C GC2 in the same trench capacitor pair.

[0022] In a possible implementation, the channel normalization formula is:

[0023]

[0024] Among them, C gc To correct the channel capacitance; C GC is the intermediate channel capacitance; W is the channel width of the target transistor; L1 is the channel length of the target transistor.

[0025] In a possible implementation, the method further includes:

[0026] When the correction capacitance-voltage curve is not saturated, extracting the characteristic capacitance of the target transistor from the correction capacitance-voltage curve by fitting;

[0027] The front gate oxide thickness of the target transistor is calculated based on the characteristic capacitance.

[0028] In a possible implementation, the method further includes:

[0029] When the correction capacitance-voltage curve is saturated, calculating the characteristic capacitance of the target transistor using a characteristic capacitance calculation formula;

[0030] Among them, the characteristic capacitance calculation formula is C gc,max is the minimum channel capacitance of the corrected capacitance-voltage curve; C gc,max is the maximum channel capacitance of the corrected capacitance-voltage curve; W is the channel width of the target transistor; and L1 is the channel length of the target transistor.

[0031] A capacitance-voltage curve correction device, the device comprising:

[0032] a first acquisition unit, configured to acquire a superimposed voltage of a target transistor through a high end of a first impedance test bridge, and acquire an output current of the target transistor through a low end of the first impedance test bridge; a front gate of the target transistor being connected to the high end of the first impedance test bridge; a source and a drain of the target transistor being short-circuited, and the shorted source and drain of the target transistor being connected to the low end of the first impedance test bridge; and a back gate of the target transistor being connected to a ground line;

[0033] a second acquisition unit, configured to acquire a superimposed voltage of a reference transistor through a high end of a second impedance test bridge, and acquire an output current of the reference transistor through a low end of the second impedance test bridge; a front gate of the reference transistor being connected to the high end of the second impedance test bridge; a source and a drain of the reference transistor being short-circuited, and the shorted source and drain of the reference transistor being connected to the low end of the second impedance test bridge; a back gate of the reference transistor being connected to a ground line; the superimposed voltage being obtained by superimposing an AC voltage and a DC voltage; and a channel length of the reference transistor being greater than a channel length of the target transistor;

[0034] a first drawing unit, configured to draw a target capacitance-voltage curve of the target transistor according to the superimposed voltage and output current of the target transistor, and to draw a reference capacitance-voltage curve of the reference transistor according to the superimposed voltage and output current of the reference transistor;

[0035] a generating unit, configured to generate a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve;

[0036] The second drawing unit is configured to draw a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs.

[0037] A capacitance-voltage curve correction device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the capacitance-voltage curve correction method described above is implemented.

[0038] A computer-readable storage medium stores instructions. When the instructions are executed on a terminal device, the terminal device executes the capacitance-voltage curve correction method as described above.

[0039] Compared with the prior art, this application has the following beneficial effects:

[0040] The present application provides a method, device, equipment and storage medium for correcting a capacitance-voltage curve. Specifically, when executing the method for correcting the capacitance-voltage curve provided in an embodiment of the present application, the superimposed voltage and output current of the target transistor can be obtained respectively through the high end and low end of the first impedance test bridge, and the superimposed voltage and output current of the reference transistor can be obtained respectively through the high end and low end of the second impedance test bridge, wherein the superimposed voltage is obtained by superimposing the AC voltage and the DC voltage, and the channel length of the reference transistor is greater than the channel length of the target transistor. Then, the target capacitance-voltage curve of the target transistor is drawn according to the superimposed voltage and output current of the target transistor, and the reference capacitance-voltage curve of the reference transistor is drawn according to the superimposed voltage and output current of the reference transistor. Then, based on the target capacitance-voltage curve and the reference capacitance-voltage curve, several channel capacitance pairs are generated. Then, based on several channel capacitance pairs, a correction capacitance-voltage curve is drawn. The present application can achieve high-precision correction of the capacitance-voltage curve of the target transistor by using a reference transistor and a target transistor, ensuring accuracy and reliability. This application is applicable not only to short-channel transistors, but also to other devices operating in carrier inversion mode, such as FinFETs (Fin Field-Effect Transistors) and GAAs (Gate-All-Around Field-Effect Transistors). Furthermore, this correction method is also applicable to transistors with large parasitic capacitance and unsaturated CV curves. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A flow chart of a capacitance-voltage curve correction method provided in an embodiment of the present application;

[0043] Figure 2 A comparison diagram of a target capacitance-voltage curve and a reference capacitance-voltage curve provided in an embodiment of the present application;

[0044] Figure 3 A comparison diagram of a target capacitance-voltage curve and a correction capacitance-voltage curve provided in an embodiment of the present application;

[0045] Figure 4 A characteristic capacitance fitting curve provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of a capacitance-voltage curve correction device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the background technology involved in the embodiments of the present application will be described below.

[0048] The short channel effect (SCE) is a phenomenon that occurs when manufacturing transistors with extremely short channel lengths, leading to unstable device performance and increased power consumption. To avoid SCE, a common approach is to improve transistor performance by adjusting the properties of the gate oxide layer, thereby reducing SCE.

[0049] A fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistor (FDSOI MOSFET) is a transistor structure made by stacking a dielectric layer with a high dielectric constant (high-к) with silicon dioxide (SiO2). Because the high-к dielectric layer has a higher relative dielectric constant (к), the physical thickness of the high-к dielectric layer is greater for the same characteristic capacitance, exponentially reducing the tunneling current and thus alleviating the impact of the short-channel effect. In this way, an equivalent SiO2 thickness can be achieved for the same capacitance, which is called the equivalent oxide thickness (EOT). EOT is crucial for semiconductor processing, device design, and production processes because it directly affects the performance and stability of transistors.

[0050] EOT is typically extracted from a device's capacitance-voltage (CV) curve. However, current methods for extracting CV curves suffer from inaccuracies, which can affect the accuracy and stability of process and device design.

[0051] In order to solve this problem, a method, device, equipment and storage medium for correcting a capacitance-voltage curve are provided in an embodiment of the present application. The superimposed voltage of the target transistor is first obtained through the high end of the first impedance test bridge, the output current of the target transistor is obtained through the low end of the first impedance test bridge, the superimposed voltage of the reference transistor is obtained through the high end of the second impedance test bridge, and the output current of the reference transistor is obtained through the low end of the second impedance test bridge, wherein the channel length of the reference transistor is greater than the channel length of the target transistor. Then, the target capacitance-voltage curve and the reference capacitance-voltage curve are drawn respectively according to the superimposed voltage and output current of the target transistor and the superimposed voltage and output current of the reference transistor. Then, several channel capacitance pairs are generated based on the target capacitance-voltage curve and the reference capacitance-voltage curve, and a correction capacitance-voltage curve is drawn based on several channel capacitance pairs. The present application can achieve high-precision correction of the capacitance-voltage curve of the target transistor by using a reference transistor and a target transistor to ensure accuracy and reliability.

[0052] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] See also Figure 1 , which is a flow chart of a method for correcting a capacitance-voltage curve provided by an embodiment of the present application, such as Figure 1 As shown, the capacitance-voltage curve correction method may include steps S101-S105:

[0054] S101: obtaining a superimposed voltage of a target transistor through a high end of a first impedance test bridge, and obtaining an output current of the target transistor through a low end of the first impedance test bridge.

[0055] The front gate of the target transistor is connected to the high side of the first impedance test bridge. The front gate is the control terminal of the transistor, which is usually connected to an appropriate control circuit to control the conductive state of the transistor. In this case, the front gate is connected to the high side of the first impedance test bridge, allowing the gate voltage or front gate voltage of the transistor to be measured.

[0056] The source and drain of the target transistor are shorted and connected to the low end of the first impedance test bridge. The source and drain of the transistor are usually the two ports through which current flows. By shorting them and connecting them to the low end of the first impedance test bridge, the output current of the transistor can be measured.

[0057] The back gate is connected to ground. The back gate or substrate (if any) of the transistor is usually connected to ground. Doing so ensures that the back gate of the transistor is at a stable potential and helps ensure the accuracy of the measurement.

[0058] At the high end of the first impedance test bridge, the voltage from the front gate of the target transistor and other possible voltage superpositions can be measured. The superposition voltage is obtained by superposing the AC voltage and the DC voltage. The superposition voltage V G(t)叠加 =V G(t)交流 +V G直流 .

[0059] At the low end of the first impedance test bridge, the value of the target transistor output current can be measured, which is the current flowing from source to drain.

[0060] An impedance bridge is an instrument used to measure the impedance of a circuit. It typically consists of four resistors: two standard resistors of known values ​​and two unknown resistors to be measured. By adjusting the resistors in the bridge to achieve a balanced circuit, the value of the unknown resistor can be calculated based on the known resistor values ​​and the balanced bridge conditions.

[0061] Impedance test bridges can be used to measure various types of impedance, including resistance, inductance, and capacitance. They are widely used in electronic circuit design, testing, and repair, providing accurate impedance measurement results.

[0062] Common impedance test bridges include Wheatstone Bridge, Maxwell Bridge, Kelvin Bridge, etc.

[0063] S102: Acquire the superimposed voltage of the reference transistor through the high end of the second impedance test bridge, and acquire the output current of the reference transistor through the low end of the second impedance test bridge.

[0064] The front gate of the reference transistor is connected to the high end of the second impedance test bridge. The source and drain of the reference transistor are short-circuited, and the shorted source and drain of the reference transistor are connected to the low end of the second impedance test bridge. The back gate of the reference transistor is connected to the ground line.

[0065] The high-side interface of the second impedance test bridge is used to measure the superimposed voltage of the reference transistor, that is, the voltage of the transistor in the circuit. Similarly, the low-side interface of the second impedance test bridge is used to measure the output current of the reference transistor, that is, the value of the current when it passes through the transistor.

[0066] Since there are AC and DC signals in the circuit when the transistor is working, the high end of the impedance test bridge obtains the superimposed voltage of the transistor.

[0067] The channel length of a transistor refers to the length of the path for current to flow from the source to the drain of the transistor. The channel length of the reference transistor is longer than the channel length of the target transistor, but not significantly longer.

[0068] S103: Draw a target capacitance-voltage curve of the target transistor according to the superimposed voltage and output current of the target transistor, and draw a reference capacitance-voltage curve of the reference transistor according to the superimposed voltage and output current of the reference transistor.

[0069] After obtaining the superimposed voltage and output current of the target transistor and the superimposed voltage and output current of the reference transistor, a target capacitance-voltage curve can be drawn according to the superimposed voltage and output current of the target transistor, and a reference capacitance-voltage curve can be drawn according to the superimposed voltage and output current of the reference transistor. Figure 2 As shown, Figure 2 A comparison diagram of a target capacitance-voltage curve and a reference capacitance-voltage curve provided in an embodiment of the present application is shown. Figure 2 The dotted line in FIG is a reference capacitance-voltage curve of a reference transistor with a channel length of 36 nanometers. Figure 2 The solid line in FIG. 5 is the target capacitance-voltage curve of the target transistor with a channel length of 26 nm. Figure 2 The horizontal coordinate V in G is the gate voltage in volts (V), the vertical axis is C GC is the mid-channel capacitance, measured in Farads (F).

[0070] S104: Generate a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve.

[0071] A plurality of channel capacitance pairs are generated based on channel capacitances extracted from capacitance-voltage curves of the target transistor and the reference transistor.

[0072] In a possible implementation, generating a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve includes:

[0073] A plurality of target channel capacitances are extracted from the target capacitance-voltage curve, and a plurality of reference channel capacitances are extracted from the reference capacitance-voltage curve. Then, the target channel capacitances and the reference channel capacitances at the same voltage are combined to form a channel capacitance pair.

[0074] Specifically, first, several target channel capacitances are extracted from the capacitance-voltage curve of the target transistor. These target channel capacitances are the capacitances between the channel region and the control gate, and have different values ​​at different voltages. Similarly, several reference channel capacitances can also be extracted from the capacitance-voltage curve of the reference transistor, and their values ​​at different voltages will also be different. Then, a target channel capacitance and a reference channel capacitance at the same voltage are combined to form a channel capacitance pair. Such a channel capacitance pair can be used for further analysis and comparison.

[0075] S105: Drawing a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs.

[0076] After obtaining a plurality of channel capacitance pairs, a corrected capacitance-voltage curve may be drawn based on the plurality of channel capacitance pairs.

[0077] In a possible implementation, drawing a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs includes:

[0078] According to the plurality of channel capacitance pairs, the correction channel capacitance calculation formula and the channel normalization formula, a plurality of correction channel capacitances are calculated, and then a correction capacitance-voltage curve is drawn based on the plurality of correction channel capacitances.

[0079] Specifically, first, based on the extracted channel capacitance pairs, the correction channel capacitance calculation formula and the channel normalization formula, several correction channel capacitances are calculated. This process involves using specific formulas and methods to calculate and convert the data of the channel capacitance pairs to obtain the corrected and normalized channel capacitance values. Secondly, based on these corrected channel capacitance values, a correction capacitance-voltage curve is drawn. This means using the corrected channel capacitance as the ordinate and the voltage as the abscissa to draw a correction capacitance-voltage curve on the graph. Through this curve, you can intuitively understand the changes in the correction capacitance of the transistor as the voltage changes.

[0080] In a possible implementation, the correction channel capacitance calculation formula is:

[0081]

[0082] Among them, C GC is the middle channel capacitance; C GC1 is the target channel capacitance of the target transistor; C GC2 is the reference channel capacitance of the reference transistor; L1 is the channel length of the target transistor; L2 is the channel length of the reference transistor; C GC1 and C GC2 in the same trench capacitor pair.

[0083] In a possible implementation, the channel normalization formula is:

[0084]

[0085] Among them, C gc To correct the channel capacitance; C GC is the intermediate channel capacitance; W is the channel width of the target transistor; L1 is the channel length of the target transistor.

[0086] Channel Width: refers to the lateral dimension of the channel region (perpendicular to the direction of current flow), that is, the distance between the source and drain. Channel width determines the width of the channel for electrons or holes to flow in the transistor, thereby affecting the conductivity and performance of the transistor.

[0087] Channel length: This refers to the longitudinal dimension of the channel region (parallel to the direction of current flow), i.e., the distance between the source and drain. Channel length affects transistor performance indicators such as switching speed, current drive capability, and output resistance.

[0088] like Figure 3 As shown, Figure 3 A comparison diagram of a target capacitance-voltage curve and a correction capacitance-voltage curve provided in an embodiment of the present application is shown. Figure 3 The dotted line in FIG is the target capacitance-voltage curve of the target transistor with a channel length of 26 nanometers. Figure 3 The solid line in FIG is the corrected capacitance-voltage curve of the target transistor with a channel length of 26 nm. Figure 3 The horizontal coordinate V in G is the gate voltage in volts (V), the vertical axis is C gc is the corrected channel capacitance, measured in Farads (F).

[0089] In a possible implementation, for the cases where the corrected capacitance-voltage curve of the target transistor is unsaturated and saturated, the front gate oxide thickness of the target transistor can be calculated by the following method:

[0090] For the case where the corrected capacitance-voltage curve of the target transistor is not saturated, when the corrected capacitance-voltage curve is not saturated, the characteristic capacitance of the target transistor is extracted from the corrected capacitance-voltage curve by fitting.

[0091] A non-saturated corrected capacitance-voltage curve indicates that the capacitance still exhibits a linear or nearly linear relationship with voltage on the corrected capacitance-voltage curve, and has not reached saturation. In other words, the capacitance still changes significantly with increasing voltage, and the capacitance value does not stop increasing or decrease in magnitude.

[0092] Specifically, the characteristic capacitance of the target transistor can be extracted from the corrected capacitance-voltage curve by the following fitting method:

[0093] Cgc (V G ) curve conforms to the following relationship:

[0094]

[0095] Among them, Qi is the inversion charge, is the thermal voltage and n is the ideality factor.

[0096] Further transformation of the above formula:

[0097]

[0098] From formula (2), we can see that It changes linearly with Qi, and the inverse of the slope of the curve is the characteristic capacitance C ox The relationship between the device's inversion charge Qi and VG can be expressed by the formula C gc Points are awarded as Qi.

[0099] Therefore, draw The curve is fitted in the area where the curve has good linearity to obtain the characteristic capacitance fitting curve. Figure 4 As shown, Figure 4 A characteristic capacitance fitting curve provided in an embodiment of the present application is: Figure 4 Where k is the slope of the characteristic capacitance fitting curve. Figure 4 The horizontal axis Qi is the inversion charge, and the vertical axis inversion charge Qi is related to the correction channel capacitance C gc ratio.

[0100] Calculate the slope of the characteristic capacitance fitting curve Right now The accurate C ox value.

[0101] By formula The C extracted above can be ox , vacuum dielectric constant ε0 and relative dielectric constant ε of front gate SiO2 r Substitute into the above formula to extract the equivalent oxide thickness EOT of the front gate.

[0102] In the case where the correction capacitance-voltage curve of the target transistor is saturated, when the correction capacitance-voltage curve is saturated, the characteristic capacitance of the target transistor may be calculated using a characteristic capacitance calculation formula.

[0103] Saturation of the corrected capacitance-voltage curve indicates that if the capacitance stops changing with increasing voltage after reaching a certain value, or if the increase in capacitance becomes very small, the curve is said to be saturated. In other words, saturation of the corrected capacitance-voltage curve means that the capacitance has stopped changing or has flattened out, and can no longer increase.

[0104] Among them, the characteristic capacitance calculation formula is C gc,max is the minimum channel capacitance of the corrected capacitance-voltage curve; C gc,max is the maximum channel capacitance of the corrected capacitance-voltage curve; W is the channel width of the target transistor; and L1 is the channel length of the target transistor.

[0105] After the characteristic capacitance is calculated, the front gate oxide thickness EOT of the target transistor can be calculated based on the characteristic capacitance:

[0106]

[0107] Where ε0 is the dielectric constant of vacuum, which is approximately equal to 8.85×10 -12 F / m; ε r is the relative dielectric constant of SiO2, usually 3.9.

[0108] Based on the contents of S101-S105, it is known that the superimposed voltage and output current of the target transistor are first obtained respectively through the high end and low end of the first impedance test bridge, and the superimposed voltage and output current of the reference transistor whose channel length is greater than the channel length of the target transistor are obtained respectively through the high end and low end of the second impedance test bridge. Then, according to the superimposed voltage, output current of the target transistor and the superimposed voltage and output current of the reference transistor, the target capacitance-voltage curve and the reference capacitance-voltage curve are drawn respectively. Then, based on the target capacitance-voltage curve and the reference capacitance-voltage curve, several channel capacitance pairs are generated. Finally, the correction capacitance-voltage curve is drawn based on several channel capacitance pairs. The present application can achieve high-precision correction of the capacitance-voltage curve of the target transistor by using a reference transistor and a target transistor to ensure accuracy and reliability. At the same time, the present application is not only applicable to transistors with short channels, but also to other devices with carrier inversion working mode. In addition, this correction method is also applicable to transistors with large parasitic capacitance and unsaturated CV curve.

[0109] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of a capacitance-voltage curve correction device provided in an embodiment of the present application. Figure 5 As shown, the capacitance-voltage curve correction device includes:

[0110] A first acquisition unit 501 is configured to acquire a superimposed voltage of a target transistor through a high end of a first impedance test bridge, and acquire an output current of the target transistor through a low end of the first impedance test bridge; a front gate of the target transistor is connected to the high end of the first impedance test bridge; a source and a drain of the target transistor are short-circuited, and the shorted source and drain of the target transistor are connected to the low end of the first impedance test bridge; and a back gate of the target transistor is connected to a ground line;

[0111] A second acquisition unit 502 is configured to acquire a superimposed voltage of a reference transistor through a high end of a second impedance test bridge, and acquire an output current of the reference transistor through a low end of the second impedance test bridge; the front gate of the reference transistor is connected to the high end of the second impedance test bridge; the source and drain of the reference transistor are short-circuited, and the shorted source and drain of the reference transistor are connected to the low end of the second impedance test bridge; the back gate of the reference transistor is connected to a ground line; the superimposed voltage is obtained by superimposing an AC voltage and a DC voltage; and the channel length of the reference transistor is greater than the channel length of the target transistor;

[0112] A first drawing unit 503 is configured to draw a target capacitance-voltage curve of the target transistor according to the superimposed voltage and output current of the target transistor, and to draw a reference capacitance-voltage curve of the reference transistor according to the superimposed voltage and output current of the reference transistor;

[0113] a generating unit 504, configured to generate a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve;

[0114] The second drawing unit 505 is configured to draw a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs.

[0115] In a possible implementation, the generating unit 504 specifically includes:

[0116] a first extraction unit, configured to extract a plurality of target channel capacitances from the target capacitance-voltage curve and a plurality of reference channel capacitances from the reference capacitance-voltage curve;

[0117] The construction unit is used to form a channel capacitance pair with a target channel capacitance and a reference channel capacitance at the same voltage.

[0118] In a possible implementation, the second drawing unit 505 specifically includes:

[0119] a first calculation unit, configured to calculate a plurality of corrected channel capacitances according to the plurality of channel capacitance pairs, the corrected channel capacitance calculation formula, and the channel normalization formula;

[0120] A third drawing unit is configured to draw the corrected capacitance-voltage curve based on the plurality of corrected channel capacitances.

[0121] In a possible implementation, the correction channel capacitance calculation formula is:

[0122]

[0123] Among them, C GC is the middle channel capacitance; C GC1 is the target channel capacitance of the target transistor; C GC2 is the reference channel capacitance of the reference transistor; L1 is the channel length of the target transistor; L2 is the channel length of the reference transistor; C GC1 and C GC2 in the same trench capacitor pair.

[0124] In a possible implementation, the channel normalization formula is:

[0125]

[0126] Among them, C gc To correct the channel capacitance; C GC is the intermediate channel capacitance; W is the channel width of the target transistor; L1 is the channel length of the target transistor.

[0127] In a possible implementation, the apparatus further includes:

[0128] a second extraction unit, configured to extract a characteristic capacitance of the target transistor from the correction capacitance-voltage curve by fitting when the correction capacitance-voltage curve is not saturated;

[0129] A second calculation unit is configured to calculate a front gate oxide thickness of the target transistor based on the characteristic capacitance.

[0130] In a possible implementation, the apparatus further includes:

[0131] a third calculation unit, configured to calculate the characteristic capacitance of the target transistor using a characteristic capacitance calculation formula when the correction capacitance-voltage curve is saturated;

[0132] Among them, the characteristic capacitance calculation formula is C gc,max is the minimum channel capacitance of the corrected capacitance-voltage curve; C gc,max is the maximum channel capacitance of the corrected capacitance-voltage curve; W is the channel width of the target transistor; and L1 is the channel length of the target transistor.

[0133] In addition, an embodiment of the present application also provides a capacitance-voltage curve correction device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the capacitance-voltage curve correction method described above is implemented.

[0134] In addition, an embodiment of the present application further provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on a terminal device, the terminal device executes the capacitance-voltage curve correction method as described above.

[0135] The embodiment of the present application provides a correction device for a capacitance-voltage curve, first using a first acquisition unit 501 to obtain the superimposed voltage and output current of the target transistor through the high end and low end of the first impedance test bridge, and using a second acquisition unit 502 to obtain the superimposed voltage and output current of the reference transistor through the high end and low end of the second impedance test bridge. The first drawing unit 503 draws the target capacitance-voltage curve of the target transistor according to the superimposed voltage and output current of the target transistor, and draws the reference capacitance-voltage curve of the reference transistor according to the superimposed voltage and output current of the reference transistor. Then, a generation unit 504 is used to generate several channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve, so that the second drawing unit 505 can draw a correction capacitance-voltage curve based on several channel capacitance pairs. By using a reference transistor and a target transistor, the present application can achieve high-precision correction of the capacitance-voltage curve of the target transistor to ensure accuracy and reliability. At the same time, the present application is not only applicable to short-channel transistors, but also to other devices with carrier inversion working mode, such as FinFET and GAA. In addition, this correction method is also applicable to transistors with large parasitic capacitance and unsaturated CV curves.

[0136] The above is a detailed introduction to the correction method, device, equipment and storage medium of a capacitance-voltage curve provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0137] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0138] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0139] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Claims

1. A method for correcting a capacitance-voltage curve, characterized in that: The method comprises: The superimposed voltage of the target transistor is obtained through the high end of the first impedance test bridge, and the output current of the target transistor is obtained through the low end of the first impedance test bridge; the front gate of the target transistor is connected to the high end of the first impedance test bridge; the source and drain of the target transistor are short-circuited, and the shorted source and drain of the target transistor are connected to the low end of the first impedance test bridge; the back gate of the target transistor is connected to the ground line; The superimposed voltage of the reference transistor is obtained through the high end of the second impedance test bridge, and the output current of the reference transistor is obtained through the low end of the second impedance test bridge; the front gate of the reference transistor is connected to the high end of the second impedance test bridge; the source and drain of the reference transistor are short-circuited, and the shorted source and drain of the reference transistor are connected to the low end of the second impedance test bridge; the back gate of the reference transistor is connected to the ground line; the superimposed voltage is obtained by superimposing an AC voltage and a DC voltage; the channel length of the reference transistor is greater than the channel length of the target transistor; plotting a target capacitance-voltage curve of the target transistor according to the superimposed voltage and output current of the target transistor, and plotting a reference capacitance-voltage curve of the reference transistor according to the superimposed voltage and output current of the reference transistor; generating a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve; drawing a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs; Drawing a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs includes: Calculating a plurality of corrected channel capacitances according to the plurality of channel capacitance pairs, the corrected channel capacitance calculation formula, and the channel normalization formula; The corrected capacitance-voltage curve is drawn based on the plurality of corrected channel capacitances.

2. The method according to claim 1, characterized in that The generating a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve includes: extracting a plurality of target channel capacitances from the target capacitance-voltage curve and extracting a plurality of reference channel capacitances from the reference capacitance-voltage curve; The target channel capacitance and the reference channel capacitance at the same voltage form a channel capacitance pair.

3. The method according to claim 1, characterized in that The calculation formula for the corrected channel capacitance is: ； in, is the middle channel capacitance; is a target channel capacitance of the target transistor; is the reference channel capacitance of the reference transistor; L1 is the channel length of the target transistor; L2 is the channel length of the reference transistor; and in the same trench capacitor pair.

4. The method according to claim 1, wherein The channel normalization formula is: ； in, To correct the channel capacitance; is the intermediate channel capacitance; W is the channel width of the target transistor; L1 is the channel length of the target transistor.

5. The method according to claim 1, wherein The method further comprises: When the correction capacitance-voltage curve is not saturated, extracting the characteristic capacitance of the target transistor from the correction capacitance-voltage curve by fitting; The front gate oxide thickness of the target transistor is calculated based on the characteristic capacitance.

6. The method according to claim 5, characterized in that The method further comprises: When the correction capacitance-voltage curve is saturated, calculating the characteristic capacitance of the target transistor using a characteristic capacitance calculation formula; Among them, the characteristic capacitance calculation formula is ; is the minimum channel capacitance of the corrected capacitance-voltage curve; is the maximum channel capacitance of the corrected capacitance-voltage curve; W is the channel width of the target transistor; and L1 is the channel length of the target transistor.

7. A capacitance-voltage curve correction device, characterized in that: The device comprises: a first acquisition unit, configured to acquire a superimposed voltage of a target transistor through a high end of a first impedance test bridge, and acquire an output current of the target transistor through a low end of the first impedance test bridge; a front gate of the target transistor being connected to the high end of the first impedance test bridge; a source and a drain of the target transistor being short-circuited, and the shorted source and drain of the target transistor being connected to the low end of the first impedance test bridge; and a back gate of the target transistor being connected to a ground line; a second acquisition unit, configured to acquire a superimposed voltage of a reference transistor through a high end of a second impedance test bridge, and acquire an output current of the reference transistor through a low end of the second impedance test bridge; a front gate of the reference transistor being connected to the high end of the second impedance test bridge; a source and a drain of the reference transistor being short-circuited, and the shorted source and drain of the reference transistor being connected to the low end of the second impedance test bridge; a back gate of the reference transistor being connected to a ground line; the superimposed voltage being obtained by superimposing an AC voltage and a DC voltage; and a channel length of the reference transistor being greater than a channel length of the target transistor; a first drawing unit, configured to draw a target capacitance-voltage curve of the target transistor according to the superimposed voltage and output current of the target transistor, and to draw a reference capacitance-voltage curve of the reference transistor according to the superimposed voltage and output current of the reference transistor; a generating unit, configured to generate a plurality of channel capacitance pairs based on the target capacitance-voltage curve and the reference capacitance-voltage curve; a second drawing unit, configured to draw a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs; Drawing a corrected capacitance-voltage curve based on the plurality of channel capacitance pairs includes: Calculating a plurality of corrected channel capacitances according to the plurality of channel capacitance pairs, the corrected channel capacitance calculation formula, and the channel normalization formula; The corrected capacitance-voltage curve is drawn based on the plurality of corrected channel capacitances.

8. A capacitance-voltage curve correction device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for correcting the capacitance-voltage curve according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, and when the instructions are executed on a terminal device, the terminal device executes the capacitance-voltage curve correction method according to any one of claims 1 to 6.

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