Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: etching a metal hard mask material layer by a first etching process until the surface of a dielectric structure is exposed to form a metal hard mask layer and a first groove in the metal hard mask layer; performing a morphology repair process on the side wall of the first groove by a second etching process, wherein the etching rate of the second etching process is lower than the etching rate of the first etching process, the etching time of the second etching process is longer than the etching time of the first etching process, and the bombardment force of the second etching process is lower than the bombardment force of the first etching process, so as to reduce the surface roughness of the side wall of the first groove; after the second etching process, etching the dielectric structure by using the metal hard mask layer as a mask to form a groove in the dielectric layer, so as to reduce the roughness morphology deviation of the metal hard mask layer, and further reduce the roughness morphology deviation of the groove in the dielectric layer formed subsequently, so as to optimize the morphology of the first conductive structure in the groove and improve the device performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the development of process technology, the size of transistors has been continuously reduced, and RC delay has seriously affected the performance of integrated circuits. For this reason, copper is used to replace aluminum as a metal interconnect material. Copper interconnects can be realized using Damascus process and mechanical chemical polishing (abbreviated as CMP) technology.

[0003] The existing Damascus process can be divided into the via first trench last (VIA First Trench Last, abbreviated as VFTL) process and the trench first via last (Trench First VIA Last, abbreviated as TFVL) process. Among them, the trench first via last process is widely used, and its process feature is to use a metal hard mask layer to etch the trench first and then etch the via.

[0004] However, the existing Damascus process needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a base and a dielectric structure located on the surface of the base, the dielectric structure comprising a dielectric layer; forming a metal hard mask material layer on the surface of the dielectric structure; etching the metal hard mask material layer using a first etching process until the surface of the dielectric structure is exposed to form a metal hard mask layer and a first groove located in the metal hard mask layer; performing a morphology repair treatment on the sidewall of the first groove using a second etching process, and the etching rate of the second etching process is less than the etching rate of the first etching process, the etching time of the second etching process is greater than the etching time of the first etching process, and the bombardment force of the second etching process is less than the bombardment force of the first etching process, so as to reduce the surface roughness of the sidewall of the first groove; after the second etching process, etching the dielectric structure using the metal hard mask layer as a mask to form a groove in the dielectric layer.

[0007] Optionally, the process parameters of the first etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power ranges from 300W to 800W, the gas pressure range in the etching chamber is 5mTorr to 8mTorr, and the etching gas flow rate is 100sccm to 300sccm.

[0008] Optionally, the process parameters of the second etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power ranges from 50W to 150W, the gas pressure range in the etching chamber is 5mTorr to 8mTorr, and the etching gas flow rate is 10sccm to 50sccm.

[0009] Optionally, the method further includes: forming a first conductive structure in the trench.

[0010] Optionally, after the second etching process and before forming the groove, the method further includes: forming a first photoresist layer on the surface of the metal hard mask layer and in part of the first groove; the first photoresist layer exposes part of the surface of the dielectric structure; using the first photoresist layer as a mask, etching the dielectric structure to form a second groove in the dielectric structure; after forming the second groove, removing the first photoresist layer; while forming the groove, etching the dielectric layer at the bottom of the second groove until the substrate surface is exposed to form a through hole at the bottom of the groove; the first conductive structure is also located in the through hole.

[0011] Optionally, the method for forming the first conductive structure includes: forming a metal material layer on the surface of the dielectric structure, in the through hole and in the groove; and planarizing the metal material layer until the surface of the dielectric layer is exposed.

[0012] Optionally, the dielectric structure further includes an etch stop layer located between the dielectric layer and the substrate; the substrate has a second conductive structure or a device structure therein; the through hole is also located in the etch stop layer, and the second conductive structure or the device structure is exposed at the bottom of the through hole.

[0013] Optionally, the method for forming the metal hard mask layer and the first groove also includes: forming a patterned second photoresist layer on the surface of the metal hard mask material layer; using the second photoresist layer as a mask, and adopting the first etching process to etch the metal hard mask material layer to form the metal hard mask layer and the first groove.

[0014] Optionally, before etching the metal hard mask material layer, the method further includes: forming a first adhesion barrier layer on the surface of the metal mask material layer, wherein the second photoresist layer is located on the surface of the first adhesion barrier layer; and etching the first adhesion barrier layer using the second photoresist layer as a mask.

[0015] Optionally, the material of the first adhesion barrier layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0016] Optionally, the first adhesion barrier layer has a thickness ranging from 4 nm to 15 nm.

[0017] Optionally, the dielectric structure further includes a second adhesion barrier layer located on the surface of the dielectric layer, and a material of the second adhesion barrier layer is different from a material of the dielectric layer; and the metal hard mask material layer is located on the surface of the second adhesion barrier layer.

[0018] Optionally, an etching selectivity ratio of the second etching process to the second adhesion barrier layer and the metal hard mask layer ranges from 5 to 15.

[0019] Optionally, the material of the second adhesion barrier layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0020] Optionally, the second adhesion barrier layer has a thickness ranging from 30 nm to 70 nm.

[0021] Optionally, the material of the metal hard mask layer includes titanium nitride or titanium nitride.

[0022] Optionally, the thickness of the metal hard mask material layer is in a range of 20 nm to 50 nm.

[0023] Optionally, the material of the dielectric layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a second etching process is used to perform morphology repair treatment on the side wall of the first groove, and the etching rate of the second etching process is lower than the etching rate of the first etching process, the etching time of the second etching process is longer than the etching time of the first etching process, and the bombardment force of the second etching process is lower than the bombardment force of the first etching process, so as to reduce the surface roughness of the side wall of the first groove, which is beneficial to reducing the profile roughness morphology deviation of the metal hard mask layer, and further reducing the profile roughness morphology deviation of the groove in the subsequently formed dielectric layer, which is beneficial to optimizing the morphology of the first conductive structure in the groove and improving device performance.

[0026] Furthermore, before etching the metal hard mask material layer, a first adhesion barrier layer is formed on the surface of the metal mask material layer. In addition to serving as a barrier layer, the first adhesion barrier layer also serves to protect the metal hard mask layer during the subsequent etching process, thereby reducing etching damage to the top surface of the metal hard mask layer and reducing the generation of excessive metal by-products during etching, thereby introducing a more complex by-product system.

[0027] Furthermore, the dielectric structure also includes a second adhesion barrier layer located on the surface of the dielectric layer. In addition to serving as an adhesion and barrier layer, the second adhesion barrier layer also serves to protect the dielectric layer in the second etching process, thereby reducing etching damage to the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 3 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0029] Figure 4 is corresponding to Figure 2 CD-SEM morphology photograph of the hard mask layer;

[0030] Figure 5 is corresponding to Figure 3 CD-SEM morphology photograph of the groove;

[0031] Figure 6 is a flow chart of steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0032] Figures 7 to 14 is a structural schematic diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0033] Fig.15 The CD-SEM morphology comparison photographs of the unmodified metal hard mask layer and the improved metal hard mask layer in the embodiment of the present invention;

[0034] Fig.16 The CD-SEM morphology comparison photos of the unmodified groove and the improved groove in the embodiment of the present invention are shown. DETAILED DESCRIPTION

[0035] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0036] As described in the background art, the existing Damascus process needs to be further improved. Now, a formation process of a semiconductor structure is described and analyzed.

[0037] Figures 1 to 3It is a cross-sectional schematic diagram of the formation process of a semiconductor structure.

[0038] Please refer to Figure 1 , providing a substrate, the substrate comprising a base 100, an etch stop layer 101 located on the surface of the base 100, and a low-k dielectric layer 102 located on the etch stop layer 101; forming a first oxide layer 103 on the surface of the substrate, a hard mask material layer 104 located on the surface of the first oxide layer 103, and a second oxide layer 105 located on the hard mask material layer 104; forming a patterned photoresist layer 106 on the surface of the second oxide layer 105.

[0039] Please refer to Figure 2 , with the photoresist layer 106 (such as Figure 1 ) as a mask, etching the second oxide layer 105 and the hard mask material layer 104 until the first oxide layer 103 is exposed, forming a groove 107 in the second oxide layer 105 and the hard mask material layer 104, and forming a hard mask layer 108 with the hard mask material layer 104; removing the photoresist layer 106.

[0040] Please refer to Figure 3 , using the hard mask layer 108 as a mask, etching the first oxide layer 103 and the low-k dielectric layer 102 to form a groove 109 in the low-k dielectric layer 102. During the etching process, the second oxide layer 105 on the surface of the hard mask layer 108 is also removed.

[0041] The above method is used in the Damascus process, and the hard mask layer 108 is made of TiN metal material to optimize the resolution of the photolithography and etching processes, control the graphic size of the groove 109, and improve the accuracy of the photolithography lines.

[0042] However, the morphology of the metal wire formed by the above method is poor. For details, please refer to Figure 4 and Figure 5 ,in, Figure 4 is corresponding to Figure 2 The actual morphology scan photo of the hard mask layer, Figure 5 is corresponding to Figure 3 Scanning photo of the actual morphology of the groove.

[0043] Specifically, in the etching process of forming the hard mask layer 108, the hard mask material layer 104 is etched through a main etching process. At the same time, in order to ensure that the hard mask material layer 104 is completely etched, the first oxide layer 103 at the bottom of the opening 107 is also etched to a certain extent. The rough morphology deviation of the hard mask layer 108 formed by the main etching process is relatively large (e.g., Figure 2 The dashed line and Figure 4As shown in FIG. 1 ), the morphology of the formed groove 109 is greatly deviated (as shown in FIG. Figure 3 The dashed line and Figure 5 As shown in the figure, the morphology of the final metal line is affected, which in turn affects the device performance.

[0044] In order to solve the above problems, in a method for forming a semiconductor structure provided by the present invention, a second etching process is used to perform morphology repair treatment on the side wall of the first groove, and the etching rate of the second etching process is lower than the etching rate of the first etching process, the etching time of the second etching process is longer than the etching time of the first etching process, and the bombardment force of the second etching process is lower than the bombardment force of the first etching process, so as to reduce the surface roughness of the side wall of the first groove, which is beneficial to reducing the profile roughness morphology deviation of the metal hard mask layer, and further reducing the profile roughness morphology deviation of the groove in the subsequently formed dielectric layer, which is beneficial to optimizing the morphology of the first conductive structure in the groove and improving device performance.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figure 6 is a flow chart of the steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0047] In this embodiment, the method for forming the semiconductor structure includes the following steps:

[0048] Step S201, providing a substrate, wherein the substrate comprises a base and a dielectric structure located on a surface of the base, wherein the dielectric structure comprises a dielectric layer;

[0049] Step S202, forming a metal hard mask material layer on the surface of the dielectric structure;

[0050] Step S203, etching the metal hard mask material layer using a first etching process until the surface of the dielectric structure is exposed, so as to form a metal hard mask layer and a first groove located in the metal hard mask layer;

[0051] Step S204, using a second etching process to perform morphology repair processing on the sidewall of the first groove, wherein the etching rate of the second etching process is lower than the etching rate of the first etching process, the etching time of the second etching process is longer than the etching time of the first etching process, and the bombardment force of the second etching process is lower than the bombardment force of the first etching process, so as to reduce the surface roughness of the sidewall of the first groove;

[0052] Step S205 , after the second etching process, etching the dielectric structure using the metal hard mask layer as a mask to form a trench in the dielectric layer.

[0053] The following is a detailed description with reference to the accompanying drawings.

[0054] Figures 7 to 14 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0055] Please refer to Figure 7 , providing a substrate, the substrate comprising a base 300 and a dielectric structure 31 located on a surface of the base 300 , the dielectric structure 31 comprising a dielectric layer 311 .

[0056] The material of the dielectric layer 311 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0057] In this embodiment, the material of the dielectric layer 311 is a low dielectric constant material (low-K material, k<3.9). Specifically, the material of the dielectric layer 311 is SiCOH.

[0058] The substrate 300 has a second conductive structure or a device structure therein, which is subsequently used to form a first conductive structure electrically connected to the conductive structure or the device structure.

[0059] In this embodiment, the substrate 300 has a second conductive structure (not shown in the figure).

[0060] In another embodiment, the substrate has a device structure therein, and the device structure may include a transistor, a diode, a triode, a capacitor, an inductor, etc.

[0061] In this embodiment, the dielectric structure 31 further includes an etch stop layer 312 located between the dielectric layer 311 and the substrate 300 .

[0062] In this embodiment, the dielectric structure 31 further includes a second adhesion barrier layer 313 located on the surface of the dielectric layer 311. The material of the second adhesion barrier layer 313 is different from that of the dielectric layer 311. In another embodiment, the dielectric structure 31 may not include the second adhesion barrier layer.

[0063] The material of the second adhesion barrier layer 313 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0064] In this embodiment, the material of the second adhesion barrier layer 313 is silicon oxide.

[0065] The second adhesion barrier layer 313 is formed by a chemical vapor deposition (CVD) process.

[0066] In this embodiment, the second adhesion barrier layer 313 is formed by a plasma enhanced chemical vapor deposition (PECVD) process using TEOS (tetraethoxysilane) as a deposition source.

[0067] The second adhesion barrier layer 313 has a thickness ranging from 30 nm to 70 nm. The thickness range is selected because if the thickness is too thin, it may not provide barrier protection and adhesion, and if it is too thick, it may be difficult to etch later.

[0068] Please continue to refer to Figure 7 , a metal hard mask material layer 302 is formed on the surface of the dielectric structure 31 .

[0069] In this embodiment, the metal hard mask material layer 302 is located on the surface of the second adhesion barrier layer 313. The second adhesion barrier layer 313 acts as a barrier layer to prevent the metal hard mask material layer 302 from directly contacting the dielectric layer 311, reduce the diffusion of metal ions in the metal hard mask material layer 302 into the dielectric layer 311, and affect the performance of the dielectric layer 311. At the same time, it is beneficial to improve the adhesion of the metal hard mask material layer 302 on the surface of the dielectric structure 31.

[0070] The material of the metal hard mask material layer 302 includes titanium nitride (TiN) or tantalum nitride (TaN). In this embodiment, the material of the metal hard mask material layer 302 is titanium nitride.

[0071] In this embodiment, the thickness of the metal hard mask material layer 302 is in the range of 20 nm to 50 nm. The thickness is selected because if the thickness is too thin, it may not play a role in blocking protection and adhesion, and if it is too thick, it is difficult to etch later.

[0072] Subsequently, the metal hard mask material layer 302 is etched by a first etching process until the surface of the dielectric structure 31 is exposed, so as to form a metal hard mask layer and a first groove in the metal hard mask layer.

[0073] In this embodiment, the method for forming the metal hard mask layer and the first groove is as follows. Figures 8 to 9 .

[0074] Please refer to Figure 8 A patterned second photoresist layer 303 is formed on the surface of the metal hard mask material layer 302 .

[0075] The method for forming the second photoresist layer 303 includes: forming a second photoresist material layer (not shown in the figure) on the surface of the metal hard mask material layer 302 ; and patterning the second photoresist material layer to form the second photoresist layer 303 .

[0076] In this embodiment, before etching the metal hard mask material layer 302, a first adhesion barrier layer 304 is formed on the surface of the metal mask material layer 302; and the second photoresist layer 303 is located on the surface of the first adhesion barrier layer 304. In another embodiment, the first adhesion barrier layer may not be formed.

[0077] Here, the first adhesion barrier layer 304 acts as a barrier layer to prevent the metal hard mask material layer 302 and the second photoresist layer 303 from directly contacting each other, thereby reducing the diffusion of metal ions in the metal hard mask material layer 302 into the second photoresist layer 303, which affects the performance of the second photoresist layer 303 .

[0078] The material of the first adhesion barrier layer 304 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride oxynitride.

[0079] In this embodiment, the material of the first adhesion barrier layer 304 is silicon oxide.

[0080] The first adhesion barrier layer 304 is formed by a chemical vapor deposition process.

[0081] In this embodiment, the first adhesion barrier layer 304 is obtained by reacting gas silane (SiH 4 ) and highly purified oxygen (O 2 ).

[0082] In this embodiment, the thickness of the first adhesion barrier layer 304 is in the range of 4 nm to 15 nm. The reason for selecting the above thickness range is that if the thickness is too thin, it may not play a barrier role, and if it is too thick, it is difficult to etch, which affects the etching morphology of the metal mask layer.

[0083] Please refer to Fig. 9 , with the second photoresist layer 303 (such as Figure 8 ) is a mask, and the first etching process is used to etch the metal hard mask material layer 302 (as shown Figure 8 As shown), the metal hard mask layer 305 and the first groove 306 are formed.

[0084] At this point, the sidewall roughness of the first groove 306 formed in the first etching process is relatively large (eg Fig. 9In order to improve the accuracy of pattern transfer, a subsequent second etching process is required to repair the morphology.

[0085] The first groove 306 exposes the dielectric structure. Specifically, in this embodiment, the first groove 306 exposes the second adhesion barrier layer 313. In another embodiment, the first groove exposes the dielectric layer.

[0086] In this embodiment, the process parameters of the first etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power range is 300W to 800W, the gas pressure range in the etching chamber is 5mTorr to 8mTorr, and the etching gas flow rate is 100sccm to 300sccm.

[0087] In this embodiment, the first adhesion barrier layer 304 is etched using the second photoresist layer 303 as a mask.

[0088] In this embodiment, the material of the metal hard mask layer 305 includes TiN or TaN.

[0089] In this embodiment, after the metal hard mask layer 305 is formed, the second photoresist layer 303 is also removed.

[0090] Please refer to Fig.10 , a second etching process is used to perform a morphology repair treatment on the side wall of the first groove 306, and the etching rate of the second etching process is lower than the etching rate of the first etching process, the etching time of the second etching process is longer than the etching time of the first etching process, and the bombardment force of the second etching process is lower than the bombardment force of the first etching process, so as to reduce the surface roughness of the side wall of the first groove 306 (such as Fig.10 shown by the dashed line in the middle).

[0091] Here, the morphology repair treatment is used to reduce the surface roughness of the side wall of the first groove 306, which is beneficial to reducing the profile roughness morphology deviation of the metal hard mask layer 305, and then reducing the profile roughness morphology deviation of the groove in the dielectric layer formed subsequently, which is beneficial to optimizing the morphology of the first conductive structure in the groove and improving device performance.

[0092] In this embodiment, the process parameters of the second etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power range is 50W to 150W, the gas pressure range in the etching chamber is 5mTorr to 8mTorr, and the etching gas flow rate is 10sccm to 50sccm.

[0093] In this embodiment, in the second etching process, the first adhesion barrier layer 304 on the surface of the metal hard mask layer 305 also serves to protect the top surface of the metal hard mask layer 305, thereby reducing etching damage to the top surface of the metal hard mask layer 305 and reducing the problem of excessive metal by-products generated during etching, thereby introducing a more complex by-product system.

[0094] In this embodiment, the etching selectivity ratio of the second etching process to the second adhesion barrier layer 313 and the metal hard mask material layer is in a range of 5 to 15.

[0095] In this embodiment, since the surface of the dielectric layer 311 is covered with the second adhesion barrier layer 313, the first groove 306 exposes the second adhesion barrier layer 313. In the second etching process, the second adhesion barrier layer 313 also plays a role in protecting the dielectric layer 311 and reducing etching damage to the dielectric layer 311.

[0096] Subsequently, after the second etching process, the dielectric structure 31 is etched using the metal hard mask layer 305 as a mask to form a trench in the dielectric layer 311 .

[0097] Here, in order to further illustrate the technical effect of the technical solution of the present invention, please refer to Fig.15 .

[0098] Fig.15 The actual morphology comparison photos of the metal hard mask layer before and after the morphology repair treatment in the embodiment of the present invention are shown.

[0099] in, Fig.15 (a) is a morphology photograph of the metal hard mask layer before morphology repair treatment. Fig.15 (b) is a morphology photograph of the metal hard mask layer after morphology repair treatment.

[0100] It can be seen from the morphology comparison photos that the morphology repair treatment significantly reduces the rough profile deviation of the metal hard mask layer.

[0101] In this embodiment, after the second etching process and before forming the groove, please refer to Figure 11 to Figure 12 .

[0102] Please refer to Fig.11 A first photoresist layer 307 is formed on the surface of the metal hard mask layer 305 and in a portion of the first groove 306 , and the first photoresist layer 307 exposes a portion of the surface of the dielectric structure 31 .

[0103] In this embodiment, the method for forming the first photoresist layer 307 includes: forming a first photoresist material layer (not shown in the figure) on the surface of the metal hard mask layer 305 and in the first groove 306 ; and patterning the first photoresist material layer to form the first photoresist layer 307 .

[0104] Please refer to Fig.12 , with the first photoresist layer 307 (such as Fig.11 ) is used as a mask, the dielectric structure 31 is etched to form a second groove 308 in the dielectric structure 31; after the second groove 308 is formed, the first photoresist layer 307 is removed.

[0105] Specifically, the second groove 308 is located in the dielectric layer 311 and the second adhesion barrier layer 313. In another embodiment, the second groove may be located only in the second adhesion barrier layer.

[0106] Please refer to Fig.13 After the second etching process, the dielectric structure 31 is etched using the metal hard mask layer 305 as a mask to form a trench 309 in the dielectric layer 311 .

[0107] In this embodiment, during the etching process of forming the groove 309, the first adhesion barrier layer 304 also serves to protect the metal hard mask layer 305, thereby reducing etching damage to the top surface of the metal hard mask layer 305 and reducing the problem of excessive metal by-products generated during etching, thereby introducing a more complex by-product system.

[0108] In this embodiment, while forming the trench 309 , the dielectric layer 311 at the bottom of the second recess 308 is also etched until the surface of the substrate 300 is exposed, so as to form a through hole 310 at the bottom of the trench 309 .

[0109] In this embodiment, the through hole 311 is also located in the etching stop layer 312, and the second conductive structure (not shown in the figure) is exposed at the bottom of the through hole 311. In another embodiment, the through hole exposes the device structure.

[0110] Please Fig.13 Based on the reference Fig.14 , a first conductive structure 320 is formed in the trench 309 .

[0111] In this embodiment, the first conductive structure 320 is also located in the through hole 310 .

[0112] In this embodiment, the method for forming the first conductive structure 320 includes: forming a metal material layer (not shown in the figure) on the surface of the dielectric structure 31 , in the through hole 310 and in the groove 309 ; and planarizing the metal material layer until the surface of the dielectric layer 311 is exposed.

[0113] Here, in order to further illustrate the technical effect of the technical solution of the present invention, please refer to Fig.15 and Fig.16 .

[0114] Fig.15 The CD-SEM morphology comparison photos of the unmodified metal hard mask layer and the improved metal hard mask layer in the embodiment of the present invention are shown.

[0115] in, Fig.15 (a) is a morphology photograph of the metal hard mask layer without improvement (i.e. before morphology repair treatment). Fig.15 (b) is a morphology photograph of the improved metal hard mask layer (i.e., after morphology repair treatment).

[0116] It can be seen from the morphology comparison photos that the morphology repair treatment significantly reduces the rough profile deviation of the metal hard mask layer.

[0117] Specifically, the edge roughness (Line Width roughness, abbreviated as LWR) of the metal hard mask layer before the improvement is about 8 nm, and the edge roughness of the metal hard mask layer after the improvement is about 4 nm.

[0118] Fig.16 The CD-SEM morphology comparison photos of the unmodified groove and the improved groove in the embodiment of the present invention are shown.

[0119] in, Fig.16 (c) in the figure is not improved (corresponding to Fig.15 The trench morphology photograph of the metal hard mask layer without morphology treatment in (a). Fig.16 (d) in the figure is the improved one (corresponding to Fig.15 (b) A photograph of the trench morphology of the metal hard mask layer after morphology repair treatment.

[0120] It can be seen from the morphology comparison photos that the improvement of the profile roughness morphology deviation of the metal hard mask layer is conducive to reducing the profile roughness morphology deviation of the groove in the formed dielectric layer.

[0121] Specifically, the edge roughness of the unmodified groove is about 7 nm, and the edge roughness of the improved groove is about 3 nm to 4 nm.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base and a dielectric structure located on a surface of the base, the dielectric structure comprising a dielectric layer; Forming a metal hard mask material layer on the surface of the dielectric structure, wherein the material of the metal hard mask material layer includes titanium nitride or titanium nitride; The metal hard mask material layer is etched by a first etching process until the surface of the dielectric structure is exposed to form a metal hard mask layer and a first groove in the metal hard mask layer, wherein the process parameters of the first etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power ranges from 300W to 800W, the gas pressure in the etching chamber ranges from 5mTorr to 8mTorr, and the etching gas flow rate ranges from 100sccm to 300sccm; A second etching process is used to perform morphology repair treatment on the sidewall of the first groove, and the process parameters of the second etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power range is 50W to 150W, the gas pressure range in the etching chamber is 5mTorr to 8mTorr, the etching gas flow rate is 10sccm to 50sccm, and the etching rate of the second etching process is less than the etching rate of the first etching process, the etching time of the second etching process is greater than the etching time of the first etching process, and the bombardment force of the second etching process is less than the bombardment force of the first etching process, so as to reduce the surface roughness of the sidewall of the first groove; After the second etching process, the dielectric structure is etched using the metal hard mask layer as a mask to form a groove in the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method also includes forming a first conductive structure in the trench.

3. The method for forming a semiconductor structure according to claim 2, wherein: After the second etching process and before forming the groove, the method further includes: forming a first photoresist layer on the surface of the metal hard mask layer and in part of the first groove; the first photoresist layer exposes part of the surface of the dielectric structure; using the first photoresist layer as a mask, etching the dielectric structure to form a second groove in the dielectric structure; after forming the second groove, removing the first photoresist layer; while forming the groove, etching the dielectric layer at the bottom of the second groove until the substrate surface is exposed to form a through hole at the bottom of the groove; the first conductive structure is also located in the through hole.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the first conductive structure comprises: forming a metal material layer on the surface of the dielectric structure, in the through hole and in the groove; and planarizing the metal material layer until the surface of the dielectric layer is exposed.

5. The method for forming a semiconductor structure according to claim 3, wherein: The dielectric structure also includes an etch stop layer located between the dielectric layer and the substrate; the substrate has a second conductive structure or device structure in it; the through hole is also located in the etch stop layer, and the bottom of the through hole exposes the second conductive structure or device structure.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the metal hard mask layer and the first groove also includes: forming a patterned second photoresist layer on the surface of the metal hard mask material layer; using the second photoresist layer as a mask and adopting the first etching process to etch the metal hard mask material layer to form the metal hard mask layer and the first groove.

7. The method for forming a semiconductor structure according to claim 6, wherein: Before etching the metal hard mask material layer, the method further includes: forming a first adhesion barrier layer on the surface of the metal mask material layer, wherein the second photoresist layer is located on the surface of the first adhesion barrier layer; and etching the first adhesion barrier layer using the second photoresist layer as a mask.

8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the first adhesion barrier layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

9. The method for forming a semiconductor structure according to claim 7, wherein: The first adhesion barrier layer has a thickness ranging from 4 nm to 15 nm.

10. The method for forming a semiconductor structure according to claim 7, wherein: The dielectric structure further includes a second adhesion barrier layer located on the surface of the dielectric layer, wherein the material of the second adhesion barrier layer is different from that of the dielectric layer; and the metal hard mask material layer is located on the surface of the second adhesion barrier layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The etching selectivity ratio of the second etching process to the second adhesion barrier layer and the metal hard mask layer is in a range of 5 to 15.

12. The method for forming a semiconductor structure according to claim 10, wherein: The material of the second adhesion barrier layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

13. The method for forming a semiconductor structure according to claim 10, wherein: The second adhesion barrier layer has a thickness ranging from 30 nm to 70 nm.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the metal hard mask layer includes titanium nitride or titanium nitride.

15. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the metal hard mask material layer is in a range of 20 nm to 50 nm.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

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