Infrared detector manufacturing method and infrared detector

Abstract

The present application discloses a method for manufacturing an infrared detector and an infrared detector, which belongs to the field of infrared detectors. The method performs photolithography in steps, and the pixel sub-array patterns formed by each step of photolithography are combined to form a target pixel array pattern. Since the spacing of the pixel sub-array patterns formed by each step of photolithography is greater than the spacing of the target pixel array pattern, the difficulty of small-pitch photolithography is reduced and the control pattern accuracy is improved; at the same time, a hard mask layer is deposited on the surface of the wafer in advance before the step-by-step photolithography to transfer the photolithography pattern to the hard mask layer, which further improves the pattern accuracy and avoids the cumulative damage to the wafer caused by the step-by-step photolithography, etching, and degumming process. Therefore, the pattern deformation can be effectively avoided, thereby improving the consistency between pixels, and then improving the quality of the infrared detector and the processing yield rate. The present application can be applied to the preparation of small-pitch infrared detectors, especially for infrared detectors with pixel spacing below 5μm. The processing effect is good.

Description

Technical Field

[0001] The present application relates to the field of infrared detectors, and in particular to a method for manufacturing an infrared detector and an infrared detector. Background Art

[0002] In the traditional infrared detector manufacturing process, the infrared detector material needs to be patterned by photolithography technology to form a pixel array pattern. Taking mercury cadmium telluride infrared photosensitive wafer as an example, since the wafer itself is a square wafer, the uniformity of the coating will be affected during the photoresist coating process, causing the photoresist to produce edge effects and present a surface undulation state, and the coated photoresist is generally more than 4μm thick, which will cause a certain degree of distortion in the photolithography pattern. With the development of infrared detector technology, the pixel spacing is getting smaller and smaller, which will cause the distortion phenomenon to be further aggravated, thus seriously affecting the quality of infrared detectors. Therefore, how to improve the quality of infrared detectors is a technical problem that technicians in this field currently need to solve. Summary of the invention

[0003] The purpose of this application is to provide an infrared detector manufacturing method and an infrared detector, so as to improve the quality of the infrared detector.

[0004] To achieve the above objectives, the present application provides a method for manufacturing an infrared detector, comprising:

[0005] depositing a hard mask layer on a surface of the passivation layer of the wafer facing away from the absorber layer;

[0006] Coating a photoresist on a surface of the hard mask layer facing away from the passivation layer;

[0007] Performing photolithography on the photoresist to form a pixel subarray photolithography pattern;

[0008] Etching the hard mask layer at the position of the pixel subarray photolithography pattern to form a pixel subarray mask pattern; the spacing between adjacent pixel patterns in the pixel subarray mask pattern is greater than the spacing between adjacent pixel patterns in the target pixel array mask pattern;

[0009] After forming the pixel subarray mask pattern, removing the remaining photoresist;

[0010] Repeating the step of coating the photoresist on the surface of the hard mask layer away from the passivation layer, to the step of removing the remaining photoresist, until the pixel subarray mask patterns are combined to form a target pixel array mask pattern;

[0011] The absorption layer at the position of the target pixel array mask pattern forms a PN junction, and the lead-out electrode is interconnected with the readout circuit to obtain the infrared detector.

[0012] Optionally, the absorption layer at the target pixel array mask pattern position forms a PN junction, and the lead-out electrode is interconnected with the readout circuit to obtain the infrared detector, including:

[0013] Implanting ions into the target pixel array mask pattern position to form the PN junction in the absorption layer at the target pixel array mask pattern position;

[0014] Etching the passivation layer at the target pixel array mask pattern position until the PN junction is exposed to form a through hole penetrating the passivation layer;

[0015] Depositing metal in the through hole and performing photolithography to form an electrode;

[0016] The electrodes are interconnected with a readout circuit to obtain the infrared detector.

[0017] Optionally, the hard mask layer is a silicon dioxide mask layer; the thickness of the silicon dioxide mask layer is And include the values ​​at both ends.

[0018] Optionally, the thickness of the photoresist is less than 1 μm.

[0019] Optionally, before depositing the hard mask layer on the surface of the passivation layer of the wafer away from the absorption layer, the method further comprises:

[0020] Depositing a metal layer on a surface of the passivation layer of the wafer facing away from the absorption layer;

[0021] Performing a patterning process on the metal layer to form a metal mark;

[0022] Accordingly, the step of depositing a hard mask layer on a surface of the passivation layer of the wafer facing away from the absorption layer comprises:

[0023] Depositing the hard mask layer on the surface of the wafer on which the metal mark is formed;

[0024] Accordingly, the photolithography of the photoresist to form a pixel subarray photolithography pattern includes:

[0025] The metal mark is aligned and the photoresist is photolithographically processed to form the pixel subarray photolithographic pattern.

[0026] Optionally, the step of patterning the metal layer to form a metal mark includes:

[0027] Coating a photoresist on the surface of the metal layer away from the passivation layer, and photolithographically forming a marking pattern;

[0028] The metal layer and the remaining photoresist at the non-mark pattern position are removed to form the metal mark.

[0029] Optionally, depositing a metal layer on a surface of the passivation layer of the wafer facing away from the absorption layer includes:

[0030] Depositing a chromium layer and a gold layer in sequence on the surface of the passivation layer of the wafer facing away from the absorption layer;

[0031] Accordingly, removing the metal layer and the remaining photoresist at the non-marked pattern position to form the metal mark includes:

[0032] Using an ion beam etching device to remove the gold layer and part of the chromium layer at the non-mark pattern position;

[0033] After the ion beam etching is completed, removing the remaining photoresist;

[0034] After removing the photoresist, the wafer is placed in an etching solution to remove the remaining chromium layer.

[0035] Optionally, after placing the wafer in a corrosive solution to remove the remaining chromium layer, the method further comprises:

[0036] The wafer is subjected to a heat treatment process; the temperature during the heat treatment process is 150° C. to 180° C., including the values ​​at both ends; the time for the heat treatment process is 30 min to 60 min, including the values ​​at both ends.

[0037] Optionally, the thickness of the chromium layer is And including the values ​​at both ends; the thickness of the gold layer is And include the values ​​at both ends.

[0038] To achieve the above-mentioned purpose, the present application also provides an infrared detector, including: an infrared detector prepared by the above-mentioned infrared detector manufacturing method.

[0039] Obviously, the infrared detector manufacturing method provided by the present application forms a target pixel array pattern by combining pixel subarray patterns formed by each step of photolithography. Since the spacing of the pixel subarray patterns formed by each step of photolithography is greater than the spacing of the target pixel array pattern, the difficulty of small-pitch photolithography is reduced and the control pattern accuracy is improved. At the same time, a hard mask layer is deposited on the surface of the wafer before the step-by-step photolithography to transfer the photolithography pattern to the hard mask layer, which further improves the pattern accuracy and avoids the cumulative damage to the wafer caused by the step-by-step photolithography, etching, and degumming processes. Therefore, it can effectively avoid pattern deformation, thereby improving the consistency between pixels, and then improving the quality of the infrared detector and the processing yield rate. The present application also provides an infrared detector manufacturing method, which is prepared by the above-mentioned infrared detector manufacturing method. Compared with the infrared detector prepared by the traditional infrared detector manufacturing method, the pattern distortion rate is lower, the consistency between pixels is higher, the quality of the infrared detector is higher, and the processing yield rate is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0041] Figures 1 to 6 It is a schematic diagram of the conventional infrared detector manufacturing process;

[0042] Figure 7 A schematic diagram of a first type of graphic distortion provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of a second type of graphic distortion provided in an embodiment of the present application;

[0044] Fig. 9 A schematic diagram of a third type of graphic distortion provided in an embodiment of the present application;

[0045] Fig.10 A flowchart of a method for manufacturing an infrared detector provided in an embodiment of the present application;

[0046] Figures 11 to 17 A schematic diagram of a manufacturing process flow of an infrared detector provided in an embodiment of the present application;

[0047] Fig.18 The pixel subarray mask pattern formed after the first photolithography, etching and stripping provided in the embodiment of the present application;

[0048] Fig.19A pixel subarray mask pattern formed after the second photolithography, etching, and stripping provided in the embodiment of the present application;

[0049] Fig. 20 A pixel subarray mask pattern formed after the third photolithography, etching, and stripping provided in the embodiment of the present application;

[0050] Fig.21 The pixel subarray mask pattern formed after the fourth photolithography, etching and stripping provided in the embodiment of the present application;

[0051] Fig. 22 The pixel array mask pattern is formed after four times of photolithography, etching and stripping provided in the embodiment of the present application.

[0052] The following are the descriptions of the reference numerals:

[0053] 1-wafer; 1.1-absorption layer; 1.2-passivation layer; 2-photoresist; 3-PN junction; 4-electrode; 5-readout circuit; 6-metal layer; 6.1-metal mark; 7-silicon dioxide mask layer. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] The traditional infrared detector manufacturing process is as follows: 1. Figure 1 As shown, a photoresist 2 is applied to the surface of the passivation layer 1.2 in the wafer 1, and an ion implantation area pattern is photolithographically formed; 2. Figure 2 As shown, ions are injected at the graphic position of the ion injection area; 3. Figure 3 As shown, after ion implantation, a PN junction 3 is formed in the absorption layer 1.1; 4. Figure 4 As shown, an opening pattern is again photolithographically formed at a position corresponding to the PN junction 3 on the surface of the passivation layer 1.2, and a hole is etched in the passivation layer 12 at the position of the opening pattern; 5. Figure 5 As shown, fill the hole with metal, lead out the electrode 4, and obtain the infrared detector chip; 6. Figure 6 As shown, the electrode 4 and the readout circuit 5 are interconnected to obtain an infrared detector.

[0056] With the development of infrared detector technology, the size of pixel arrays in devices continues to increase, while the pixel spacing continues to decrease. Under the traditional infrared detector manufacturing process, the difficulty of manufacturing products with a spacing of 5μm has further increased, mainly manifested in higher requirements for graphic accuracy and smaller line seams (L / S, i.e. line width / line spacing) of the pixel array. Taking mercury cadmium telluride infrared photosensitive wafers as an example, since the wafer itself is a square wafer, the process of coating the photoresist will affect the uniformity of the coating, causing the photoresist to produce edge effects and present a surface undulation state, and the thickness of the coated photoresist is generally more than 4μm, which will cause certain distortions in the photolithography pattern. Figure 7 The pixel pattern shown in the figure has burrs. This situation will become more serious in smaller pixel spacing (i.e. smaller pattern gap). Figure 8 As shown in the figure, the random pixel pattern has serious burrs, etc. This type of distortion will lead to differences in response between pixels, resulting in a large number of randomly scattered blind pixels in the pixel array. Fig. 9 The distortion shown in the figure is a relatively serious distortion. The upper pattern of the photoresist will be close to each other, resulting in the inability to form effective isolation between pixels, causing the infrared detector to fail to work properly. Therefore, the present application provides a method for manufacturing an infrared detector, which can effectively avoid pattern deformation by step-by-step photolithography of large-pitch pixel subarray patterns and pre-depositing a hard mask layer on the surface of the wafer before step-by-step photolithography to transfer the photolithography pattern to the hard mask layer, thereby improving the consistency between pixels and thus improving the quality of the infrared detector and the processing yield rate.

[0057] Please refer to Fig.10 , Fig.10 A flowchart of a method for manufacturing an infrared detector provided in an embodiment of the present application, the method may include:

[0058] S101: depositing a hard mask layer on a surface of the passivation layer of the wafer away from the absorption layer.

[0059] It should be noted that the chip 1 used in this embodiment includes an absorption layer 1.1 and a passivation layer 1.2 arranged in sequence along the thickness direction. This embodiment does not limit the specific type of chip 1, and the corresponding chip 1 can be used according to the type of infrared detector actually required. For example, the chip 1 used can be a mercury cadmium telluride infrared photosensitive chip or an indium antimonide infrared photosensitive chip. Among them, the absorption layer 1.1 in the mercury cadmium telluride infrared photosensitive chip is made of mercury cadmium telluride material, and the absorption layer 1.1 in the indium antimonide infrared photosensitive chip is made of indium antimonide material. Mercury cadmium telluride material and indium antimonide material are both infrared sensitive materials.

[0060] This embodiment does not limit the specific type of the hard mask layer, and any hard mask layer can be used. For example, the hard mask layer can be a silicon dioxide mask layer 7. This embodiment does not limit the specific thickness of the silicon dioxide mask layer 7, and the specific thickness of the silicon dioxide mask layer 7 can be determined according to actual conditions. For example, the thickness of the silicon dioxide mask layer 7 can be And include the values ​​at both ends.

[0061] Furthermore, a clear mark with high brightness and high contrast can be used to improve the alignment accuracy of each photolithography, thereby effectively reducing the alignment cumulative deviation of multiple photolithography. Before step S101 in this embodiment, the following may also be included:

[0062] Depositing a metal layer 6 on the surface of the passivation layer 1.2 of the wafer 1 facing away from the absorption layer 1.1;

[0063] Performing a patterning process on the metal layer 6 to form a metal mark 6.1;

[0064] Accordingly, step S101 may include: depositing a hard mask layer on the surface of the wafer 1 on which the metal mark 6.1 is formed;

[0065] Accordingly, step S103 may include: aligning the metal mark 6.1, performing photolithography on the photoresist, and forming a pixel subarray photolithography pattern.

[0066] The present embodiment does not limit the specific type of the metal layer 6, which may be any metal layer 6, or a stacked layer of at least two metal layers 6. The present embodiment does not limit the specific method of depositing the metal layer 6, as long as it is ensured that a metal layer 6 can be formed on the surface of the passivation layer 1.2, for example, an ion deposition device may be used to deposit the metal layer 6 on the surface of the passivation layer 1.2 of the wafer 1 away from the absorption layer 1.1. The present embodiment does not limit the specific voltage value of the ion beam during the deposition process using the ion deposition device, for example, the voltage of the ion beam may be less than or equal to 300V.

[0067] The specific shape and position of the metal mark 6.1 are not important in this embodiment, as long as the mark has high enough brightness, high enough contrast, and is clear enough so that the mark can be recognized by subsequent photolithography.

[0068] This embodiment does not limit the specific method of graphic processing, as long as it can ensure that the metal mark 6.1 can be formed. For example, photoresist 2 can be coated on the surface of the metal layer 6 away from the passivation layer 1.2, and a marking pattern can be formed by photolithography; the metal layer 6 and the remaining photoresist 2 at the non-marking pattern position are removed to form the metal mark 6.1.

[0069] This embodiment does not limit the specific method of removing the metal layer 6, as long as it is ensured that the metal layer 6 at the non-marked pattern position can be removed, for example, an ion etching device can be used to remove the metal layer 6 at the non-marked pattern position. In the process of etching the metal layer 6, certain damage may be caused to the interface of the absorption layer 1.1 of the wafer 1. In order to alleviate the damage to the interface of the absorption layer 1.1 caused by the etching of the metal layer 6, the present embodiment deposits a chromium layer and a gold layer in sequence on the surface of the passivation layer 1.2 of the wafer 1 away from the absorption layer 1.1; accordingly, removing the metal layer 6 and the remaining photoresist 2 at the non-marked pattern position to form a metal mark 6.1 may include: using an ion beam etching device to remove the gold layer and part of the chromium layer at the non-marked pattern position; after the ion beam etching is completed, removing the remaining photoresist 2; after removing the photoresist 2, placing the wafer 1 in a corrosive solution to remove the remaining chromium layer. It should be noted that in the process of etching the metal layer 6 in this embodiment, by retaining part of the chromium layer, the damage to the interface of the absorption layer 1.1 caused by the etching of the metal layer 6 can be alleviated.

[0070] This embodiment does not limit the specific thickness of the chromium layer, and the specific thickness of the chromium layer can be determined according to actual conditions. For example, the thickness of the chromium layer can be This embodiment does not limit the specific thickness of the gold layer, and the specific thickness of the gold layer can be determined according to actual conditions. For example, the thickness of the gold layer can be And include the values ​​at both ends.

[0071] The present embodiment does not limit the specific type of the etching liquid, as long as it can be ensured to etch away the chromium layer.

[0072] Furthermore, in order to eliminate the damage at the interface of the absorption layer 1.1 caused during the etching process of the metal layer 6, after placing the wafer 1 in the etching solution to remove the remaining chromium layer, this embodiment may also include: performing a heat treatment process on the wafer 1; the temperature during the heat treatment process is 150°C to 180°C, including the values ​​at both ends; the time for the heat treatment process is 30min to 60min, including the values ​​at both ends.

[0073] S102: coating photoresist on the surface of the hard mask layer away from the passivation layer.

[0074] This embodiment does not limit the specific thickness of the photoresist. In order to ensure the pattern accuracy, the thickness of the photoresist in this embodiment can be less than 1 μm.

[0075] S103: Photolithography is performed on the photoresist to form a pixel subarray photolithography pattern.

[0076] This embodiment does not limit the specific type of pixel subarray photolithography patterns formed by each photolithography, as long as it is ensured that all pixel subarray mask patterns formed can finally be combined to form a target pixel array mask pattern. Further, in this embodiment, the pixel subarray photolithography patterns formed by each photolithography can be different to prevent repetition in the formed pixel subarray photolithography patterns, resulting in repeated etching of the repeated positions, causing unnecessary damage to the hard mask layer, thereby affecting the pattern accuracy.

[0077] S104: etching the hard mask layer at the position of the pixel subarray photolithography pattern to form a pixel subarray mask pattern; the spacing between adjacent pixel patterns in the pixel subarray mask pattern is greater than the spacing between adjacent pixel patterns in the target pixel array mask pattern.

[0078] It should be noted that in the present embodiment, multiple photolithography, etching and stripping processes need to be repeated before the target pattern is formed, and each time the photolithography, etching and stripping process is performed, certain damage may be caused to the absorption layer 1.1 of the chip 1. By pre-depositing a hard mask layer on the surface of the passivation layer 1.2 to transfer the photolithography pattern to the hard mask layer, the cumulative damage to the absorption layer 1.1 caused by the step-by-step photolithography, etching and stripping processes can be avoided.

[0079] S105: After forming the pixel subarray mask pattern, remove the remaining photoresist.

[0080] S106: Repeat the step of coating photoresist on the surface of the hard mask layer away from the passivation layer, and the step of removing the remaining photoresist, until the pixel sub-array mask patterns are combined to form a target pixel array mask pattern.

[0081] This embodiment does not limit the number of repeated executions, as long as it is ensured that all the formed pixel sub-array mask patterns can be combined to form a target pixel array mask pattern, and the execution must be repeated at least twice.

[0082] S107: forming a PN junction in the absorption layer at the target pixel array mask pattern position, and leading out electrodes to be interconnected with a readout circuit to obtain an infrared detector.

[0083] The present embodiment does not limit the specific method of realizing interconnection, as long as it can ensure that the electrical connection with the readout circuit can be realized. For example, ions may be injected into the target pixel array mask pattern position to form a PN junction 3 in the absorption layer 1.1 at the target pixel array mask pattern position; the passivation layer 1.2 at the target pixel array mask pattern position is etched until the PN junction 3 is exposed to form a through hole penetrating the passivation layer 1.2; metal is deposited in the through hole and photolithographically formed to form an electrode 4; the electrode 4 is interconnected with the readout circuit to obtain an infrared detector.

[0084] Based on the above embodiments, the present application forms a target pixel array pattern by combining pixel sub-array patterns formed by each step of photolithography. Since the spacing of the pixel sub-array patterns formed by each step of photolithography is greater than the spacing of the target pixel array pattern, the difficulty of small-pitch photolithography is reduced and the accuracy of controlling the pattern is improved. At the same time, a hard mask layer is pre-deposited on the surface of the chip before the step-by-step photolithography to transfer the photolithography pattern to the hard mask layer, which further improves the pattern accuracy and avoids the cumulative damage to the chip caused by the step-by-step photolithography, etching, and degumming processes. Therefore, it can effectively avoid pattern deformation, thereby improving the consistency between pixels, and further improving the quality of the infrared detector and the processing yield rate.

[0085] An embodiment of the present application also provides an infrared detector, including: an infrared detector prepared by the infrared detector manufacturing method described above.

[0086] Based on the above embodiments, the infrared detector of the present application is prepared by the above infrared detector manufacturing method. Compared with the infrared detector prepared by the traditional infrared detector manufacturing method, the image distortion rate is lower, the consistency between pixels is higher, the quality of the infrared detector is higher, and the processing yield is higher.

[0087] The following is a specific example to illustrate the infrared detector manufacturing process. The process is as follows:

[0088] 1. If Fig.11 As shown, on a wafer 1 deposited with a passivation layer 1.2 (a mercury cadmium telluride infrared photosensitive wafer or an indium antimonide infrared photosensitive wafer, etc.) a metal layer 6 including a chromium layer and a gold layer is sequentially deposited by an ion deposition device; wherein the thickness of the chromium layer is (including the values ​​at both ends), the thickness of the gold layer is (including the values ​​at both ends); the voltage of the ion beam does not exceed 300V;

[0089] 2. If Fig.12 As shown, a layer of photoresist 2 is coated on the surface of the wafer 1, and alignment marks are photolithographically processed. After the mark pattern is formed, the gold layer and part of the chromium layer at the non-marked part are removed by ion beam etching equipment, and then the photoresist 2 is removed, and the wafer 1 is placed in a chromium etching solution to remove the excess chromium layer; so far, as shown in FIG. Fig.13 As shown, a high-brightness, high-contrast clear metal mark 6.1 required for subsequent photolithography is formed;

[0090] 3. The wafer 1 is subjected to a heat treatment process at a temperature of 150° C. to 180° C. (including the values ​​at both ends) and a time of 30 min to 60 min (including the values ​​at both ends) in order to eliminate the damage at the interface of the absorption layer 1.1 caused by the metal etching in step 2;

[0091] 4. If Fig.14 As shown, a silicon dioxide mask layer 7 is grown on the surface of the wafer 1, with a thickness of (including the values ​​at both ends);

[0092] 5. A layer of photoresist is coated on the wafer 1. To ensure the pattern accuracy, the thickness of the photoresist is less than 1 μm. In this step, the photolithography process originally completed by one step of photolithography is divided into several steps to reduce the pattern density of each photolithography, that is, to increase the spacing between pixel patterns. In this embodiment, it is divided into 4 steps. This step requires a high-definition mark formed based on step 2 to improve the alignment accuracy of each photolithography. In this step, each photolithography is performed and an etching is performed once to transfer the photolithography pattern to the silicon dioxide mask layer 7. Figures 18 to 21 As shown, after 4 times of photolithography, etching, and stripping, the Fig. 22 The mask pattern of the small pitch (5μm) array shown in the figure is as follows Fig.15 The silicon dioxide mask layer 7 after patterning is shown;

[0093] 6. If Fig.16 As shown, based on the silicon dioxide mask pattern formed in step 5, ion implantation is performed to form a photoelectric PN junction 3 array with a small pixel pitch; after the ion implantation, the passivation layer 1.2 is directly etched based on the mask pattern of the silicon dioxide mask layer 7 until the PN junction 3 is exposed, thereby forming a through hole penetrating the passivation layer 1.2;

[0094] 7. If Fig.17 As shown, the remaining silicon dioxide mask layer 7 is removed, and then metal is deposited in the through hole and photolithographically formed to form an electrode 4; the electrode 4 is interconnected with the readout circuit 5 to obtain the required small-pitch infrared detector chip.

[0095] Specific examples are used herein to illustrate the principles and implementation methods of the present application, and the embodiments are in a progressive relationship, each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. The description of the above embodiments is only used to help understand the method and core ideas of the present application. For ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0096] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A method for manufacturing an infrared detector, characterized in that: include: Depositing a chromium layer and a gold layer in sequence on the surface of the passivation layer of the wafer facing away from the absorption layer; Coating photoresist on the surface of the gold layer away from the passivation layer, and photolithographically forming a marking pattern; Using an ion beam etching device to remove the gold layer and part of the chromium layer at the non-marked pattern position; After the ion beam etching is completed, removing the remaining photoresist; After removing the photoresist, placing the wafer in an etching solution to remove the remaining chromium layer; Depositing a hard mask layer on the surface of the wafer having the metal mark formed thereon; Coating a photoresist on a surface of the hard mask layer facing away from the passivation layer; Aligning the metal mark, photolithography the photoresist to form a pixel subarray photolithography pattern; Etching the hard mask layer at the position of the pixel subarray photolithography pattern to form a pixel subarray mask pattern; The spacing between adjacent pixel patterns in the pixel subarray mask pattern is greater than the spacing between adjacent pixel patterns in the target pixel array mask pattern; After forming the pixel subarray mask pattern, removing the remaining photoresist; Repeating the step of coating the photoresist on the surface of the hard mask layer away from the passivation layer, to the step of removing the remaining photoresist, until the pixel subarray mask patterns are combined to form a target pixel array mask pattern; The absorption layer at the position of the target pixel array mask pattern forms a PN junction, and the lead-out electrode is interconnected with the readout circuit to obtain the infrared detector.

2. The method for manufacturing an infrared detector according to claim 1, characterized in that: The absorption layer at the target pixel array mask pattern position forms a PN junction, and the electrode is connected to the readout circuit to obtain the infrared detector, including: Implanting ions into the target pixel array mask pattern position to form the PN junction in the absorption layer at the target pixel array mask pattern position; Etching the passivation layer at the target pixel array mask pattern position until the PN junction is exposed to form a through hole penetrating the passivation layer; Depositing metal in the through hole and performing photolithography to form an electrode; The electrodes are interconnected with a readout circuit to obtain the infrared detector.

3. The method for manufacturing an infrared detector according to claim 1, characterized in that: The hard mask layer is a silicon dioxide mask layer; the thickness of the silicon dioxide mask layer is 5000 Å to 20000 Å, including the values ​​at both ends.

4. The method for manufacturing an infrared detector according to claim 1, characterized in that: The thickness of the photoresist is less than 1 μm.

5. The method for manufacturing an infrared detector according to claim 1, characterized in that: After placing the wafer in a corrosive solution to remove the remaining chromium layer, the method further comprises: The wafer is subjected to a heat treatment process; the temperature during the heat treatment process is 150° C. to 180° C., including the values ​​at both ends; the time for the heat treatment process is 30 min to 60 min, including the values ​​at both ends.

6. The method for manufacturing an infrared detector according to claim 5, characterized in that: The thickness of the chromium layer is 200Å~500Å, including the values ​​at both ends; the thickness of the gold layer is 500Å~1000Å, including the values ​​at both ends.

7. An infrared detector, characterized in that: include: An infrared detector prepared by the infrared detector manufacturing method according to any one of claims 1 to 6.

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