Display device

Abstract

The present application provides a display device, including a display panel, a source driver circuit, and a refresh rate control circuit. The display panel includes a gate driver circuit, a first scan line, a second scan line, a data line, a sub-pixel, a gating circuit, and a control line. The display area of ​​the display panel includes multiple sub-display areas. The control line is connected to multiple gating circuits within a sub-display area, and each gating circuit is connected to a first scan line and a second scan line. The refresh rate control circuit outputs multiple refresh rate control signals to the multiple control lines, and the gating circuit inputs or does not input the scan signal transmitted by the first scan line to the second scan line based on the refresh rate control signal. The display panel of the display device provided by the present application has multiple sub-display areas, each of which is independently controlled by the refresh rate control circuit and the gating circuit, and can display at the same or different refresh rates, thereby realizing zoned multi-frequency display of the display device and reducing power consumption.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] In order to achieve higher display quality, the driving frequency and resolution of display devices are getting higher and higher, which leads to the continuous increase in the power consumption of display devices. Therefore, effectively controlling the power consumption of display devices is also a major means of product competition. At present, the application scenarios of display devices are diverse. In scenarios such as live broadcast, online classes, games and chats, users have different requirements for the display frequency of display devices. Although existing display devices can already achieve partition display, the refresh rate of the display device can only be switched to full screen. If some partition interfaces in the display device are displayed at high frequency to ensure the smoothness of the picture, and other partition screens are displayed at low frequency to meet the display requirements, then the overall power consumption of the display device will be greatly reduced. Therefore, how to enable the display device to adapt to various scenarios for partitioned multi-frequency display has become an urgent problem that needs to be solved. Summary of the Invention

[0003] The present application provides a display device to solve the problem in the prior art that display devices cannot perform partitioned multi-frequency display.

[0004] In a first aspect, the present application provides a display device, comprising a display panel, a source driver circuit, and a refresh rate control circuit, wherein the display panel comprises a gate driver circuit, a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, a plurality of sub-pixels, a plurality of gating circuits, and a plurality of control lines, wherein the gate driver circuit is electrically connected to the plurality of first scan lines, the source driver circuit is electrically connected to the plurality of data lines, the refresh rate control circuit is electrically connected to the plurality of control lines, and each sub-pixel is electrically connected to one of the second scan lines and one of the data lines;

[0005] The display area of ​​the display panel includes a plurality of sub-display areas arranged in a direction parallel to the data lines and / or in a direction perpendicular to the data lines, the control line is electrically connected to a plurality of the gating circuits located in one of the sub-display areas, and each of the gating circuits located in the sub-display area is electrically connected to one of the first scan lines and one of the second scan lines;

[0006] The refresh frequency control circuit is configured to generate multiple refresh frequency control signals and output the multiple refresh frequency control signals to the multiple control lines, and the selection circuit is configured to input or not input the scan signal transmitted by the first scan line to the second scan line according to the refresh frequency control signal transmitted by the control line.

[0007] In the display device provided in the present application, the refresh frequency control circuit is configured to control the sub-pixels in the multiple sub-display areas to write data signals at the same refresh frequency according to the multiple refresh frequency control signals, or to control the sub-pixels in at least two sub-display areas to write data signals at different refresh frequencies according to at least two refresh frequency control signals.

[0008] In the display device provided in the present application, the at least two sub-display areas include at least a first sub-display area and a second sub-display area;

[0009] In a case where data signals are written to sub-pixels in at least two of the sub-display areas at different refresh frequencies, a first refresh frequency of data signals to be written to sub-pixels in the first sub-display area is greater than a second refresh frequency of data signals to be written to sub-pixels in the second sub-display area;

[0010] The at least two refresh frequency control signals include a first refresh frequency control signal and a second refresh frequency control signal;

[0011] The refresh frequency control circuit is configured to generate the first refresh frequency control signal and the second refresh frequency control signal, and control the sub-pixels in the first sub-display area and the second sub-display area to write data signals according to the first refresh frequency control signal during the driving cycle of the first frame image, and control the sub-pixels in the first sub-display area to write data signals according to the second refresh frequency control signal during the driving cycle of the second frame image, and control the sub-pixels in the second sub-display area not to write data signals.

[0012] In the display device provided in the present application, the first refresh frequency is equal to twice the second refresh frequency;

[0013] The refresh frequency control circuit is configured to control the sub-pixels in the first sub-display area to write data signals according to the first refresh frequency control signal during the driving cycle of the first frame image and the driving cycle of the second frame image, and to control the sub-pixels in the second sub-display area to write data signals according to the second refresh frequency control signal during the driving cycle of the first frame image, and to control the sub-pixels in the second sub-display area not to write data signals according to the second refresh frequency control signal during the driving cycle of the second frame image.

[0014] In the display device provided in the present application, the first refresh frequency is equal to four times the second refresh frequency;

[0015] The refresh frequency control circuit is configured to control the sub-pixels in the first sub-display area to write data signals according to the first refresh frequency control signal during the driving cycle of the first frame picture, the driving cycle of the second frame picture, the driving cycle of the third frame picture, and the driving cycle of the fourth frame picture, and to control the sub-pixels in the second sub-display area to write data signals according to the second refresh frequency control signal during the driving cycle of the first frame picture, and to control the sub-pixels in the second sub-display area not to write data signals according to the second refresh frequency control signal during the driving cycle of the second frame picture, the driving cycle of the third frame picture, and the driving cycle of the fourth frame picture.

[0016] In the display device provided in the present application, the multiple control lines include multiple first control lines, and the multiple first control lines are arranged in a direction perpendicular to the data lines. The refresh frequency control circuit is electrically connected to the multiple first control lines. The selection circuit includes a first transistor, one of the source and the drain of the first transistor is electrically connected to the first scan line, and the other of the source and the drain of the first transistor is electrically connected to the second scan line. One of the first control lines is electrically connected to the gates of the multiple first transistors located in one of the sub-display areas. The sub-pixel includes a third transistor, the gate of the third transistor is electrically connected to the second scan line, one of the source and the drain of the third transistor is electrically connected to the data line, and the other of the source and the drain of the third transistor is electrically connected to the pixel electrode of the sub-pixel.

[0017] In the display device provided in the present application, the multiple control lines also include multiple second control lines, the multiple second control lines are arranged in a direction perpendicular to the data lines, the refresh frequency control circuit is electrically connected to the multiple second control lines, the selection circuit also includes a second transistor, one of the source and the drain of the second transistor is electrically connected to the low-level signal input end of the display panel, the other of the source and the drain of the second transistor is electrically connected to the second scan line, and one second control line is electrically connected to the gates of the multiple second transistors located in one of the sub-display areas.

[0018] In the display device provided in the present application, when the first transistor is turned on, the second transistor is turned off; or

[0019] When the first transistor is turned off, the second transistor is turned on; or

[0020] When the first transistor is turned off, the second transistor is turned off.

[0021] In the display device provided in the present application, during a driving period of the first frame, the scanning signal transmitted by the second scanning line located in the first sub-display area is the scanning signal transmitted by the first scanning line located in the first sub-display area, and the scanning signal transmitted by the second scanning line located in the second sub-display area is the scanning signal transmitted by the first scanning line located in the second sub-display area;

[0022] During the driving period of the second frame, the scanning signal transmitted by the second scanning line located in the first sub-display area is the scanning signal transmitted by the first scanning line located in the first sub-display area, and the scanning signal transmitted by the second scanning line located in the second sub-display area is the low-level signal transmitted by the low-level signal input end.

[0023] In the display device provided in the present application, when at least two of the sub-display areas are arranged in a direction perpendicular to the data line, the two second scan lines electrically connected to the sub-pixels in the same row in one of the at least two sub-display areas are insulated.

[0024] The beneficial effects of the present application are that: the display panel in the display device provided by the present application includes a gate drive circuit, multiple first scan lines, multiple second scan lines, multiple data lines, multiple sub-pixels, multiple gating circuits, and multiple control lines. Compared with conventional display panels, it has multiple sub-display areas in a direction parallel to the data lines and / or in a direction perpendicular to the data lines. In addition, the display device also includes a refresh frequency control circuit, which transmits a refresh frequency control signal to the gating circuit through a control line. Each sub-display area is separately controlled by the refresh frequency control circuit and the gating circuit, so that each sub-display area can be displayed at the same or different refresh rates, thereby realizing the diversification of display images of the display device and reducing the power consumption of the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a display device provided in an embodiment of the present application;

[0026] Figure 2 A circuit diagram of multiple sub-display areas of a display device provided in an embodiment of the present application;

[0027] Figure 3 A timing diagram of multiple sub-display areas and their driving modes of a display device provided in one embodiment of the present application;

[0028] Figure 4 Based on Figure 3 A driving timing diagram of a gate driving signal and a control signal of a display device;

[0029] Figure 5 A timing diagram of multiple sub-display areas and their driving modes of a display device provided in another embodiment of the present application;

[0030] Figure 6 Based on Figure 5 A driving timing diagram of a gate driving signal and a control signal of a display device;

[0031] Figure 7 A timing diagram of multiple sub-display areas and their driving methods of a display device provided in another embodiment of the present application;

[0032] Figure 8 Based on Figure 7 A driving timing diagram of gate driving signals and control signals of a display device. DETAILED DESCRIPTION

[0033] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. The described embodiments are only used to explain the ideas created by the present invention and should not be regarded as limiting the scope of protection of this application.

[0034] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise explicitly and specifically defined.

[0035] The display frequency of existing display devices is usually constant or can only be switched as a whole. It is impossible to partition the display frequency according to the usage scenario and use different refresh rates in each partition for display, resulting in high power consumption of the display device.

[0036] To solve the above problems, Figure 1 As shown, an embodiment of the present application provides a display device, including a display panel, a source driving circuit and a refresh frequency control circuit, the display panel including a gate driving circuit, multiple first scan lines, multiple second scan lines, multiple data lines, multiple sub-pixels, multiple selection circuits, and multiple control lines, the gate driving circuit is electrically connected to the multiple first scan lines, the source driving circuit is electrically connected to the multiple data lines, the refresh frequency control circuit is electrically connected to the multiple control lines, and each of the sub-pixels is electrically connected to one second scan line and one data line.

[0037] The display area of ​​the display panel includes a plurality of sub-display areas arranged in a direction parallel to the data lines and / or in a direction perpendicular to the data lines, the control line is electrically connected to a plurality of the gating circuits located in one of the sub-display areas, and each of the gating circuits located in the sub-display area is electrically connected to one of the first scan lines and one of the second scan lines;

[0038] The refresh frequency control circuit is configured to generate multiple refresh frequency control signals and output the multiple refresh frequency control signals to the multiple control lines, and the selection circuit is configured to input or not input the scan signal transmitted by the first scan line to the second scan line according to the refresh frequency control signal transmitted by the control line.

[0039] Furthermore, the refresh frequency control circuit is configured to control the sub-pixels in the multiple sub-display areas to write data signals at the same refresh frequency according to the multiple refresh frequency control signals, or to control the sub-pixels in at least two sub-display areas to write data signals at different refresh frequencies according to at least two refresh frequency control signals.

[0040] Through the above settings, the display area of ​​the display panel can be divided according to the usage scenario of the display device and the refresh rate, and each sub-display area can be individually controlled by the driver, thereby reducing the burden on the display screen and reducing the power consumption of the display device.

[0041] On this basis, the at least two sub-display areas include at least a first sub-display area and a second sub-display area. Wherein, when the display panel writes data signals to sub-pixels in the at least two sub-display areas at different refresh frequencies, a first refresh frequency of the data signals to be written to the sub-pixels in the first sub-display area is greater than a second refresh frequency of the data signals to be written to the sub-pixels in the second sub-display area.

[0042] Furthermore, at least two of the refresh frequency control signals include a first refresh frequency control signal and a second refresh frequency control signal; the refresh frequency control circuit is configured to generate the first refresh frequency control signal and the second refresh frequency control signal, and control the sub-pixels in the first sub-display area and the second sub-display area to write data signals according to the first refresh frequency control signal during the driving cycle of the first frame image, and control the sub-pixels in the first sub-display area to write data signals according to the second refresh frequency control signal during the driving cycle of the second frame image, and control the sub-pixels in the second sub-display area not to write data signals.

[0043] like Figure 1As shown, in one embodiment of the present application, the display area is divided into sub-display area A, sub-display area B, sub-display area C, and sub-display area D in the first scanning direction, and each sub-display area is controlled by an independent data control line SWA1 / 2, SWB1 / 2, SWC1 / 2, and SWD1 / 2, respectively.

[0044] It should be noted that in some embodiments of the present application, the first refresh frequency and the second refresh frequency usually maintain a multiple relationship, specifically: the first refresh frequency is equal to twice the second refresh frequency, or the first refresh frequency is equal to four times the second refresh frequency.

[0045] In which, when the first refresh frequency is equal to twice the second refresh frequency, the refresh frequency control circuit is configured to control the sub-pixels in the first sub-display area to write data signals according to the first refresh frequency control signal during the driving period of the first frame image and the driving period of the second frame image that are consecutive in time, and to control the sub-pixels in the second sub-display area to write data signals according to the second refresh frequency control signal during the driving period of the first frame image, and to control the sub-pixels in the second sub-display area not to write data signals according to the second refresh frequency control signal during the driving period of the second frame image.

[0046] Further, when the first refresh frequency is equal to four times the second refresh frequency, the refresh frequency control circuit is configured to control the sub-pixels in the first sub-display area to write data signals according to the first refresh frequency control signal during the driving period of the first frame picture, the driving period of the second frame picture, the driving period of the third frame picture, and the driving period of the fourth frame picture that are consecutive in time, and to control the sub-pixels in the second sub-display area to write data signals according to the second refresh frequency control signal during the driving period of the first frame picture, and to control the sub-pixels in the second sub-display area not to write data signals according to the second refresh frequency control signal during the driving period of the second frame picture, the driving period of the third frame picture, and the driving period of the fourth frame picture.

[0047] like Figure 2As shown, in some embodiments of the display panel of the present application, each sub-pixel includes a driving transistor, a liquid crystal capacitor, a storage capacitor, and a control module; wherein the control module is electrically connected to the control signal line, the scan line, and the gate of the driving transistor, the source of the driving transistor is electrically connected to the data line, the drain of the driving transistor is connected to one end of the liquid crystal capacitor and the storage capacitor, and the other end of the liquid crystal capacitor and the storage capacitor is connected to a common electrode. The multiple control lines include multiple first control lines, the multiple first control lines are arranged in a direction perpendicular to the data lines, and the refresh rate control circuit is electrically connected to the multiple first control lines.

[0048] Furthermore, the selection circuit includes a first transistor, one of the source and the drain of the first transistor is electrically connected to the first scan line, the other of the source and the drain of the first transistor is electrically connected to the second scan line, a first control line is electrically connected to the gates of multiple first transistors located in a sub-display area, the sub-pixel includes a third transistor, the gate of the third transistor is electrically connected to the second scan line, one of the source and the drain of the third transistor is electrically connected to the data line, and the other of the source and the drain of the third transistor is electrically connected to the pixel electrode of the sub-pixel.

[0049] Furthermore, the plurality of control lines also include a plurality of second control lines, the plurality of second control lines are arranged in a direction perpendicular to the data lines, the refresh frequency control circuit is electrically connected to the plurality of second control lines, the selection circuit also includes a second transistor, one of the source and the drain of the second transistor is electrically connected to the low-level signal input end of the display panel, the other of the source and the drain of the second transistor is electrically connected to the second scan line, and one of the second control lines is electrically connected to the gates of the plurality of second transistors located in one of the sub-display areas.

[0050] It should be noted that in the above embodiment, when the first transistor is turned on, the second transistor is turned off; or when the first transistor is turned off, the second transistor is turned on; or when the first transistor is turned off, the second transistor is turned off. That is, only one of the first and second transistors is turned on at the same time to achieve the selection of the scanning signal. Specifically, the selection of the scanning signal in this application is as follows:

[0051] During the driving period of the first frame, the scanning signal transmitted by the second scanning line located in the first sub-display area is the scanning signal transmitted by the first scanning line located in the first sub-display area, and the scanning signal transmitted by the second scanning line located in the second sub-display area is the scanning signal transmitted by the first scanning line located in the second sub-display area;

[0052] During the driving period of the second frame, the scanning signal transmitted by the second scanning line located in the first sub-display area is the scanning signal transmitted by the first scanning line located in the first sub-display area, and the scanning signal transmitted by the second scanning line located in the second sub-display area is the low-level signal transmitted by the low-level signal input end.

[0053] When at least two of the sub-display areas are arranged in a direction perpendicular to the data lines, two second scan lines electrically connected to the sub-pixels in the same row in one of the at least two sub-display areas are insulated.

[0054] Reference Figure 2 , taking the display area as divided into three sub-display areas in the first scanning direction as an example, to achieve independent control of the refresh rate of each sub-display area, the data control signals of sub-display area A are SWA1 and SWA2, the data control signals of sub-display area B are SWB1 and SWB2, and the data control signals of sub-display area C are SWC1 and SWC2; the gate lines and control signals are screened by the control module to select the gate lines gate1A, gate1B, and gate1C corresponding to the display partitions; the display frequencies of display areas A, B, and C are controlled by the frequencies of SWA1, SWA2, SWB1, SWB2, SWC1, and SWC2.

[0055] In addition, the present application also includes a timing control circuit, which is electrically connected to the gate drive circuit and the source drive circuit, and the timing control circuit is used to control the output duration of the control signal to determine the refresh rate of each sub-display area. In the driving timing of the timing control circuit, the clock signal is shifted through the gate drive circuit, and gate drive signals such as gate1 and gate2 are output in sequence. The corresponding data signals data1~dataM*N in the pixel circuit are combined with the output of the gate drive circuit to write the node N in the sub-pixel (that is, the connection point between the driving transistor and the liquid crystal capacitor and the storage capacitor) in sequence, that is, the gate of the driving transistor is turned on after receiving the gate drive signal, and the node N is written into the potential N1~N1,M*N.

[0056] In some embodiments of the present application, in order to achieve different refresh rates for each sub-display area of ​​the display panel, taking the refresh rate control in one sub-display area as an example, the driving method of the present application is as follows:

[0057] When the display screen is displayed at the maximum refresh rate A, in the N-1 frame, the N frame, the N+1 frame and the N+2 frame, the gate of each of the first transistors receives a high-level drive signal, and the gate of each of the second transistors receives a low-level drive signal; wherein N is a positive integer and a multiple of 2, and A>0.

[0058] When the display screen is displayed at a refresh rate of A / 2, in the N-1 frame and the N+1 frame, the gate of each of the first transistors receives a high-level drive signal, and the gate of each of the second transistors receives a low-level drive signal; in the N frame and the N+2 frame, the gate of each of the first transistors receives a low-level drive signal, and the gate of each of the second transistors receives a high-level drive signal.

[0059] When the display screen is displayed at a refresh rate of A / 4, in the N-1 frame, the gate of each of the first transistors receives a high-level drive signal, and the gate of each of the second transistors receives a low-level drive signal; in the N frame, the N+1 frame and the N+2 frame, the gate of each of the first transistors receives a low-level drive signal, and the gate of each of the second transistors receives a high-level drive signal.

[0060] In which, when the signal received by the gate of the first transistor is a high-level driving signal and the signal received by the gate of the second transistor is a low-level driving signal, the gate of the driving transistor in each of the sub-pixels receives the signal from the scan line; when the signal received by the gate of the first transistor is a low-level driving signal and the signal received by the gate of the second transistor is a high-level driving signal, the signal received by the gate of the driving transistor in each of the sub-pixels is a low-level driving signal.

[0061] Based on the above solution, this application provides several specific embodiments. In these embodiments, the display area of ​​the display panel is divided into three sub-display areas, as follows:

[0062] Example 1

[0063] like Figure 3 As shown in (a), the display panel is divided into three sub-display areas A, B, and C from left to right in the second scanning direction, where the refresh rate of sub-display area A is 120HZ, the refresh frequency of sub-display area B is 120Hz, and the refresh frequency of sub-display area C is 120Hz.

[0064] like Figure 3 (b) and Figure 4As shown, to achieve the above refresh rate, the corresponding selection control signal state is as follows:

[0065] In the N-1th frame, in each sub-display area, the control signals SWA1 / SWB1 / SWC1 received by the gates of the first transistors are all high-level drive signals VGH, and the control signals SWA2 / SWB2 / SWC2 received by the gates of the second transistors are all low-level drive signals VGL. At this time, the drive signals gate1A, gate1B, and gate1C received by the drive transistors connected to the scan line gate1 are all equal to the gate drive signals transmitted by gate1, and the drive signals gate2A, gate2B, and gate2C received by the drive transistors connected to the scan line gate2 are all equal to the gate drive signals of gate2.

[0066] In the Nth frame, in each sub-display area, the control signals SWA1 / SWB1 / SWC1 received by the gates of the first transistors are all high-level drive signals VGH, and the control signals SWA2 / SWB2 / SWC2 received by the gates of the second transistors are all low-level drive signals VGL. At this time, the drive signals gate1A, gate1B, and gate1C received by the drive transistors connected to the scan line gate1 are all equal to the gate drive signals transmitted by gate1, and the drive signals gate2A, gate2B, and gate2C received by the drive transistors connected to the scan line gate2 are all equal to the gate drive signals of gate2.

[0067] In the (N+1)th frame, in each sub-display area, the control signals SWA1 / SWB1 / SWC1 received by the gates of the first transistors are all high-level drive signals VGH, and the control signals SWA2 / SWB2 / SWC2 received by the gates of the second transistors are all low-level drive signals VGL. At this time, the drive signals gate1A, gate1B, and gate1C received by the drive transistors connected to the scan line gate1 are all equal to the gate drive signals transmitted by gate1, and the drive signals gate2A, gate2B, and gate2C received by the drive transistors connected to the scan line gate2 are all equal to the gate drive signals of gate2.

[0068] In the N+2th frame, in each sub-display area, the control signal SWA1 / SWB1 / SWC1 received by the gate of the first transistor is the high-level drive signal VGH, and the control signal SWA2 / SWB2 / SWC2 received by the gate of the second transistor is the low-level drive signal VGL. At this time, the drive signals gate1A, gate1B, and gate1C received by the drive transistor connected to the scan line gate1 are all equal to the gate drive signal transmitted by gate1, and the drive signals gate2A, gate2B, and gate2C received by the drive transistor connected to the scan line gate2 are all equal to the gate drive signal of gate2.

[0069] In this embodiment, in the N-1th frame, the Nth frame, the N+1th frame, and the N+2th frame, the refresh rates of the sub-display areas are the same, so that the refresh rate of the display area of ​​the entire display panel can be maintained at 120HZ.

[0070] Example 2

[0071] like Figure 5 As shown in (a), the display panel is divided into three sub-display areas A, B, and C from top to bottom in the first scanning direction, where the refresh rate of sub-display area A is 60HZ, the refresh frequency of sub-display area B is 120Hz, and the refresh frequency of sub-display area C is 30Hz.

[0072] like Figure 5 (b) and Figure 6 As shown, to achieve the above refresh rate, the corresponding selection control signal state is as follows:

[0073] In the N-1th frame, in each sub-display area, the control signal SWA1 / SWB1 / SWC1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWA2 / SWB2 / SWC2 received by the gate of the second transistor is a low-level drive signal VGL. At this time, the drive signals gate1A, gate1B, and gate1C received by the drive transistor connected to the scan line gate1 are all equal to the gate drive signal transmitted by gate1, and the drive signals gate2A, gate2B, and gate2C received by the drive transistor connected to the scan line gate2 are all equal to the gate drive signal of gate2.

[0074] In the Nth frame, in the sub-display area A, the control signal SWA1 received by the gate of the first transistor is a low-level drive signal VGL, and the control signal SWA2 received by the gate of the second transistor is a high-level drive signal VGH; in the sub-display area B, the control signal SWB1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWB2 received by the gate of the second transistor is a low-level drive signal VGL; in the sub-display area C, the control signal SWC1 received by the gate of the first transistor is a low-level drive signal VGL, and the control signal SWC2 received by the gate of the second transistor is a high-level drive signal VGH; at this time, the drive transistor connected to the scan line gate1 receives the drive signal gate1A=gate1C=VGL, gate1B=gate1, and the drive transistor connected to the scan line gate2 receives the drive signal gate2A=gate2C=VGL, gate2B=gate2.

[0075] In the N+1th frame, in the sub-display area A, the control signal SWA1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWA2 received by the gate of the second transistor is a low-level drive signal VGL; in the sub-display area B, the control signal SWB1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWB2 received by the gate of the second transistor is a low-level drive signal VGL; in the sub-display area C, the control signal SWC1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWC2 received by the gate of the second transistor is a low-level drive signal VGL; at this time, the drive transistor connected to the scan line gate1 receives the drive signal gate1A=gate1B=gate1, gate1C=VGL, and the drive transistor connected to the scan line gate2 receives the drive signal gate2A=gate2B=gate2, gate2C=VGL.

[0076] In the N+2th frame, in the sub-display area A, the control signal SWA1 received by the gate of the first transistor is the low-level drive signal VGL, and the control signal SWA2 received by the gate of the second transistor is the high-level drive signal VGH; in the sub-display area B, the control signal SWB1 received by the gate of the first transistor is the high-level drive signal VGH, and the control signal SWB2 received by the gate of the second transistor is the low-level drive signal VGL; in the sub-display area C, the control signal SWC1 received by the gate of the first transistor is the low-level drive signal VGL, and the control signal SWC2 received by the gate of the second transistor is the high-level drive signal VGH; at this time, the drive transistor connected to the scan line gate1 receives the drive signal gate1A=gate1C=VGL, gate1B=gate1, and the drive transistor connected to the scan line gate2 receives the drive signal gate2A=gate2C=VGL, gate2B=gate2.

[0077] In this embodiment, through driving control in the N-1th frame, the Nth frame, the N+1th frame, and the N+2th frame, the refresh rate of the sub-display area A is 60HZ, the refresh rate of the sub-display area B is 120HZ, and the refresh rate of the sub-display area C is 30HZ, that is, the refresh rates of the various display areas are different.

[0078] Example 3

[0079] like Figure 7 As shown in (a), the display panel is divided into three sub-display areas A, B, and C from top to bottom in the second scanning direction, where the refresh rate of sub-display area A is 120HZ, the refresh frequency of sub-display area B is 120Hz, and the refresh frequency of sub-display area C is 120Hz.

[0080] like Figure 7 (b) and Figure 8 As shown, to achieve the above refresh rate, the corresponding selection control signal state is as follows:

[0081] In the N-1th frame, in each sub-display area, the control signal SWA1 / SWB1 / SWC1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWA2 / SWB2 / SWC2 received by the gate of the second transistor is a low-level drive signal VGL. At this time, the drive signals gate1A, gate1B, and gate1C received by the drive transistor connected to the scan line gate1 are all equal to the gate drive signal transmitted by gate1, and the drive signals gate2A, gate2B, and gate2C received by the drive transistor connected to the scan line gate2 are all equal to the gate drive signal of gate2.

[0082] In the Nth frame, in the sub-display area A, the control signal SWA1 received by the gate of the first transistor is a low-level drive signal VGL, and the control signal SWA2 received by the gate of the second transistor is a high-level drive signal VGH; in the sub-display area B, the control signal SWB1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWB2 received by the gate of the second transistor is a low-level drive signal VGL; in the sub-display area C, the control signal SWC1 received by the gate of the first transistor is a low-level drive signal VGL, and the control signal SWC2 received by the gate of the second transistor is a high-level drive signal VGH; at this time, the drive transistor connected to the scan line gate1 receives the drive signal gate1A=gate1C=VGL, gate1B=gate1, and the drive transistor connected to the scan line gate2 receives the drive signal gate2A=gate2C=VGL, gate2B=gate2.

[0083] In the N+1th frame, in the sub-display area A, the control signal SWA1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWA2 received by the gate of the second transistor is a low-level drive signal VGL; in the sub-display area B, the control signal SWB1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWB2 received by the gate of the second transistor is a low-level drive signal VGL; in the sub-display area C, the control signal SWC1 received by the gate of the first transistor is a high-level drive signal VGH, and the control signal SWC2 received by the gate of the second transistor is a low-level drive signal VGL; at this time, the drive transistor connected to the scan line gate1 receives the drive signal gate1A=gate1B=gate1C=gate1, and the drive transistor connected to the scan line gate2 receives the drive signal gate2A=gate2B=gate2C=gate2.

[0084] In the N+2th frame, in the sub-display area A, the control signal SWA1 received by the gate of the first transistor is the low-level drive signal VGL, and the control signal SWA2 received by the gate of the second transistor is the high-level drive signal VGH; in the sub-display area B, the control signal SWB1 received by the gate of the first transistor is the high-level drive signal VGH, and the control signal SWB2 received by the gate of the second transistor is the low-level drive signal VGL; in the sub-display area C, the control signal SWC1 received by the gate of the first transistor is the low-level drive signal VGL, and the control signal SWC2 received by the gate of the second transistor is the high-level drive signal VGH; at this time, the drive transistor connected to the scan line gate1 receives the drive signal gate1A=gate1C=VGL, gate1B=gate1, and the drive transistor connected to the scan line gate2 receives the drive signal gate2A=gate2C=VGL, gate2B=gate2.

[0085] In this embodiment, through driving control in the N-1th frame, the Nth frame, the N+1th frame, and the N+2th frame, the refresh rate of the sub-display area A is 60HZ, the refresh rate of the sub-display area B is 120HZ, and the refresh rate of the sub-display area C is 60HZ, that is, the refresh rates of the various display areas are partially the same.

[0086] Of course, the present application may have many other embodiments. Without departing from the spirit and essential points of the present application, technicians familiar with the field may make various corresponding changes and modifications based on the present application, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present application.

Claims

1. A display device, characterized in that: The display device includes a display panel, a source driver circuit, and a refresh rate control circuit. The display panel includes a gate driver circuit, a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, a plurality of sub-pixels, a plurality of gating circuits, and a plurality of control lines. The gate driver circuit is electrically connected to the plurality of first scan lines, the source driver circuit is electrically connected to the plurality of data lines, the refresh rate control circuit is electrically connected to the plurality of control lines, and each sub-pixel is electrically connected to one of the second scan lines and one of the data lines. The display area of ​​the display panel includes a plurality of sub-display areas arranged in a direction parallel to the data lines and / or in a direction perpendicular to the data lines, the control line is electrically connected to a plurality of the gating circuits located in one of the sub-display areas, and each of the gating circuits located in the sub-display area is electrically connected to one of the first scan lines and one of the second scan lines; The refresh frequency control circuit is configured to generate a plurality of refresh frequency control signals and output the plurality of refresh frequency control signals to the plurality of control lines, and the gating circuit is configured to input or not input the scan signal transmitted by the first scan line to the second scan line according to the refresh frequency control signals transmitted by the control lines; The refresh frequency control circuit is configured to control the sub-pixels in the plurality of sub-display areas to write data signals at the same refresh frequency according to the plurality of refresh frequency control signals, or to control the sub-pixels in at least two sub-display areas to write data signals at different refresh frequencies according to at least two refresh frequency control signals; The at least two sub-display areas include at least a first sub-display area and a second sub-display area; In a case where data signals are written to sub-pixels in at least two of the sub-display areas at different refresh frequencies, a first refresh frequency of data signals to be written to sub-pixels in the first sub-display area is greater than a second refresh frequency of data signals to be written to sub-pixels in the second sub-display area; The at least two refresh frequency control signals include a first refresh frequency control signal and a second refresh frequency control signal; The refresh frequency control circuit is configured to generate the first refresh frequency control signal and the second refresh frequency control signal, and control the sub-pixels in the first sub-display area and the second sub-display area to write data signals according to the first refresh frequency control signal during a driving period of a first frame image, and control the sub-pixels in the first sub-display area to write data signals according to the second refresh frequency control signal during a driving period of a second frame image, and control the sub-pixels in the second sub-display area not to write data signals; The plurality of control lines include a plurality of first control lines, the plurality of first control lines are arranged in a direction perpendicular to the data lines, the refresh frequency control circuit is electrically connected to the plurality of first control lines, the gating circuit includes a first transistor, one of a source and a drain of the first transistor is electrically connected to the first scan line, the other of the source and the drain of the first transistor is electrically connected to the second scan line, one of the first control line is electrically connected to the gates of the plurality of first transistors located in one of the sub-display areas, the sub-pixel includes a third transistor, the gate of the third transistor is electrically connected to the second scan line, one of the source and the drain of the third transistor is electrically connected to the data line, and the other of the source and the drain of the third transistor is electrically connected to the pixel electrode of the sub-pixel; The plurality of control lines further include a plurality of second control lines, the plurality of second control lines being arranged in a direction perpendicular to the data lines, the refresh frequency control circuit being electrically connected to the plurality of second control lines, the gating circuit further including a second transistor, one of a source and a drain of the second transistor being electrically connected to a low-level signal input terminal of the display panel, the other of a source and a drain of the second transistor being electrically connected to the second scan line, and one second control line being electrically connected to gates of the plurality of second transistors located in one of the sub-display areas; During the driving period of the first frame, the scanning signal transmitted by the second scanning line located in the first sub-display area is the scanning signal transmitted by the first scanning line located in the first sub-display area, and the scanning signal transmitted by the second scanning line located in the second sub-display area is the scanning signal transmitted by the first scanning line located in the second sub-display area; During the driving period of the second frame, the scanning signal transmitted by the second scanning line located in the first sub-display area is the scanning signal transmitted by the first scanning line located in the first sub-display area, and the scanning signal transmitted by the second scanning line located in the second sub-display area is the low-level signal transmitted by the low-level signal input end.

2. The display device according to claim 1, wherein The first refresh frequency is equal to twice the second refresh frequency; The refresh frequency control circuit is configured to control the sub-pixels in the first sub-display area to write data signals according to the first refresh frequency control signal during the driving cycle of the first frame image and the driving cycle of the second frame image, and to control the sub-pixels in the second sub-display area to write data signals according to the second refresh frequency control signal during the driving cycle of the first frame image, and to control the sub-pixels in the second sub-display area not to write data signals according to the second refresh frequency control signal during the driving cycle of the second frame image.

3. The display device according to claim 1, wherein The first refresh frequency is equal to four times the second refresh frequency; The refresh frequency control circuit is configured to control the sub-pixels in the first sub-display area to write data signals according to the first refresh frequency control signal during the driving cycle of the first frame picture, the driving cycle of the second frame picture, the driving cycle of the third frame picture, and the driving cycle of the fourth frame picture, and to control the sub-pixels in the second sub-display area to write data signals according to the second refresh frequency control signal during the driving cycle of the first frame picture, and to control the sub-pixels in the second sub-display area not to write data signals according to the second refresh frequency control signal during the driving cycle of the second frame picture, the driving cycle of the third frame picture, and the driving cycle of the fourth frame picture.

4. The display device according to claim 1, wherein When the first transistor is turned on, the second transistor is turned off; or When the first transistor is turned off, the second transistor is turned on; or When the first transistor is turned off, the second transistor is turned off.

5. The display device according to claim 1, wherein When at least two of the sub-display areas are arranged in a direction perpendicular to the data lines, two second scan lines electrically connected to the sub-pixels in the same row in one of the at least two sub-display areas are insulated.

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