A driving circuit, LIN bus and driving method

Abstract

The present invention provides a driving circuit, a LIN bus and a driving method, comprising: a driving module and a feedback acceleration module; the input end of the driving module receives a transmission signal and generates a level control signal, the output end is connected to the output port of the driving circuit, and provides an explicit level or a recessive level for the output port according to the level control signal; the input end of the feedback acceleration module is connected to the output end of the driving module, and provides an acceleration voltage for the output signal of the driving circuit according to the level state of the transmission signal. By setting the feedback acceleration module, the present invention can accelerate the time for the driving circuit to conduct current or shut down current, can effectively reduce the delay of the rising edge and the falling edge of the output signal, can improve the duty cycle of the output signal, and ensure the timeliness of the response of the driving circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a driving circuit, a LIN bus and a driving method. Background Art

[0002] LIN (Local Interconnect Network) is a serial communication network defined for automotive distributed electronic systems. The LIN bus system is equipped with multiple nodes. Due to physical layer limitations, a LIN network can connect up to 16 nodes. Typical applications are generally less than 12 nodes. One of the nodes is set as the LIN master node. There is only one LIN master node, and the remaining nodes can be set as slave nodes. There can be 1 to 15 slave nodes. The LIN master node exchanges data with each LIN slave node by transmitting signals. Among them, if all nodes do not drive the transceiver transistor to turn on, the voltage on the LIN data bus is the battery voltage, which is a recessive level, indicating a logic "1". When a node needs to send information to the outside, the transceiver driving transistor in the sending control unit is turned on, and the LIN data bus wire is grounded. At this time, the voltage on the LIN bus is 0V, which is a dominant level indicating a logic "0". Each node receives and adjusts the level state of each node by setting a driving circuit, so that each node can perform tasks according to the transmission signal requirements.

[0003] However, the current driving circuit has a poor duty cycle symmetry of the output signal, that is, the driving circuit responds slowly, resulting in a long delay in the transmission of each signal.

[0004] Based on the above reasons, the present invention proposes a driving circuit, a LIN bus and a driving method, which reduce the duty cycle of the output signal of the driving circuit and ensure the timeliness of the output circuit response.

[0005] Note that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a driving circuit, a LIN bus and a driving method, which are used to solve the problems of poor symmetry of duty cycle of output signal of the driving circuit and slow response in the prior art.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a driving circuit, including: a driving module and a feedback acceleration module;

[0008] The input end of the driving module receives the transmission signal and generates a level control signal, and the output end is connected to the output port of the driving circuit, and provides a dominant level or a recessive level for the output port according to the level control signal;

[0009] The input end of the feedback acceleration module is connected to the output end of the driving module, and provides an acceleration voltage for the output signal of the driving circuit according to the level state of the sending signal.

[0010] Optionally, the driving module includes a level control signal generating unit and an output unit; the input end of the level control signal generating unit is connected to the sending signal, and the output end is connected to the input end of the output unit, the level state of the sending signal is determined and the level control signal is transmitted and generated; the output end of the output unit is connected to the output port of the driving circuit, when the level control signal is at a high level, a dominant level is provided to the output port of the driving circuit; when the level control signal generating unit is at a low level, a recessive level is provided to the output port of the driving circuit.

[0011] Optionally, the level control signal generating unit includes a first pull-up circuit and a first pull-down circuit; the control end of the first pull-up circuit is connected to the sending signal, the input end is connected to the first supply voltage, and the output end is connected to the input end of the output unit; the control end of the first pull-down circuit is connected to the sending signal, the input end is grounded, and the output end is connected to the input end of the output unit.

[0012] Optionally, the driving module also includes a slope buffer unit; the slope buffer unit includes a first resistor, a capacitor, a second NMOS tube and a buffer; the first end of the first resistor is connected to the first supply voltage, and the second end is connected to the drain of the second NMOS tube; the first plate of the capacitor is simultaneously connected to the connection node of the first pull-up circuit and the first pull-down circuit and the gate of the second NMOS tube, and the second plate is connected to the drain of the second NMOS tube; the source of the second NMOS tube is grounded; the positive input end of the buffer is connected to the gate of the second NMOS tube, and the negative input end is simultaneously connected to the output end of the buffer and the input end of the output unit.

[0013] Optionally, the output unit includes a second resistor, a first diode, a second diode and a first NMOS tube; the gate of the first NMOS tube is connected to the level control signal, the source is grounded, and the drain is connected to the cathode of the first diode; the anode of the first diode is connected to the cathode of the second diode and the output port of the drive circuit; the anode of the second diode is connected to the first end of the second resistor; and the second end of the second resistor is connected to the second supply voltage.

[0014] Optionally, the feedback acceleration module includes a detection unit and a feedback control unit; the input end of the detection unit is connected to the output end of the driving module, and the output end is connected to the control end of the feedback control unit, and a first feedback control signal and a second feedback control signal are provided to the feedback control unit according to the output signal of the driving module; the first feedback control signal is opposite to the second feedback control signal; the output end of the feedback control unit is connected to the level control signal; when the control end of the feedback control unit receives the first feedback control signal as a high level, an explicit level acceleration voltage is provided to the output port of the driving circuit; when the control end of the feedback control unit receives the first feedback control signal as a low level, a recessive level acceleration voltage is provided to the output port of the driving circuit.

[0015] Optionally, the detection unit includes a first current mirror, a Schmitt trigger, an inverter, an AND gate and an OR gate; the input side of the first current mirror is connected to the output end of the driving module, and the output side of the second current mirror is connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the input end of the inverter; the first input end of the OR gate is connected to the input of the sending signal, the second input end is connected to the output end of the inverter IN, and the output end outputs the first feedback control signal; the first input end of the AND gate is connected to the input of the sending signal, the second input end is connected to the output end of the inverter IN, and the output end outputs the second feedback control signal.

[0016] Optionally, the first current mirror includes a third diode, a third resistor, a fourth resistor, a first PMOS tube and a second PMOS tube; the cathode of the third diode is connected to the output end of the driving module, and the anode is connected to the first end of the third resistor; the second end of the third resistor is connected to the drain of the first PMOS tube; the source of the first PMOS tube is connected to the third power supply voltage, and the gate is connected to the drain; the source of the second PMOS tube is connected to the third power supply voltage, the gate is connected to the gate of the first PMOS tube, and the drain is connected to the input end of the Schmitt trigger and the first end of the fourth resistor; the second end of the fourth resistor is grounded.

[0017] Optionally, the feedback control unit includes a second pull-up circuit and a second pull-down circuit; the control end of the second pull-up circuit is connected to the first feedback control signal, and the output end is connected to the level control signal; the control end of the second pull-down circuit is connected to the second feedback control signal, and the output end is connected to the level control signal.

[0018] To achieve the above-mentioned purpose and other related purposes, the present invention provides a LIN bus, including: a plurality of nodes; each node is provided with a load device and the above-mentioned drive circuit; each node executes a response according to a signal output by the drive circuit to power the load device.

[0019] To achieve the above object and other related objects, the present invention provides a driving method, which is implemented using the above driving circuit, comprising:

[0020] S1, receiving the transmission signal and generating a level control signal, and providing the dominant level or the invisible level for the output port of the driving circuit according to the level state of the level control signal Recessive level ;

[0021] S2. According to the level state of the transmission signal, provide an acceleration voltage for the output signal of the driving circuit, reduce the output of the dominant level or output the invisible level Recessive level time.

[0022] Optionally, when the receiving transmission signal starts to rise from a low level, the time for the output port of the driving circuit to output the recessive level to the dominant level becomes shorter; when the receiving transmission signal starts to fall from a high level, the output port of the driving circuit to output the dominant level to the recessive level Recessive level The time becomes shorter.

[0023] As described above, a driving circuit, a LIN bus and a driving method of the present invention have the following beneficial effects:

[0024] 1. The drive circuit, LIN bus and drive method of the present invention can accelerate the time for the drive circuit to turn on or off the current by setting a feedback acceleration module, can effectively reduce the delay of the rising edge and the falling edge of the output signal, can improve the duty cycle of the output signal, and ensure the timeliness of the drive circuit response.

[0025] 2. The driving circuit, LIN bus and driving method of the present invention have simple structures and convenient methods, and can be well applied in production and manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 4 is a schematic diagram of a driving circuit according to an embodiment of the present invention.

[0027] Figure 2 Shown is a schematic diagram of the detection unit of the present invention.

[0028] Figure 3 Shown is the circuit timing diagram of the present invention.

[0029] Figure 4FIG. 4 is a schematic diagram of a driving circuit according to another embodiment of the present invention.

[0030] Component number description

[0031] 1. Driving circuit

[0032] 11 Driver Module

[0033] 111 Level control signal generating unit

[0034] 112 Output Units

[0035] 12 Feedback Acceleration Module

[0036] 121 Detection Unit

[0037] 122 Feedback control unit

[0038] 2 Load devices DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] See also Figure 1 to Figure 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0041] Embodiment 1

[0042] like Figure 1 As shown, this embodiment provides a driving circuit 1, including: a driving module 11 and a feedback acceleration module 12.

[0043] Specifically, the input end of the driving module 11 receives the transmission signal TXD and generates a level control signal, and the output end is connected to the output port LIN of the driving circuit 1, and provides a dominant level or a recessive level for the output port LIN of the driving circuit 1 according to the level control signal. In actual use, the output port LIN of the driving circuit 1 usually maintains a high level state as a recessive level. Recessive level, which is represented by a logic value "1"; after changing to a low level, it is a dominant level, which is represented by a logic value "0". In this embodiment, if the transmission signal TXD is a high level, the generated level control signal is a high level, providing a dominant level for the output port LIN; if the transmission signal TXD is a low level, the generated level control signal is a low level, providing a recessive level for the output port LIN. It should be noted that the transmission signal TXD and the generated level control signal change in the same direction in this embodiment, but an inverter can also be connected after the transmission signal TXD to generate a level control signal, in which case the transmission signal TXD and the generated level control signal are opposite.

[0044] More specifically, the driving module 11 includes a level control signal generating unit 111 and an output unit 112. The input end of the level control signal generating unit 111 is connected to the transmission signal TXD, and the output end is connected to the input end of the output unit 112, and the level state of the transmission signal is determined and the level control signal is transmitted to the output unit 112.

[0045] As an example, the level control signal generating unit 111 includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes a first current source I1 and a first switch S1, and the pull-down circuit includes a second current source I2 and a second switch S2. The input end of the first current source I1 is connected to the first power supply voltage VDD, and the output end is connected to the first end of the first switch S1, and the first switch S1 serves as the control end of the pull-up circuit; the second end of the first switch S1 is connected to the first end of the second switch S2; the second end of the second switch S2 is connected to the input end of the second current source I2, and the second switch S2 serves as the control end of the pull-down circuit; the output end of the second current source I2 is grounded. The control end of the pull-up circuit is connected to the transmission signal TXD, the input end is connected to the first power supply voltage VDD, and the output end is connected to the input end of the output unit 112. When the transmission signal TXD is at a high level, the level control signal is at a high level according to the transmission signal TXD, the first switch S1 is turned on, the second switch S2 is turned off, the first current source I1 is turned on, and the level control signal provided to the output unit 112 is at a high level, and at this time, a dominant level is provided to the output port LIN; the control end of the pull-down circuit is connected to the transmission signal TXD, the input end is grounded, and the output end is connected to the input end of the output unit 112. When the transmission signal TXD is at a low level, the first switch S1 is turned off, the second switch S2 is turned on, the second current source I2 is turned on, and the level control signal provided to the output unit 112 is at a low level, and at this time, an invisible level is provided to the output port LIN. Recessive levelIt should be noted that, in this embodiment, the currents of the first current source I1 and the second current source I2 flow in the same direction, and the output end of the second current source I2 is grounded as the input end of the first pull-down circuit. When the control end of the first pull-down circuit (i.e., the second switch S2) is turned on, a pull-down current is provided for the output end of the first pull-down circuit (i.e., the node of the second switch S2 and the first switch S1, that is, the node of the level control signal), and finally a pull-down current is provided for the subsequent current.

[0046] In another embodiment, the driving module 11 further includes a slope buffer unit 113; the slope buffer unit 113 includes a first resistor R1, a capacitor C1, a second NMOS tube NM2 and a buffer BUF. The first end of the first resistor R1 is connected to the first power supply voltage VDD, and the second end is connected to the drain of the second NMOS tube NM2; the first plate of the capacitor C1 is simultaneously connected to the connection node of the first pull-up circuit and the second pull-down circuit and the gate of the second NMOS tube NM2, the second plate is connected to the drain of the second NMOS tube NM2, and the source of the second NMOS tube NM2 is grounded. A capacitor C1 is added between the drain and the gate of the second NMOS tube as a Miller capacitor. The power supply port of the buffer is connected to the first power supply voltage VDD, the ground port is grounded, the positive input end is connected to the gate of the second NMOS tube NM2, and the negative input end is simultaneously connected to the output end of the buffer and the input end of the output unit 112. A slope buffer unit 113 is provided after the level control signal generating unit 111 (i.e., through the Miller capacitor and the buffer BUF) to buffer the slope of the output signal change of the final driving circuit 1 (e.g., Figure 3 As shown): when the level of the input signal TXD rises from a low level, the level of the output signal decreases accordingly, and after decreasing to the first threshold, the level remains stable for a period of time and then decreases; when the level of the input signal TXD decreases from a high level, the level of the output signal increases accordingly, and after increasing to the second threshold, the level remains stable for a period of time and then continues to increase. It should be noted that, in this embodiment, the buffer BUF is configured as an isolation buffer with low output impedance. Setting the slope buffer unit 113 can improve electromagnetic compatibility and prevent electromagnetic interference problems caused by rapid level conversion. The first NMOS tube NM1 and the second NMOS tube NM2 are devices of the same type, and in actual use, they can also be set as PMOS tubes at the same time. In order to facilitate signal detection and calculation, the first NMOS tube NM1 and the second NMOS tube NM2 have the same structure.

[0047] As an example, the output unit 112 includes a second resistor R2, a first diode D1, a second diode D2 and a first NMOS tube NM1; the gate of the first NMOS tube is connected to the level control signal, the source is grounded, and the drain is connected to the cathode of the first diode D1; the cathode of the first diode D1 is connected to the output end of the input detection unit 111, and the anode of the first diode D1 is connected to the cathode of the second diode D2 and the output port of the drive circuit 1; the anode of the second diode D2 is connected to the first end of the second resistor R2; the second end of the second resistor R2 is connected to the second power supply voltage VBAT (VBAT is the external battery power supply voltage). When the gate of the first NMOS tube receives a high level of the level control signal, the first NMOS tube is turned on, and the potential of the output port LIN of the drive circuit 1 is reduced, showing a "dominant level" and a logic value of "0"; when the gate of the first NMOS tube receives a low level of the level control signal, the first NMOS tube is turned off, and the potential of the output port LIN of the drive circuit 1 is maintained at a high potential or increased, showing a "hidden level" and a logic value of "1".

[0048] Specifically, the feedback acceleration module 12 includes a detection unit 121 and a feedback control unit 122 .

[0049] More specifically, if Figure 2 As shown, the input end of the detection unit 121 is connected to the output end of the driving module 11, and the output end is connected to the control end of the feedback control unit 122. According to the output signal of the driving module 11, the first feedback control signal Φ1 and the second feedback control signal Φ2 are provided to the feedback control unit 121; the first feedback control signal Φ1 is opposite to the second feedback control signal Φ2. It should be noted that in this embodiment, two diodes are arranged in front of the output end of the driving module 11, which play a role in limiting the voltage range, but do not change the change trend of the output signal of the driving module 11. Therefore, in this embodiment, the input end of the detection unit 121 can be connected to the negative end of the first diode, or to the positive end of the first diode. In the end, the output signal of the driving module 11 is actually received, and a feedback response is generated according to the signal output by the driving module 11.

[0050] As an example, the detection unit includes a first current mirror, a Schmitt trigger SCH, an inverter IN, an AND gate and an OR gate. In this embodiment, the input side of the first current mirror is connected to the output end of the driving module 11, and the output side of the second current mirror is connected to the input end of the Schmitt trigger SCH, and the level state signal CFB received from the drain of the first NMOS tube is transmitted to the detection unit 121. In fact, the gate of the first NMOS tube receives the level control signal to turn on or off, and the change trend of the gate receiving the level control signal is basically the same as the change trend of the drain. The detection unit 121 is connected to the drain of the first NMOS tube, and can detect the on or off state of the first NMOS tube, and convert the drain current change signal CFB into a voltage signal, and its change trend is consistent with the state of the level control signal received by the gate of the first NMO tube. The output end of the Schmitt trigger SCH is connected to the input end of the inverter IN. The first input end of the OR gate is connected to the sending signal TXD, the second input end is connected to the output end of the inverter IN (that is, the output signal VFB of the reverse end), and the output end outputs the first feedback control signal Φ1. The first input end of the AND gate is connected to the transmission signal TXD, the second input end is connected to the output end of the inverter IN (i.e., the output signal VFB of the reverse end), and the output end outputs the second feedback control signal Φ2. By setting the Schmitt trigger SCH and the inverter, the CFB signal is delayed and reversed to obtain the logic voltage signal VFB. The change trend of the CFB signal is the same as that of the transmission signal TXD, so it is equivalent to delaying and reversing the TXD signal. Through the OR gate and the AND gate, the VFB and TXD signals are logically operated to calculate the first feedback control signal Φ1 and the second feedback control signal Φ2, and the logic values ​​of these two feedback control signals are reversed.

[0051] In this embodiment, the first current mirror includes a third diode D3, a third resistor R3, a fourth resistor R4, a first PMOS transistor PM1 and a second PMOS transistor PM2; the cathode of the third diode D3 is connected to the output end of the driving module 11, and the anode is connected to the first end of the third resistor R3; the second end of the third resistor R3 is connected to the drain of the first PMOS transistor PM1; the source of the first PMOS transistor PM1 is connected to the third power supply voltage VDD. In this embodiment, the first power supply voltage VDD and the third power supply voltage VDD use the same power supply voltage, and the gate is connected to the drain; the source of the second PMOS transistor PM2 is connected to the third power supply voltage, the gate is connected to the gate of the first PMOS transistor PM1, and the drain is connected to the input end of the Schmitt trigger SCH and the first end of the fourth resistor R4; the second end of the fourth resistor R4 is grounded. It should be noted that the fourth resistor R4 device can also be replaced by a pull-down current source.

[0052] More specifically, the output end of the feedback control unit 122 is connected to the level control signal; when the control end of the feedback control unit 122 receives the first feedback control signal Φ1 as a high level, an explicit level acceleration voltage is provided to the output port of the drive circuit; when the control end of the feedback control unit 122 receives the first feedback control signal Φ1 as a low level, a recessive level acceleration voltage is provided to the output port of the drive circuit.

[0053] As an example, the feedback control unit 122 includes a second pull-up circuit and a second pull-down circuit. The second pull-up circuit includes a third current source I3 and a third switch S3, and the second pull-up circuit includes a fourth current source I4 and a fourth switch S4. The third switch S3 and the fourth switch S4 are arranged on both sides of the node where the second pull-up circuit and the second pull-down circuit are connected, and serve as control terminals of the second pull-up circuit and the second pull-down circuit, respectively. The input terminal of the third current source I3 is connected to the third power supply voltage VDD, and the output terminal is connected to the first terminal of the third switch S3; the second terminal of the third switch S3 is connected to the first terminal of the fourth switch S4, and the second terminal of the fourth switch S4 is connected to the input terminal of the fourth current source I4; the output terminal of the fourth current source I4 is grounded. The control terminal of the second pull-up circuit is connected to the first feedback control signal Φ1, and the output terminal is connected to the level control signal. The control terminal of the second pull-down circuit is connected to the second feedback control signal Φ2, and the output terminal is connected to the level control signal. It should be noted that, in the present embodiment, the currents of the third current source I3 and the fourth current source I4 flow in the same direction, and the output end of the fourth current source I4 is grounded as the input end of the second pull-down circuit. When the control end of the second pull-down circuit (i.e., the fourth switch S4) is turned on, a pull-down signal is provided for the output end of the second pull-down circuit (i.e., the node of the third switch S3 and the fourth switch S4, which is also connected to the node of the level control signal), thereby providing a pull-down current for the subsequent current.

[0054] In this embodiment, when the gate of the first NMOS tube NM1 receives a high-level level level control signal, the first NMOS tube NM1 is turned on, and the potential of the output port LIN of the driving circuit 1 is reduced, showing a "dominant level", and the detection unit 121 detects that the drain change signal of the first NMOS tube NM1 is high-level, and outputs the first feedback control signal Φ1 as a high-level. The feedback control unit 122 receives the first feedback control signal Φ1 as a high-level, the third current source I3 is turned on, and the fourth current source I4 is turned off, and a larger current changing to a high potential is provided to the first NMOS tube NM1, that is, the feedback control unit 122 provides a dominant level acceleration voltage to the output port of the driving circuit 1. When the gate start voltage remains unchanged, the current becomes larger, and the time to turn on the first NMOS tube NM1 becomes shorter, which is manifested as the first NMOS tube NM1 being turned on faster, and the slope of the time change of the output signal of the output port LIN from the high level to the low level increases, that is, the time becomes shorter. When the gate of the first NMOS tube NM1 receives a level control signal of low level, the first NMOS tube NM1 is turned off. At this time, the potential of the output port LIN of the driving circuit 1 maintains a high potential or rises to a high potential, showing a "hidden level", and the detection unit 121 detects that the drain change signal of the first NMOS tube NM1 is low level, and then outputs the first feedback control signal Φ1 as a low level. The feedback control unit 122 receives the first feedback control signal Φ1 as a low level, the third current source I3 is turned off, and the fourth current source I4 is turned on, and a larger current changing to a low potential is provided to the gate of the first NMOS tube NM1, that is, the feedback control unit 122 provides a recessive level acceleration voltage to the output port of the driving circuit. When the gate opening voltage remains unchanged, the current becomes larger, and the time to turn off the first NMOS tube NM1 becomes shorter, which is manifested as the first NMOS tube NM1 turning off faster, and the slope of the time change of the output signal of the output port LIN from a low level to a high level increases, that is, the time becomes shorter.

[0055] The present embodiment also provides a LIN bus, which includes a plurality of nodes; each node is provided with a load device 2 and the drive circuit 1 described above. Each node responds according to the signal output by the drive circuit to power the load device 2. In the present embodiment, the load device 2 includes a parallel inductor RL, a parallel capacitor CL and a third diode D3. The positive end of the third diode D3 is connected to the second power supply voltage VBAT, and the negative end is connected to the first end of the parallel capacitor CL. The second end of the parallel capacitor CL is simultaneously connected to the output port LIN of the drive circuit 1 and the first plate of the parallel capacitor CL. The second plate of the parallel capacitor CL is grounded. It should be noted that the setting of the load device 2 in the present embodiment is only for reference. Different loads will be set in actual use, and the load will be driven by the drive circuit to make the load respond.

[0056] This embodiment also provides a driving method, which is implemented using the above-mentioned driving circuit 1, including:

[0057] S1, receiving the transmission signal TXD and generating a level control signal, and providing a dominant level or a recessive level for the output port LIN of the driving circuit 1 according to the level state of the level control signal Recessive level .

[0058] S2. According to the level state of the transmitted signal, an acceleration voltage is provided for the output signal of the driving circuit 1 to reduce the output dominant level or output invisible level. Recessive level time.

[0059] Specifically, when the receiving transmission signal starts to rise from a low level, the time for the output port of the driving circuit 1 to output the recessive level to the dominant level becomes shorter; when the receiving transmission signal starts to fall from a high level, the output port of the driving circuit 1 outputs the dominant level to the recessive level. Recessive level The time becomes shorter.

[0060] Combine the following Figure 1 , Figure 2 as well as Figure 3 , the detailed process of the driving method is described: the level control signal generating unit 111 receives the transmission signal TXD and generates a level control signal. In this embodiment, the level control signal is in the same direction as the transmission signal TXD (in fact, the level control signal and the transmission signal TXD can also be in different directions, which can be set according to specific circumstances in actual use). The level control signal is input to the output unit 112 after passing through the slope buffer unit 113. When the level control signal received by the output unit 112 is at a high level, a dominant level is provided for the output port LIN of the driving circuit 1. When the level control signal received by the output unit 112 is at a low level, a recessive level is provided for the output port LIN of the driving circuit 1. The feedback control module 12 provides an acceleration voltage for the output signal of the driving circuit 1 according to the level state of the transmission signal TXD. In this embodiment, if the level of the transmission signal TXD is at a high level, a dominant level acceleration voltage is provided for the output port LIN of the driving circuit 1; if the level of the transmission signal TXD is at a low level, a recessive level acceleration voltage is provided to the output port LIN of the driving circuit. In fact, when the sending signal drives the output signal of the driving circuit, the feedback control module 12 provides a corresponding acceleration signal for it.

[0061] In such Figure 3In the timing diagram shown, if the transmission signal TXD is at a low level, the output signal VFB of the Schmitt trigger SCH inside the detection unit 121 and the inverter IN is obtained by delaying and reversing the transmission signal TXD. Therefore, when the transmission signal TXD is at a low level, the output signal VFB is at a high level; when the transmission signal TXD triggers the rising edge, the output signal VFB maintains the high level for a short period of time and then starts to trigger the falling edge; when the transmission signal TXD is at a high level, the output signal VFB is at a low level; when the transmission signal TXD triggers the falling edge, the output signal VFB maintains the low level for a short period of time and then starts to trigger the rising edge. The first feedback control signal Φ1 and the first feedback control signal Φ2 are generated according to the AND gate and the OR gate respectively. In this embodiment, the logic value of the first feedback control signal Φ1 is "0" when the transmission signal TXD triggers the falling edge and the output signal VFB maintains the low level for a short period of time, and the other states are logic values ​​"1". In this embodiment, the logic value of the second feedback control signal Φ2 is "1" when the transmission signal TXD triggers a rising edge and the output signal VFB maintains a high level for a short period of time, and is "0" in other states. The feedback control signal is fed back to the feedback control unit 122. When the logic value of the first feedback control signal Φ1 is "1" and the logic value of the second feedback control signal Φ2 is "1", the third current source I3 is turned off and the fourth current source I4 is turned on. At this time, the current of the gate of the second NMOS tube NM2 switching to the low level state becomes larger. Since the second NMOS tube NM2 is provided with the capacitor C1 as the Miller capacitor, the time for the gate voltage VG1 of the second NMOS tube NM2 to reach the voltage state of the first threshold becomes shorter, and then it will maintain a relatively stable period of time and then drop to the final low voltage state again. When the logic value of the first feedback control signal Φ1 is "0" and the logic value of the second feedback control signal Φ2 is "0", the third current source I3 is turned on and the fourth current source I4 is turned off. At this time, the current of the gate of the second NMOS tube NM2 switching to the high level state becomes larger. Since the second NMOS tube NM2 is provided with the capacitor C1 as the Miller capacitor, the time for the gate voltage VG1 of the second NMOS tube NM2 to reach the voltage state of the second threshold state becomes shorter, and then it will maintain a relatively stable period of time and then rise to the final high voltage state again. Although the Miller capacitor is set as a buffer, the time to drive to a certain voltage is shortened (that is, the gate opening or closing voltage of the second NMOS tube NM2 can be reached more quickly), so the signal output by the driving circuit 1 can reach the dominant level or the invisible level more quickly. Recessive level .

[0062] Embodiment 2

[0063] like Figure 4As shown, the basic structure of this embodiment is substantially the same as that of the first embodiment, except that the current sources in the level control signal generating unit 111 and the feedback control unit 122 of this embodiment are arranged differently.

[0064] Specifically, the current source in the level control signal generating unit is set as a MOS tube. In this embodiment, the sending signal TXD is connected to the gate of the third NMOS tube NM3 and the gate of the third PMOS tube PM3 at the same time. A second current mirror is set as the current power supply source of the third NMOS tube NM3 and the third PMOS tube PM3. The second current mirror includes a bias current IB, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a fourth NMOS tube PM4 and a fifth NMOS tube PM5. The drain of the fourth NMOS tube NM4 is connected to the bias current IB, the source is grounded, the gate is connected to the drain and is connected to the gate of the fifth NMOS tube NM5 and the gate of the sixth NMOS tube NM6 at the same time, which is equivalent to the bias current IB and the fourth NMOS tube NM4 constituting the input side of the second current source to power the fifth NMOS tube NM5 and the sixth NMOS tube NM6. The source of the fifth NMOS tube NM5 is grounded, and the drain is connected to the drain of the fourth PMOS tube PM4. The source of the fourth PMOS tube PM4 is connected to the first power supply voltage VDD, and the gate and drain are connected. The gate of the fifth PMOS tube PM5 is connected to the gate of the fourth PMOS tube PM4, the source is connected to the first power supply voltage VDD, and the drain is connected to the source of the third PMOS tube PM3. The drain of the third PMOS tube PM3 is connected to the drain of the third NMOS tube NM3 and the gate of the second NMOS tube NM2. The source of the sixth NMOS tube NM6 is grounded, the gate is connected to the gate of the fourth NMOS tube NM4, and the drain is connected to the source of the third NMOS tube NM3. The sending signal TXD is used as a switch through the gates of the third NMOS tube NM3 and the third PMOS tube PM3 to turn on the third NMOS tube or the third PMOS tube, and the effect achieved is basically the same as the first current source I1 and the second current source I2 in the embodiment, which will not be repeated here.

[0065] Specifically, the current source in the feedback control unit 122 is set as a MOS tube. In this embodiment, the feedback control unit 122 includes a sixth NMOS tube PM6, a seventh NMOS tube PM7, a seventh NMOS tube NM7 and an eighth NMOS tube NM8. The source of the seventh NMOS tube NM7 is grounded, the gate is connected to the gate of the fourth NMOS tube NM4, and the drain of the seventh NMOS tube NM7 is connected to the source of the eighth NMOS tube NM8. The gate of the eighth NMOS tube NM8 is connected to the second feedback control signal Φ2, and the drain is simultaneously connected to the drain of the seventh NMOS tube PM7 and the gate of the second NMOS tube NM2. The source of the sixth NMOS tube PM6 is connected to the first power supply voltage VDD, the gate is connected to the gate of the fourth NMOS tube PM4, and the drain is connected to the source of the seventh NMOS tube PM7. The gate of the seventh NMOS tube PM7 is connected to the first feedback control signal Φ1. The first feedback control signal Φ1 is used to control the on / off of the seventh NMOS transistor PM7 and the second feedback control signal Φ2 is used to control the on / off of the eighth NMOS transistor NM8. The effects achieved are basically the same as those of the third current source I3 and the fourth current source I4 in the embodiment, and are not described in detail here.

[0066] In summary, the present invention provides a driving circuit, a LIN bus and a driving method, including: a driving module and a feedback acceleration module; the input end of the driving module receives a transmission signal and generates a level control signal, and the output end is connected to the output port of the driving circuit, and provides an explicit level or a recessive level for the output port according to the level control signal; the input end of the feedback acceleration module is connected to the output end of the driving module, and provides an acceleration voltage for the output signal of the driving circuit according to the level state of the transmission signal. By setting a feedback acceleration module, the present invention can accelerate the time for the driving circuit to conduct current or shut down current, effectively reduce the delay of the rising edge and the falling edge of the output signal, improve the duty cycle of the output signal, and ensure the timeliness of the response of the driving circuit. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A driving circuit, characterized in that: The driving circuit at least includes: a driving module and a feedback acceleration module; The input end of the driving module receives the transmission signal and generates a level control signal, and the output end is connected to the output port of the driving circuit, and provides a dominant level or a recessive level for the output port according to the level control signal; The input end of the feedback acceleration module is connected to the output end of the driving module, and provides an acceleration voltage for the output signal of the driving circuit according to the level state of the sending signal; Wherein, the driving module includes a level control signal generating unit and an output unit; The control end of the level control signal generating unit is connected to the transmission signal, and the output end is connected to the input end of the output unit, and determines the level state of the transmission signal and transmits it to generate the level control signal; The output end of the output unit is connected to the output port of the driving circuit. When the level control signal is at a high level, a dominant level is provided to the output port of the driving circuit; when the level control signal generating unit is at a low level, a recessive level is provided to the output port of the driving circuit. The feedback acceleration module includes a detection unit and a feedback control unit; The input end of the detection unit is connected to the output end of the driving module, and the output end is connected to the control end of the feedback control unit, and provides the feedback control unit with a first feedback control signal and a second feedback control signal according to the output signal of the driving module; the first feedback control signal is inverse to the second feedback control signal; The output end of the feedback control unit is connected to the level control signal; when the control end of the feedback control unit receives the first feedback control signal as a high level, an explicit level acceleration voltage is provided to the output port of the drive circuit; when the control end of the feedback control unit receives the first feedback control signal as a low level, a recessive level acceleration voltage is provided to the output port of the drive circuit.

2. The driving circuit according to claim 1, characterized in that: The level control signal generating unit includes a first pull-up circuit and a first pull-down circuit; The control end of the first pull-up circuit is connected to the transmission signal, the input end is connected to the first power supply voltage, and the output end is connected to the input end of the output unit; The control end of the first pull-down circuit is connected to the transmission signal, the input end is grounded, and the output end is connected to the input end of the output unit.

3. The driving circuit according to claim 2, characterized in that: The driving module further includes a slope buffer unit; the slope buffer unit includes a first resistor, a capacitor, a second NMOS tube and a buffer; A first end of the first resistor is connected to the first supply voltage, and a second end is connected to the drain of the second NMOS transistor; The first plate of the capacitor is connected to the connection node of the first pull-up circuit and the first pull-down circuit and the gate of the second NMOS transistor, and the second plate is connected to the drain of the second NMOS transistor; The source of the second NMOS tube is grounded; The positive input terminal of the buffer is connected to the gate of the second NMOS tube, and the negative input terminal is connected to the output terminal of the buffer and the input terminal of the output unit at the same time.

4. The driving circuit according to any one of claims 2 to 3, characterized in that: The output unit includes a second resistor, a first diode, a second diode and a first NMOS tube; The gate of the first NMOS tube is connected to the level control signal, the source is grounded, and the drain is connected to the cathode of the first diode; The anode of the first diode is connected to the cathode of the second diode and the output port of the driving circuit; The anode of the second diode is connected to the first end of the second resistor; The second end of the second resistor is connected to a second supply voltage.

5. The driving circuit according to claim 1, characterized in that: The detection unit includes a first current mirror, a Schmitt trigger, an inverter, an AND gate and an OR gate; The input side of the first current mirror is connected to the output end of the driving module, and the output side of the first current mirror is connected to the input end of the Schmitt trigger; The output end of the Schmitt trigger is connected to the input end of the inverter; The first input terminal of the OR gate is connected to input the transmission signal, the second input terminal is connected to the output terminal of the inverter IN, and the output terminal outputs the first feedback control signal; The first input terminal of the AND gate is connected to input the transmission signal, the second input terminal is connected to the output terminal of the inverter IN, and the output terminal outputs the second feedback control signal.

6. The driving circuit according to claim 5, characterized in that: The first current mirror includes a third diode, a third resistor, a fourth resistor, a first PMOS transistor and a second PMOS transistor; The cathode of the third diode is connected to the output end of the driving module, and the anode is connected to the first end of the third resistor; The second end of the third resistor is connected to the drain of the first PMOS tube; The source of the first PMOS tube is connected to a third power supply voltage, and the gate is connected to the drain; The source of the second PMOS tube is connected to the third power supply voltage, the gate is connected to the gate of the first PMOS tube, and the drain is connected to the input end of the Schmitt trigger and the first end of the fourth resistor; A second end of the fourth resistor is grounded.

7. The driving circuit according to claim 6, characterized in that: The feedback control unit includes a second pull-up circuit and a second pull-down circuit; The control end of the second pull-up circuit is connected to the first feedback control signal, and the output end is connected to the level control signal; The control end of the second pull-down circuit is connected to the second feedback control signal, and the output end is connected to the level control signal.

8. A LIN bus, characterized in that: The LIN bus includes a plurality of nodes; each node is provided with a load device and a drive circuit as described in any one of claims 1 to 7; each node executes a response according to a signal output by the drive circuit to supply power to the load device.

9. A driving method, implemented using the driving circuit according to any one of claims 1 to 7, characterized in that: S1, receiving the transmission signal and generating a level control signal, and providing the dominant level or the recessive level for the output port of the driving circuit according to the level state of the level control signal; S2. According to the level state of the transmission signal, provide an acceleration voltage for the output signal of the driving circuit to reduce the time of outputting the dominant level or outputting the recessive level.

10. The driving method according to claim 9, characterized in that: When the receiving transmission signal starts to rise from a low level, the time for the output port of the driving circuit to output the recessive level to a dominant level becomes shorter; When the receiving transmission signal starts to drop from a high level, the time for the output port of the driving circuit to output the dominant level to a recessive level becomes shorter.

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